2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
94 this->fixed_hw_reg
.dw1
.f
= f
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
103 this->fixed_hw_reg
.dw1
.ud
= u
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
112 this->fixed_hw_reg
.dw1
.d
= i
;
115 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
120 this->type
= BRW_REGISTER_TYPE_VF
;
121 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
127 src_reg::src_reg(struct brw_reg reg
)
132 this->fixed_hw_reg
= reg
;
133 this->type
= reg
.type
;
136 src_reg::src_reg(dst_reg reg
)
140 this->file
= reg
.file
;
142 this->reg_offset
= reg
.reg_offset
;
143 this->type
= reg
.type
;
144 this->reladdr
= reg
.reladdr
;
145 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
151 for (int i
= 0; i
< 4; i
++) {
152 if (!(reg
.writemask
& (1 << i
)))
155 swizzles
[next_chan
++] = last
= i
;
158 for (; next_chan
< 4; next_chan
++) {
159 swizzles
[next_chan
] = last
;
162 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
163 swizzles
[2], swizzles
[3]);
169 memset(this, 0, sizeof(*this));
170 this->file
= BAD_FILE
;
171 this->writemask
= WRITEMASK_XYZW
;
179 dst_reg::dst_reg(register_file file
, int reg
)
187 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
194 this->type
= brw_type_for_base_type(type
);
195 this->writemask
= writemask
;
198 dst_reg::dst_reg(struct brw_reg reg
)
203 this->fixed_hw_reg
= reg
;
204 this->type
= reg
.type
;
207 dst_reg::dst_reg(src_reg reg
)
211 this->file
= reg
.file
;
213 this->reg_offset
= reg
.reg_offset
;
214 this->type
= reg
.type
;
215 /* How should we do writemasking when converting from a src_reg? It seems
216 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
217 * what about for src.wx? Just special-case src.xxxx for now.
219 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
220 this->writemask
= WRITEMASK_X
;
222 this->writemask
= WRITEMASK_XYZW
;
223 this->reladdr
= reg
.reladdr
;
224 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
228 vec4_instruction::is_send_from_grf()
231 case SHADER_OPCODE_SHADER_TIME_ADD
:
232 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
240 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
242 if (brw
->gen
== 6 && is_math())
245 if (is_send_from_grf())
248 if (!backend_instruction::can_do_source_mods())
255 * Returns how many MRFs an opcode will write over.
257 * Note that this is not the 0 or 1 implied writes in an actual gen
258 * instruction -- the generate_* functions generate additional MOVs
262 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
267 switch (inst
->opcode
) {
268 case SHADER_OPCODE_RCP
:
269 case SHADER_OPCODE_RSQ
:
270 case SHADER_OPCODE_SQRT
:
271 case SHADER_OPCODE_EXP2
:
272 case SHADER_OPCODE_LOG2
:
273 case SHADER_OPCODE_SIN
:
274 case SHADER_OPCODE_COS
:
276 case SHADER_OPCODE_INT_QUOTIENT
:
277 case SHADER_OPCODE_INT_REMAINDER
:
278 case SHADER_OPCODE_POW
:
280 case VS_OPCODE_URB_WRITE
:
282 case VS_OPCODE_PULL_CONSTANT_LOAD
:
284 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
286 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
288 case GS_OPCODE_URB_WRITE
:
289 case GS_OPCODE_URB_WRITE_ALLOCATE
:
290 case GS_OPCODE_THREAD_END
:
292 case GS_OPCODE_FF_SYNC
:
294 case SHADER_OPCODE_SHADER_TIME_ADD
:
296 case SHADER_OPCODE_TEX
:
297 case SHADER_OPCODE_TXL
:
298 case SHADER_OPCODE_TXD
:
299 case SHADER_OPCODE_TXF
:
300 case SHADER_OPCODE_TXF_CMS
:
301 case SHADER_OPCODE_TXF_MCS
:
302 case SHADER_OPCODE_TXS
:
303 case SHADER_OPCODE_TG4
:
304 case SHADER_OPCODE_TG4_OFFSET
:
305 return inst
->header_present
? 1 : 0;
306 case SHADER_OPCODE_UNTYPED_ATOMIC
:
307 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
310 unreachable("not reached");
315 src_reg::equals(const src_reg
&r
) const
317 return (file
== r
.file
&&
319 reg_offset
== r
.reg_offset
&&
321 negate
== r
.negate
&&
323 swizzle
== r
.swizzle
&&
324 !reladdr
&& !r
.reladdr
&&
325 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
326 sizeof(fixed_hw_reg
)) == 0);
329 /* Replaces unused channels of a swizzle with channels that are used.
331 * For instance, this pass transforms
333 * mov vgrf4.yz, vgrf5.wxzy
337 * mov vgrf4.yz, vgrf5.xxzx
339 * This eliminates false uses of some channels, letting dead code elimination
340 * remove the instructions that wrote them.
343 vec4_visitor::opt_reduce_swizzle()
345 bool progress
= false;
347 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
348 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
)
353 /* Determine which channels of the sources are read. */
354 switch (inst
->opcode
) {
355 case VEC4_OPCODE_PACK_BYTES
:
362 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
363 * but all four of src1.
383 swizzle
[0] = inst
->dst
.writemask
& WRITEMASK_X
? 0 : -1;
384 swizzle
[1] = inst
->dst
.writemask
& WRITEMASK_Y
? 1 : -1;
385 swizzle
[2] = inst
->dst
.writemask
& WRITEMASK_Z
? 2 : -1;
386 swizzle
[3] = inst
->dst
.writemask
& WRITEMASK_W
? 3 : -1;
390 /* Resolve unread channels (-1) by assigning them the swizzle of the
391 * first channel that is used.
393 int first_used_channel
= 0;
394 for (int i
= 0; i
< 4; i
++) {
395 if (swizzle
[i
] != -1) {
396 first_used_channel
= swizzle
[i
];
400 for (int i
= 0; i
< 4; i
++) {
401 if (swizzle
[i
] == -1) {
402 swizzle
[i
] = first_used_channel
;
406 /* Update sources' swizzles. */
407 for (int i
= 0; i
< 3; i
++) {
408 if (inst
->src
[i
].file
!= GRF
&&
409 inst
->src
[i
].file
!= ATTR
&&
410 inst
->src
[i
].file
!= UNIFORM
)
414 for (int j
= 0; j
< 4; j
++) {
415 swiz
[j
] = BRW_GET_SWZ(inst
->src
[i
].swizzle
, swizzle
[j
]);
418 unsigned new_swizzle
= BRW_SWIZZLE4(swiz
[0], swiz
[1], swiz
[2], swiz
[3]);
419 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
420 inst
->src
[i
].swizzle
= new_swizzle
;
427 invalidate_live_intervals();
433 vec4_visitor::split_uniform_registers()
435 /* Prior to this, uniforms have been in an array sized according to
436 * the number of vector uniforms present, sparsely filled (so an
437 * aggregate results in reg indices being skipped over). Now we're
438 * going to cut those aggregates up so each .reg index is one
439 * vector. The goal is to make elimination of unused uniform
440 * components easier later.
442 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
443 for (int i
= 0 ; i
< 3; i
++) {
444 if (inst
->src
[i
].file
!= UNIFORM
)
447 assert(!inst
->src
[i
].reladdr
);
449 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
450 inst
->src
[i
].reg_offset
= 0;
454 /* Update that everything is now vector-sized. */
455 for (int i
= 0; i
< this->uniforms
; i
++) {
456 this->uniform_size
[i
] = 1;
461 vec4_visitor::pack_uniform_registers()
463 bool uniform_used
[this->uniforms
];
464 int new_loc
[this->uniforms
];
465 int new_chan
[this->uniforms
];
467 memset(uniform_used
, 0, sizeof(uniform_used
));
468 memset(new_loc
, 0, sizeof(new_loc
));
469 memset(new_chan
, 0, sizeof(new_chan
));
471 /* Find which uniform vectors are actually used by the program. We
472 * expect unused vector elements when we've moved array access out
473 * to pull constants, and from some GLSL code generators like wine.
475 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
476 for (int i
= 0 ; i
< 3; i
++) {
477 if (inst
->src
[i
].file
!= UNIFORM
)
480 uniform_used
[inst
->src
[i
].reg
] = true;
484 int new_uniform_count
= 0;
486 /* Now, figure out a packing of the live uniform vectors into our
489 for (int src
= 0; src
< uniforms
; src
++) {
490 assert(src
< uniform_array_size
);
491 int size
= this->uniform_vector_size
[src
];
493 if (!uniform_used
[src
]) {
494 this->uniform_vector_size
[src
] = 0;
499 /* Find the lowest place we can slot this uniform in. */
500 for (dst
= 0; dst
< src
; dst
++) {
501 if (this->uniform_vector_size
[dst
] + size
<= 4)
510 new_chan
[src
] = this->uniform_vector_size
[dst
];
512 /* Move the references to the data */
513 for (int j
= 0; j
< size
; j
++) {
514 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
515 stage_prog_data
->param
[src
* 4 + j
];
518 this->uniform_vector_size
[dst
] += size
;
519 this->uniform_vector_size
[src
] = 0;
522 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
525 this->uniforms
= new_uniform_count
;
527 /* Now, update the instructions for our repacked uniforms. */
528 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
529 for (int i
= 0 ; i
< 3; i
++) {
530 int src
= inst
->src
[i
].reg
;
532 if (inst
->src
[i
].file
!= UNIFORM
)
535 inst
->src
[i
].reg
= new_loc
[src
];
537 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
538 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
539 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
540 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
541 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
547 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
549 * While GLSL IR also performs this optimization, we end up with it in
550 * our instruction stream for a couple of reasons. One is that we
551 * sometimes generate silly instructions, for example in array access
552 * where we'll generate "ADD offset, index, base" even if base is 0.
553 * The other is that GLSL IR's constant propagation doesn't track the
554 * components of aggregates, so some VS patterns (initialize matrix to
555 * 0, accumulate in vertex blending factors) end up breaking down to
556 * instructions involving 0.
559 vec4_visitor::opt_algebraic()
561 bool progress
= false;
563 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
564 switch (inst
->opcode
) {
566 if (inst
->src
[1].is_zero()) {
567 inst
->opcode
= BRW_OPCODE_MOV
;
568 inst
->src
[1] = src_reg();
574 if (inst
->src
[1].is_zero()) {
575 inst
->opcode
= BRW_OPCODE_MOV
;
576 switch (inst
->src
[0].type
) {
577 case BRW_REGISTER_TYPE_F
:
578 inst
->src
[0] = src_reg(0.0f
);
580 case BRW_REGISTER_TYPE_D
:
581 inst
->src
[0] = src_reg(0);
583 case BRW_REGISTER_TYPE_UD
:
584 inst
->src
[0] = src_reg(0u);
587 unreachable("not reached");
589 inst
->src
[1] = src_reg();
591 } else if (inst
->src
[1].is_one()) {
592 inst
->opcode
= BRW_OPCODE_MOV
;
593 inst
->src
[1] = src_reg();
597 case SHADER_OPCODE_RCP
: {
598 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
599 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
600 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
601 inst
->opcode
= SHADER_OPCODE_RSQ
;
602 inst
->src
[0] = prev
->src
[0];
614 invalidate_live_intervals();
620 * Only a limited number of hardware registers may be used for push
621 * constants, so this turns access to the overflowed constants into
625 vec4_visitor::move_push_constants_to_pull_constants()
627 int pull_constant_loc
[this->uniforms
];
629 /* Only allow 32 registers (256 uniform components) as push constants,
630 * which is the limit on gen6.
632 * If changing this value, note the limitation about total_regs in
635 int max_uniform_components
= 32 * 8;
636 if (this->uniforms
* 4 <= max_uniform_components
)
639 /* Make some sort of choice as to which uniforms get sent to pull
640 * constants. We could potentially do something clever here like
641 * look for the most infrequently used uniform vec4s, but leave
644 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
645 pull_constant_loc
[i
/ 4] = -1;
647 if (i
>= max_uniform_components
) {
648 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
650 /* Try to find an existing copy of this uniform in the pull
651 * constants if it was part of an array access already.
653 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
656 for (matches
= 0; matches
< 4; matches
++) {
657 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
662 pull_constant_loc
[i
/ 4] = j
/ 4;
667 if (pull_constant_loc
[i
/ 4] == -1) {
668 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
669 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
671 for (int j
= 0; j
< 4; j
++) {
672 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
679 /* Now actually rewrite usage of the things we've moved to pull
682 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
683 for (int i
= 0 ; i
< 3; i
++) {
684 if (inst
->src
[i
].file
!= UNIFORM
||
685 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
688 int uniform
= inst
->src
[i
].reg
;
690 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
692 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
693 pull_constant_loc
[uniform
]);
695 inst
->src
[i
].file
= temp
.file
;
696 inst
->src
[i
].reg
= temp
.reg
;
697 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
698 inst
->src
[i
].reladdr
= NULL
;
702 /* Repack push constants to remove the now-unused ones. */
703 pack_uniform_registers();
706 /* Conditions for which we want to avoid setting the dependency control bits */
708 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
710 #define IS_DWORD(reg) \
711 (reg.type == BRW_REGISTER_TYPE_UD || \
712 reg.type == BRW_REGISTER_TYPE_D)
714 /* From the destination hazard section of the spec:
715 * > Instructions other than send, may use this control as long as operations
716 * > that have different pipeline latencies are not mixed.
719 if (inst
->opcode
== BRW_OPCODE_MUL
&&
720 IS_DWORD(inst
->src
[0]) &&
721 IS_DWORD(inst
->src
[1]))
728 * In the presence of send messages, totally interrupt dependency
729 * control. They're long enough that the chance of dependency
730 * control around them just doesn't matter.
733 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
734 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
735 * completes the scoreboard clear must have a non-zero execution mask. This
736 * means, if any kind of predication can change the execution mask or channel
737 * enable of the last instruction, the optimization must be avoided. This is
738 * to avoid instructions being shot down the pipeline when no writes are
742 * Dependency control does not work well over math instructions.
743 * NB: Discovered empirically
745 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
749 * Sets the dependency control fields on instructions after register
750 * allocation and before the generator is run.
752 * When you have a sequence of instructions like:
754 * DP4 temp.x vertex uniform[0]
755 * DP4 temp.y vertex uniform[0]
756 * DP4 temp.z vertex uniform[0]
757 * DP4 temp.w vertex uniform[0]
759 * The hardware doesn't know that it can actually run the later instructions
760 * while the previous ones are in flight, producing stalls. However, we have
761 * manual fields we can set in the instructions that let it do so.
764 vec4_visitor::opt_set_dependency_control()
766 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
767 uint8_t grf_channels_written
[BRW_MAX_GRF
];
768 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
769 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
771 assert(prog_data
->total_grf
||
772 !"Must be called after register allocation");
774 foreach_block (block
, cfg
) {
775 memset(last_grf_write
, 0, sizeof(last_grf_write
));
776 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
778 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
779 /* If we read from a register that we were doing dependency control
780 * on, don't do dependency control across the read.
782 for (int i
= 0; i
< 3; i
++) {
783 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
784 if (inst
->src
[i
].file
== GRF
) {
785 last_grf_write
[reg
] = NULL
;
786 } else if (inst
->src
[i
].file
== HW_REG
) {
787 memset(last_grf_write
, 0, sizeof(last_grf_write
));
790 assert(inst
->src
[i
].file
!= MRF
);
793 if (is_dep_ctrl_unsafe(inst
)) {
794 memset(last_grf_write
, 0, sizeof(last_grf_write
));
795 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
799 /* Now, see if we can do dependency control for this instruction
800 * against a previous one writing to its destination.
802 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
803 if (inst
->dst
.file
== GRF
) {
804 if (last_grf_write
[reg
] &&
805 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
806 last_grf_write
[reg
]->no_dd_clear
= true;
807 inst
->no_dd_check
= true;
809 grf_channels_written
[reg
] = 0;
812 last_grf_write
[reg
] = inst
;
813 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
814 } else if (inst
->dst
.file
== MRF
) {
815 if (last_mrf_write
[reg
] &&
816 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
817 last_mrf_write
[reg
]->no_dd_clear
= true;
818 inst
->no_dd_check
= true;
820 mrf_channels_written
[reg
] = 0;
823 last_mrf_write
[reg
] = inst
;
824 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
825 } else if (inst
->dst
.reg
== HW_REG
) {
826 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
827 memset(last_grf_write
, 0, sizeof(last_grf_write
));
828 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
829 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
836 vec4_instruction::can_reswizzle(int dst_writemask
,
840 /* If this instruction sets anything not referenced by swizzle, then we'd
841 * totally break it when we reswizzle.
843 if (dst
.writemask
& ~swizzle_mask
)
853 * For any channels in the swizzle's source that were populated by this
854 * instruction, rewrite the instruction to put the appropriate result directly
857 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
860 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
862 int new_writemask
= 0;
863 int new_swizzle
[4] = { 0 };
865 /* Dot product instructions write a single result into all channels. */
866 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
867 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
) {
868 for (int i
= 0; i
< 3; i
++) {
869 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
872 /* Destination write mask doesn't correspond to source swizzle for the
873 * pack_bytes instruction.
875 if (opcode
== VEC4_OPCODE_PACK_BYTES
)
878 for (int c
= 0; c
< 4; c
++) {
879 new_swizzle
[c
] = BRW_GET_SWZ(src
[i
].swizzle
, BRW_GET_SWZ(swizzle
, c
));
882 src
[i
].swizzle
= BRW_SWIZZLE4(new_swizzle
[0], new_swizzle
[1],
883 new_swizzle
[2], new_swizzle
[3]);
887 for (int c
= 0; c
< 4; c
++) {
888 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
889 /* Skip components of the swizzle not used by the dst. */
890 if (!(dst_writemask
& (1 << c
)))
892 /* If we were populating this component, then populate the
893 * corresponding channel of the new dst.
895 if (dst
.writemask
& bit
)
896 new_writemask
|= (1 << c
);
898 dst
.writemask
= new_writemask
;
902 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
903 * just written and then MOVed into another reg and making the original write
904 * of the GRF write directly to the final destination instead.
907 vec4_visitor::opt_register_coalesce()
909 bool progress
= false;
912 calculate_live_intervals();
914 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
918 if (inst
->opcode
!= BRW_OPCODE_MOV
||
919 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
921 inst
->src
[0].file
!= GRF
||
922 inst
->dst
.type
!= inst
->src
[0].type
||
923 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
926 bool to_mrf
= (inst
->dst
.file
== MRF
);
928 /* Can't coalesce this GRF if someone else was going to
931 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
932 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
933 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
934 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
937 /* We need to check interference with the final destination between this
938 * instruction and the earliest instruction involved in writing the GRF
939 * we're eliminating. To do that, keep track of which of our source
940 * channels we've seen initialized.
942 bool chans_needed
[4] = {false, false, false, false};
943 int chans_remaining
= 0;
944 int swizzle_mask
= 0;
945 for (int i
= 0; i
< 4; i
++) {
946 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
948 if (!(inst
->dst
.writemask
& (1 << i
)))
951 swizzle_mask
|= (1 << chan
);
953 if (!chans_needed
[chan
]) {
954 chans_needed
[chan
] = true;
959 /* Now walk up the instruction stream trying to see if we can rewrite
960 * everything writing to the temporary to write into the destination
963 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
964 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
966 _scan_inst
= scan_inst
;
968 if (scan_inst
->dst
.file
== GRF
&&
969 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
970 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
971 /* Found something writing to the reg we want to coalesce away. */
973 /* SEND instructions can't have MRF as a destination. */
978 /* gen6 math instructions must have the destination be
979 * GRF, so no compute-to-MRF for them.
981 if (scan_inst
->is_math()) {
987 /* If we can't handle the swizzle, bail. */
988 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
989 inst
->src
[0].swizzle
,
994 /* Mark which channels we found unconditional writes for. */
995 if (!scan_inst
->predicate
) {
996 for (int i
= 0; i
< 4; i
++) {
997 if (scan_inst
->dst
.writemask
& (1 << i
) &&
999 chans_needed
[i
] = false;
1005 if (chans_remaining
== 0)
1009 /* You can't read from an MRF, so if someone else reads our MRF's
1010 * source GRF that we wanted to rewrite, that stops us. If it's a
1011 * GRF we're trying to coalesce to, we don't actually handle
1012 * rewriting sources so bail in that case as well.
1014 bool interfered
= false;
1015 for (int i
= 0; i
< 3; i
++) {
1016 if (scan_inst
->src
[i
].file
== GRF
&&
1017 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1018 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1025 /* If somebody else writes our destination here, we can't coalesce
1028 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1029 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1033 /* Check for reads of the register we're trying to coalesce into. We
1034 * can't go rewriting instructions above that to put some other value
1035 * in the register instead.
1037 if (to_mrf
&& scan_inst
->mlen
> 0) {
1038 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1039 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1043 for (int i
= 0; i
< 3; i
++) {
1044 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1045 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1046 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1055 if (chans_remaining
== 0) {
1056 /* If we've made it here, we have an MOV we want to coalesce out, and
1057 * a scan_inst pointing to the earliest instruction involved in
1058 * computing the value. Now go rewrite the instruction stream
1061 vec4_instruction
*scan_inst
= _scan_inst
;
1062 while (scan_inst
!= inst
) {
1063 if (scan_inst
->dst
.file
== GRF
&&
1064 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1065 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1066 scan_inst
->reswizzle(inst
->dst
.writemask
,
1067 inst
->src
[0].swizzle
);
1068 scan_inst
->dst
.file
= inst
->dst
.file
;
1069 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1070 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1071 scan_inst
->saturate
|= inst
->saturate
;
1073 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1075 inst
->remove(block
);
1081 invalidate_live_intervals();
1087 * Splits virtual GRFs requesting more than one contiguous physical register.
1089 * We initially create large virtual GRFs for temporary structures, arrays,
1090 * and matrices, so that the dereference visitor functions can add reg_offsets
1091 * to work their way down to the actual member being accessed. But when it
1092 * comes to optimization, we'd like to treat each register as individual
1093 * storage if possible.
1095 * So far, the only thing that might prevent splitting is a send message from
1099 vec4_visitor::split_virtual_grfs()
1101 int num_vars
= this->virtual_grf_count
;
1102 int new_virtual_grf
[num_vars
];
1103 bool split_grf
[num_vars
];
1105 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1107 /* Try to split anything > 0 sized. */
1108 for (int i
= 0; i
< num_vars
; i
++) {
1109 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1112 /* Check that the instructions are compatible with the registers we're trying
1115 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1116 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1119 if (inst
->is_send_from_grf()) {
1120 for (int i
= 0; i
< 3; i
++) {
1121 if (inst
->src
[i
].file
== GRF
) {
1122 split_grf
[inst
->src
[i
].reg
] = false;
1128 /* Allocate new space for split regs. Note that the virtual
1129 * numbers will be contiguous.
1131 for (int i
= 0; i
< num_vars
; i
++) {
1135 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1136 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1137 int reg
= virtual_grf_alloc(1);
1138 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1141 this->virtual_grf_sizes
[i
] = 1;
1144 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1145 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1146 inst
->dst
.reg_offset
!= 0) {
1147 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1148 inst
->dst
.reg_offset
- 1);
1149 inst
->dst
.reg_offset
= 0;
1151 for (int i
= 0; i
< 3; i
++) {
1152 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1153 inst
->src
[i
].reg_offset
!= 0) {
1154 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1155 inst
->src
[i
].reg_offset
- 1);
1156 inst
->src
[i
].reg_offset
= 0;
1160 invalidate_live_intervals();
1164 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1166 dump_instruction(be_inst
, stderr
);
1170 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1172 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1174 if (inst
->predicate
) {
1175 fprintf(file
, "(%cf0) ",
1176 inst
->predicate_inverse
? '-' : '+');
1179 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1180 if (inst
->conditional_mod
) {
1181 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1185 switch (inst
->dst
.file
) {
1187 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1190 fprintf(file
, "m%d", inst
->dst
.reg
);
1193 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1194 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1196 fprintf(file
, "null");
1198 case BRW_ARF_ADDRESS
:
1199 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1201 case BRW_ARF_ACCUMULATOR
:
1202 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1205 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1206 inst
->dst
.fixed_hw_reg
.subnr
);
1209 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1210 inst
->dst
.fixed_hw_reg
.subnr
);
1214 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1216 if (inst
->dst
.fixed_hw_reg
.subnr
)
1217 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1220 fprintf(file
, "(null)");
1223 fprintf(file
, "???");
1226 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1228 if (inst
->dst
.writemask
& 1)
1230 if (inst
->dst
.writemask
& 2)
1232 if (inst
->dst
.writemask
& 4)
1234 if (inst
->dst
.writemask
& 8)
1237 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1239 if (inst
->src
[0].file
!= BAD_FILE
)
1240 fprintf(file
, ", ");
1242 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1243 if (inst
->src
[i
].negate
)
1245 if (inst
->src
[i
].abs
)
1247 switch (inst
->src
[i
].file
) {
1249 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1252 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1255 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1258 switch (inst
->src
[i
].type
) {
1259 case BRW_REGISTER_TYPE_F
:
1260 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1262 case BRW_REGISTER_TYPE_D
:
1263 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1265 case BRW_REGISTER_TYPE_UD
:
1266 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1268 case BRW_REGISTER_TYPE_VF
:
1269 fprintf(stderr
, "[%-gF, %-gF, %-gF, %-gF]",
1270 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1271 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1272 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1273 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1276 fprintf(file
, "???");
1281 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1283 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1285 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1286 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1288 fprintf(file
, "null");
1290 case BRW_ARF_ADDRESS
:
1291 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1293 case BRW_ARF_ACCUMULATOR
:
1294 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1297 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1298 inst
->src
[i
].fixed_hw_reg
.subnr
);
1301 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1302 inst
->src
[i
].fixed_hw_reg
.subnr
);
1306 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1308 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1309 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1310 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1314 fprintf(file
, "(null)");
1317 fprintf(file
, "???");
1321 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1322 if (inst
->src
[i
].reg_offset
!= 0 &&
1323 inst
->src
[i
].file
== GRF
&&
1324 virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1325 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1327 if (inst
->src
[i
].file
!= IMM
) {
1328 static const char *chans
[4] = {"x", "y", "z", "w"};
1330 for (int c
= 0; c
< 4; c
++) {
1331 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1335 if (inst
->src
[i
].abs
)
1338 if (inst
->src
[i
].file
!= IMM
) {
1339 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1342 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1343 fprintf(file
, ", ");
1346 fprintf(file
, "\n");
1350 static inline struct brw_reg
1351 attribute_to_hw_reg(int attr
, bool interleaved
)
1354 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1356 return brw_vec8_grf(attr
, 0);
1361 * Replace each register of type ATTR in this->instructions with a reference
1362 * to a fixed HW register.
1364 * If interleaved is true, then each attribute takes up half a register, with
1365 * register N containing attribute 2*N in its first half and attribute 2*N+1
1366 * in its second half (this corresponds to the payload setup used by geometry
1367 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1368 * false, then each attribute takes up a whole register, with register N
1369 * containing attribute N (this corresponds to the payload setup used by
1370 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1373 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1376 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1377 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1378 if (inst
->dst
.file
== ATTR
) {
1379 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1381 /* All attributes used in the shader need to have been assigned a
1382 * hardware register by the caller
1386 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1387 reg
.type
= inst
->dst
.type
;
1388 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1390 inst
->dst
.file
= HW_REG
;
1391 inst
->dst
.fixed_hw_reg
= reg
;
1394 for (int i
= 0; i
< 3; i
++) {
1395 if (inst
->src
[i
].file
!= ATTR
)
1398 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1400 /* All attributes used in the shader need to have been assigned a
1401 * hardware register by the caller
1405 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1406 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1407 reg
.type
= inst
->src
[i
].type
;
1408 if (inst
->src
[i
].abs
)
1410 if (inst
->src
[i
].negate
)
1413 inst
->src
[i
].file
= HW_REG
;
1414 inst
->src
[i
].fixed_hw_reg
= reg
;
1420 vec4_vs_visitor::setup_attributes(int payload_reg
)
1423 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1424 memset(attribute_map
, 0, sizeof(attribute_map
));
1427 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1428 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1429 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1434 /* VertexID is stored by the VF as the last vertex element, but we
1435 * don't represent it with a flag in inputs_read, so we call it
1438 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1439 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1443 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1445 /* The BSpec says we always have to read at least one thing from
1446 * the VF, and it appears that the hardware wedges otherwise.
1448 if (nr_attributes
== 0)
1451 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1453 unsigned vue_entries
=
1454 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1457 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1459 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1461 return payload_reg
+ nr_attributes
;
1465 vec4_visitor::setup_uniforms(int reg
)
1467 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1469 /* The pre-gen6 VS requires that some push constants get loaded no
1470 * matter what, or the GPU would hang.
1472 if (brw
->gen
< 6 && this->uniforms
== 0) {
1473 assert(this->uniforms
< this->uniform_array_size
);
1474 this->uniform_vector_size
[this->uniforms
] = 1;
1476 stage_prog_data
->param
=
1477 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1478 for (unsigned int i
= 0; i
< 4; i
++) {
1479 unsigned int slot
= this->uniforms
* 4 + i
;
1480 static gl_constant_value zero
= { 0.0 };
1481 stage_prog_data
->param
[slot
] = &zero
;
1487 reg
+= ALIGN(uniforms
, 2) / 2;
1490 stage_prog_data
->nr_params
= this->uniforms
* 4;
1492 prog_data
->base
.curb_read_length
=
1493 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1499 vec4_vs_visitor::setup_payload(void)
1503 /* The payload always contains important data in g0, which contains
1504 * the URB handles that are passed on to the URB write at the end
1505 * of the thread. So, we always start push constants at g1.
1509 reg
= setup_uniforms(reg
);
1511 reg
= setup_attributes(reg
);
1513 this->first_non_payload_grf
= reg
;
1517 vec4_visitor::assign_binding_table_offsets()
1519 assign_common_binding_table_offsets(0);
1523 vec4_visitor::get_timestamp()
1525 assert(brw
->gen
>= 7);
1527 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1530 BRW_REGISTER_TYPE_UD
,
1531 BRW_VERTICAL_STRIDE_0
,
1533 BRW_HORIZONTAL_STRIDE_4
,
1537 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1539 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1540 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1541 * even if it's not enabled in the dispatch.
1543 mov
->force_writemask_all
= true;
1545 return src_reg(dst
);
1549 vec4_visitor::emit_shader_time_begin()
1551 current_annotation
= "shader time start";
1552 shader_start_time
= get_timestamp();
1556 vec4_visitor::emit_shader_time_end()
1558 current_annotation
= "shader time end";
1559 src_reg shader_end_time
= get_timestamp();
1562 /* Check that there weren't any timestamp reset events (assuming these
1563 * were the only two timestamp reads that happened).
1565 src_reg reset_end
= shader_end_time
;
1566 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1567 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1568 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1570 emit(IF(BRW_PREDICATE_NORMAL
));
1572 /* Take the current timestamp and get the delta. */
1573 shader_start_time
.negate
= true;
1574 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1575 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1577 /* If there were no instructions between the two timestamp gets, the diff
1578 * is 2 cycles. Remove that overhead, so I can forget about that when
1579 * trying to determine the time taken for single instructions.
1581 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1583 emit_shader_time_write(st_base
, src_reg(diff
));
1584 emit_shader_time_write(st_written
, src_reg(1u));
1585 emit(BRW_OPCODE_ELSE
);
1586 emit_shader_time_write(st_reset
, src_reg(1u));
1587 emit(BRW_OPCODE_ENDIF
);
1591 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1594 int shader_time_index
=
1595 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1598 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1600 dst_reg offset
= dst
;
1604 offset
.type
= BRW_REGISTER_TYPE_UD
;
1605 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1607 time
.type
= BRW_REGISTER_TYPE_UD
;
1608 emit(MOV(time
, src_reg(value
)));
1610 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1616 sanity_param_count
= prog
->Parameters
->NumParameters
;
1618 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1619 emit_shader_time_begin();
1621 assign_binding_table_offsets();
1625 /* Generate VS IR for main(). (the visitor only descends into
1626 * functions called "main").
1629 visit_instructions(shader
->base
.ir
);
1631 emit_program_code();
1635 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1636 setup_uniform_clipplane_values();
1642 /* Before any optimization, push array accesses out to scratch
1643 * space where we need them to be. This pass may allocate new
1644 * virtual GRFs, so we want to do it early. It also makes sure
1645 * that we have reladdr computations available for CSE, since we'll
1646 * often do repeated subexpressions for those.
1649 move_grf_array_access_to_scratch();
1650 move_uniform_array_access_to_pull_constants();
1652 /* The ARB_vertex_program frontend emits pull constant loads directly
1653 * rather than using reladdr, so we don't need to walk through all the
1654 * instructions looking for things to move. There isn't anything.
1656 * We do still need to split things to vec4 size.
1658 split_uniform_registers();
1660 pack_uniform_registers();
1661 move_push_constants_to_pull_constants();
1662 split_virtual_grfs();
1664 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1666 #define OPT(pass, args...) do { \
1668 bool this_progress = pass(args); \
1670 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1671 char filename[64]; \
1672 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1673 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1675 backend_visitor::dump_instructions(filename); \
1678 progress = progress || this_progress; \
1682 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1684 snprintf(filename
, 64, "%s-%04d-00-start",
1685 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1687 backend_visitor::dump_instructions(filename
);
1697 OPT(opt_reduce_swizzle
);
1698 OPT(dead_code_eliminate
);
1699 OPT(dead_control_flow_eliminate
, this);
1700 OPT(opt_copy_propagation
);
1703 OPT(opt_register_coalesce
);
1713 /* Debug of register spilling: Go spill everything. */
1714 const int grf_count
= virtual_grf_count
;
1715 float spill_costs
[virtual_grf_count
];
1716 bool no_spill
[virtual_grf_count
];
1717 evaluate_spill_costs(spill_costs
, no_spill
);
1718 for (int i
= 0; i
< grf_count
; i
++) {
1725 while (!reg_allocate()) {
1730 opt_schedule_instructions();
1732 opt_set_dependency_control();
1734 /* If any state parameters were appended, then ParameterValues could have
1735 * been realloced, in which case the driver uniform storage set up by
1736 * _mesa_associate_uniform_storage() would point to freed memory. Make
1737 * sure that didn't happen.
1739 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1744 } /* namespace brw */
1749 * Compile a vertex shader.
1751 * Returns the final assembly and the program's size.
1754 brw_vs_emit(struct brw_context
*brw
,
1755 struct gl_shader_program
*prog
,
1756 struct brw_vs_compile
*c
,
1757 struct brw_vs_prog_data
*prog_data
,
1759 unsigned *final_assembly_size
)
1761 bool start_busy
= false;
1762 double start_time
= 0;
1764 if (unlikely(brw
->perf_debug
)) {
1765 start_busy
= (brw
->batch
.last_bo
&&
1766 drm_intel_bo_busy(brw
->batch
.last_bo
));
1767 start_time
= get_time();
1770 struct brw_shader
*shader
= NULL
;
1772 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1774 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1775 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1777 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1780 prog
->LinkStatus
= false;
1781 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1784 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1790 const unsigned *assembly
= NULL
;
1791 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1792 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1793 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1795 if (unlikely(brw
->perf_debug
) && shader
) {
1796 if (shader
->compiled_once
) {
1797 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1799 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1800 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1801 (get_time() - start_time
) * 1000);
1803 shader
->compiled_once
= true;
1811 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1812 struct brw_vec4_prog_key
*key
,
1813 GLuint id
, struct gl_program
*prog
)
1815 key
->program_string_id
= id
;
1816 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1818 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1819 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1820 if (prog
->ShadowSamplers
& (1 << i
)) {
1821 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1822 key
->tex
.swizzles
[i
] =
1823 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1825 /* Color sampler: assume no swizzling. */
1826 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;