2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
115 src_reg::src_reg(struct brw_reg reg
)
120 this->fixed_hw_reg
= reg
;
121 this->type
= reg
.type
;
124 src_reg::src_reg(dst_reg reg
)
128 this->file
= reg
.file
;
130 this->reg_offset
= reg
.reg_offset
;
131 this->type
= reg
.type
;
132 this->reladdr
= reg
.reladdr
;
133 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 for (int i
= 0; i
< 4; i
++) {
140 if (!(reg
.writemask
& (1 << i
)))
143 swizzles
[next_chan
++] = last
= i
;
146 for (; next_chan
< 4; next_chan
++) {
147 swizzles
[next_chan
] = last
;
150 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
151 swizzles
[2], swizzles
[3]);
155 src_reg::is_accumulator() const
157 return file
== HW_REG
&&
158 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
159 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
166 memset(this, 0, sizeof(*this));
167 this->file
= BAD_FILE
;
168 this->writemask
= WRITEMASK_XYZW
;
176 dst_reg::dst_reg(register_file file
, int reg
)
184 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
191 this->type
= brw_type_for_base_type(type
);
192 this->writemask
= writemask
;
195 dst_reg::dst_reg(struct brw_reg reg
)
200 this->fixed_hw_reg
= reg
;
201 this->type
= reg
.type
;
204 dst_reg::dst_reg(src_reg reg
)
208 this->file
= reg
.file
;
210 this->reg_offset
= reg
.reg_offset
;
211 this->type
= reg
.type
;
212 /* How should we do writemasking when converting from a src_reg? It seems
213 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
214 * what about for src.wx? Just special-case src.xxxx for now.
216 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
217 this->writemask
= WRITEMASK_X
;
219 this->writemask
= WRITEMASK_XYZW
;
220 this->reladdr
= reg
.reladdr
;
221 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
225 dst_reg::is_null() const
227 return file
== HW_REG
&&
228 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
229 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
233 dst_reg::is_accumulator() const
235 return file
== HW_REG
&&
236 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
237 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
241 vec4_instruction::is_send_from_grf()
244 case SHADER_OPCODE_SHADER_TIME_ADD
:
245 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
253 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
255 if (brw
->gen
== 6 && is_math())
258 if (is_send_from_grf())
261 if (!backend_instruction::can_do_source_mods())
268 * Returns how many MRFs an opcode will write over.
270 * Note that this is not the 0 or 1 implied writes in an actual gen
271 * instruction -- the generate_* functions generate additional MOVs
275 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
280 switch (inst
->opcode
) {
281 case SHADER_OPCODE_RCP
:
282 case SHADER_OPCODE_RSQ
:
283 case SHADER_OPCODE_SQRT
:
284 case SHADER_OPCODE_EXP2
:
285 case SHADER_OPCODE_LOG2
:
286 case SHADER_OPCODE_SIN
:
287 case SHADER_OPCODE_COS
:
289 case SHADER_OPCODE_INT_QUOTIENT
:
290 case SHADER_OPCODE_INT_REMAINDER
:
291 case SHADER_OPCODE_POW
:
293 case VS_OPCODE_URB_WRITE
:
295 case VS_OPCODE_PULL_CONSTANT_LOAD
:
297 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
299 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
301 case GS_OPCODE_URB_WRITE
:
302 case GS_OPCODE_THREAD_END
:
304 case SHADER_OPCODE_SHADER_TIME_ADD
:
306 case SHADER_OPCODE_TEX
:
307 case SHADER_OPCODE_TXL
:
308 case SHADER_OPCODE_TXD
:
309 case SHADER_OPCODE_TXF
:
310 case SHADER_OPCODE_TXF_CMS
:
311 case SHADER_OPCODE_TXF_MCS
:
312 case SHADER_OPCODE_TXS
:
313 case SHADER_OPCODE_TG4
:
314 case SHADER_OPCODE_TG4_OFFSET
:
315 return inst
->header_present
? 1 : 0;
316 case SHADER_OPCODE_UNTYPED_ATOMIC
:
317 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
320 unreachable("not reached");
325 src_reg::equals(const src_reg
&r
) const
327 return (file
== r
.file
&&
329 reg_offset
== r
.reg_offset
&&
331 negate
== r
.negate
&&
333 swizzle
== r
.swizzle
&&
334 !reladdr
&& !r
.reladdr
&&
335 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
336 sizeof(fixed_hw_reg
)) == 0 &&
341 try_eliminate_instruction(vec4_instruction
*inst
, int new_writemask
,
342 const struct brw_context
*brw
)
344 if (inst
->has_side_effects())
347 if (new_writemask
== 0) {
348 /* Don't dead code eliminate instructions that write to the
349 * accumulator as a side-effect. Instead just set the destination
350 * to the null register to free it.
352 if (inst
->writes_accumulator
|| inst
->writes_flag()) {
353 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
359 } else if (inst
->dst
.writemask
!= new_writemask
) {
360 switch (inst
->opcode
) {
361 case SHADER_OPCODE_TXF_CMS
:
362 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
363 case VS_OPCODE_PULL_CONSTANT_LOAD
:
364 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
367 /* Do not set a writemask on Gen6 for math instructions, those are
368 * executed using align1 mode that does not support a destination mask.
370 if (!(brw
->gen
== 6 && inst
->is_math()) && !inst
->is_tex()) {
371 inst
->dst
.writemask
= new_writemask
;
381 * Must be called after calculate_live_intervals() to remove unused
382 * writes to registers -- register allocation will fail otherwise
383 * because something deffed but not used won't be considered to
384 * interfere with other regs.
387 vec4_visitor::dead_code_eliminate()
389 bool progress
= false;
392 calculate_live_intervals();
394 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
397 bool inst_writes_flag
= false;
398 if (inst
->dst
.file
!= GRF
) {
399 if (inst
->dst
.is_null() && inst
->writes_flag()) {
400 inst_writes_flag
= true;
406 if (inst
->dst
.file
== GRF
) {
407 int write_mask
= inst
->dst
.writemask
;
409 for (int c
= 0; c
< 4; c
++) {
410 if (write_mask
& (1 << c
)) {
411 assert(this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] >= pc
);
412 if (this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] == pc
) {
413 write_mask
&= ~(1 << c
);
418 progress
= try_eliminate_instruction(inst
, write_mask
, brw
) ||
422 if (inst
->predicate
|| inst
->prev
== NULL
)
426 if (inst_writes_flag
) {
427 /* Arbitrarily chosen, other than not being an xyzw writemask. */
428 #define FLAG_WRITEMASK (1 << 5)
429 dead_channels
= inst
->reads_flag() ? 0 : FLAG_WRITEMASK
;
431 dead_channels
= inst
->dst
.writemask
;
433 for (int i
= 0; i
< 3; i
++) {
434 if (inst
->src
[i
].file
!= GRF
||
435 inst
->src
[i
].reg
!= inst
->dst
.reg
)
438 for (int j
= 0; j
< 4; j
++) {
439 int swiz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
440 dead_channels
&= ~(1 << swiz
);
445 for (exec_node
*node
= inst
->prev
, *prev
= node
->prev
;
446 prev
!= NULL
&& dead_channels
!= 0;
447 node
= prev
, prev
= prev
->prev
) {
448 vec4_instruction
*scan_inst
= (vec4_instruction
*)node
;
450 if (scan_inst
->is_control_flow())
453 if (inst_writes_flag
) {
454 if (scan_inst
->dst
.is_null() && scan_inst
->writes_flag()) {
458 } else if (scan_inst
->reads_flag()) {
463 if (inst
->dst
.file
== scan_inst
->dst
.file
&&
464 inst
->dst
.reg
== scan_inst
->dst
.reg
&&
465 inst
->dst
.reg_offset
== scan_inst
->dst
.reg_offset
) {
466 int new_writemask
= scan_inst
->dst
.writemask
& ~dead_channels
;
468 progress
= try_eliminate_instruction(scan_inst
, new_writemask
, brw
) ||
472 for (int i
= 0; i
< 3; i
++) {
473 if (scan_inst
->src
[i
].file
!= inst
->dst
.file
||
474 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
)
477 for (int j
= 0; j
< 4; j
++) {
478 int swiz
= BRW_GET_SWZ(scan_inst
->src
[i
].swizzle
, j
);
479 dead_channels
&= ~(1 << swiz
);
486 invalidate_live_intervals();
492 vec4_visitor::split_uniform_registers()
494 /* Prior to this, uniforms have been in an array sized according to
495 * the number of vector uniforms present, sparsely filled (so an
496 * aggregate results in reg indices being skipped over). Now we're
497 * going to cut those aggregates up so each .reg index is one
498 * vector. The goal is to make elimination of unused uniform
499 * components easier later.
501 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
502 for (int i
= 0 ; i
< 3; i
++) {
503 if (inst
->src
[i
].file
!= UNIFORM
)
506 assert(!inst
->src
[i
].reladdr
);
508 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
509 inst
->src
[i
].reg_offset
= 0;
513 /* Update that everything is now vector-sized. */
514 for (int i
= 0; i
< this->uniforms
; i
++) {
515 this->uniform_size
[i
] = 1;
520 vec4_visitor::pack_uniform_registers()
522 bool uniform_used
[this->uniforms
];
523 int new_loc
[this->uniforms
];
524 int new_chan
[this->uniforms
];
526 memset(uniform_used
, 0, sizeof(uniform_used
));
527 memset(new_loc
, 0, sizeof(new_loc
));
528 memset(new_chan
, 0, sizeof(new_chan
));
530 /* Find which uniform vectors are actually used by the program. We
531 * expect unused vector elements when we've moved array access out
532 * to pull constants, and from some GLSL code generators like wine.
534 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
535 for (int i
= 0 ; i
< 3; i
++) {
536 if (inst
->src
[i
].file
!= UNIFORM
)
539 uniform_used
[inst
->src
[i
].reg
] = true;
543 int new_uniform_count
= 0;
545 /* Now, figure out a packing of the live uniform vectors into our
548 for (int src
= 0; src
< uniforms
; src
++) {
549 assert(src
< uniform_array_size
);
550 int size
= this->uniform_vector_size
[src
];
552 if (!uniform_used
[src
]) {
553 this->uniform_vector_size
[src
] = 0;
558 /* Find the lowest place we can slot this uniform in. */
559 for (dst
= 0; dst
< src
; dst
++) {
560 if (this->uniform_vector_size
[dst
] + size
<= 4)
569 new_chan
[src
] = this->uniform_vector_size
[dst
];
571 /* Move the references to the data */
572 for (int j
= 0; j
< size
; j
++) {
573 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
574 stage_prog_data
->param
[src
* 4 + j
];
577 this->uniform_vector_size
[dst
] += size
;
578 this->uniform_vector_size
[src
] = 0;
581 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
584 this->uniforms
= new_uniform_count
;
586 /* Now, update the instructions for our repacked uniforms. */
587 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
588 for (int i
= 0 ; i
< 3; i
++) {
589 int src
= inst
->src
[i
].reg
;
591 if (inst
->src
[i
].file
!= UNIFORM
)
594 inst
->src
[i
].reg
= new_loc
[src
];
596 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
597 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
598 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
599 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
600 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
606 src_reg::is_zero() const
611 if (type
== BRW_REGISTER_TYPE_F
) {
619 src_reg::is_one() const
624 if (type
== BRW_REGISTER_TYPE_F
) {
632 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
634 * While GLSL IR also performs this optimization, we end up with it in
635 * our instruction stream for a couple of reasons. One is that we
636 * sometimes generate silly instructions, for example in array access
637 * where we'll generate "ADD offset, index, base" even if base is 0.
638 * The other is that GLSL IR's constant propagation doesn't track the
639 * components of aggregates, so some VS patterns (initialize matrix to
640 * 0, accumulate in vertex blending factors) end up breaking down to
641 * instructions involving 0.
644 vec4_visitor::opt_algebraic()
646 bool progress
= false;
648 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
649 switch (inst
->opcode
) {
651 if (inst
->src
[1].is_zero()) {
652 inst
->opcode
= BRW_OPCODE_MOV
;
653 inst
->src
[1] = src_reg();
659 if (inst
->src
[1].is_zero()) {
660 inst
->opcode
= BRW_OPCODE_MOV
;
661 switch (inst
->src
[0].type
) {
662 case BRW_REGISTER_TYPE_F
:
663 inst
->src
[0] = src_reg(0.0f
);
665 case BRW_REGISTER_TYPE_D
:
666 inst
->src
[0] = src_reg(0);
668 case BRW_REGISTER_TYPE_UD
:
669 inst
->src
[0] = src_reg(0u);
672 unreachable("not reached");
674 inst
->src
[1] = src_reg();
676 } else if (inst
->src
[1].is_one()) {
677 inst
->opcode
= BRW_OPCODE_MOV
;
678 inst
->src
[1] = src_reg();
688 invalidate_live_intervals();
694 * Only a limited number of hardware registers may be used for push
695 * constants, so this turns access to the overflowed constants into
699 vec4_visitor::move_push_constants_to_pull_constants()
701 int pull_constant_loc
[this->uniforms
];
703 /* Only allow 32 registers (256 uniform components) as push constants,
704 * which is the limit on gen6.
706 int max_uniform_components
= 32 * 8;
707 if (this->uniforms
* 4 <= max_uniform_components
)
710 /* Make some sort of choice as to which uniforms get sent to pull
711 * constants. We could potentially do something clever here like
712 * look for the most infrequently used uniform vec4s, but leave
715 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
716 pull_constant_loc
[i
/ 4] = -1;
718 if (i
>= max_uniform_components
) {
719 const float **values
= &stage_prog_data
->param
[i
];
721 /* Try to find an existing copy of this uniform in the pull
722 * constants if it was part of an array access already.
724 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
727 for (matches
= 0; matches
< 4; matches
++) {
728 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
733 pull_constant_loc
[i
/ 4] = j
/ 4;
738 if (pull_constant_loc
[i
/ 4] == -1) {
739 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
740 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
742 for (int j
= 0; j
< 4; j
++) {
743 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
750 /* Now actually rewrite usage of the things we've moved to pull
753 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
754 for (int i
= 0 ; i
< 3; i
++) {
755 if (inst
->src
[i
].file
!= UNIFORM
||
756 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
759 int uniform
= inst
->src
[i
].reg
;
761 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
763 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
764 pull_constant_loc
[uniform
]);
766 inst
->src
[i
].file
= temp
.file
;
767 inst
->src
[i
].reg
= temp
.reg
;
768 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
769 inst
->src
[i
].reladdr
= NULL
;
773 /* Repack push constants to remove the now-unused ones. */
774 pack_uniform_registers();
778 * Sets the dependency control fields on instructions after register
779 * allocation and before the generator is run.
781 * When you have a sequence of instructions like:
783 * DP4 temp.x vertex uniform[0]
784 * DP4 temp.y vertex uniform[0]
785 * DP4 temp.z vertex uniform[0]
786 * DP4 temp.w vertex uniform[0]
788 * The hardware doesn't know that it can actually run the later instructions
789 * while the previous ones are in flight, producing stalls. However, we have
790 * manual fields we can set in the instructions that let it do so.
793 vec4_visitor::opt_set_dependency_control()
795 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
796 uint8_t grf_channels_written
[BRW_MAX_GRF
];
797 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
798 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
800 cfg_t
cfg(&instructions
);
802 assert(prog_data
->total_grf
||
803 !"Must be called after register allocation");
805 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
806 bblock_t
*bblock
= cfg
.blocks
[i
];
807 vec4_instruction
*inst
;
809 memset(last_grf_write
, 0, sizeof(last_grf_write
));
810 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
812 for (inst
= (vec4_instruction
*)bblock
->start
;
813 inst
!= (vec4_instruction
*)bblock
->end
->next
;
814 inst
= (vec4_instruction
*)inst
->next
) {
815 /* If we read from a register that we were doing dependency control
816 * on, don't do dependency control across the read.
818 for (int i
= 0; i
< 3; i
++) {
819 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
820 if (inst
->src
[i
].file
== GRF
) {
821 last_grf_write
[reg
] = NULL
;
822 } else if (inst
->src
[i
].file
== HW_REG
) {
823 memset(last_grf_write
, 0, sizeof(last_grf_write
));
826 assert(inst
->src
[i
].file
!= MRF
);
829 /* In the presence of send messages, totally interrupt dependency
830 * control. They're long enough that the chance of dependency
831 * control around them just doesn't matter.
834 memset(last_grf_write
, 0, sizeof(last_grf_write
));
835 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
839 /* It looks like setting dependency control on a predicated
840 * instruction hangs the GPU.
842 if (inst
->predicate
) {
843 memset(last_grf_write
, 0, sizeof(last_grf_write
));
844 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
848 /* Dependency control does not work well over math instructions.
850 if (inst
->is_math()) {
851 memset(last_grf_write
, 0, sizeof(last_grf_write
));
852 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
856 /* Now, see if we can do dependency control for this instruction
857 * against a previous one writing to its destination.
859 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
860 if (inst
->dst
.file
== GRF
) {
861 if (last_grf_write
[reg
] &&
862 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
863 last_grf_write
[reg
]->no_dd_clear
= true;
864 inst
->no_dd_check
= true;
866 grf_channels_written
[reg
] = 0;
869 last_grf_write
[reg
] = inst
;
870 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
871 } else if (inst
->dst
.file
== MRF
) {
872 if (last_mrf_write
[reg
] &&
873 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
874 last_mrf_write
[reg
]->no_dd_clear
= true;
875 inst
->no_dd_check
= true;
877 mrf_channels_written
[reg
] = 0;
880 last_mrf_write
[reg
] = inst
;
881 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
882 } else if (inst
->dst
.reg
== HW_REG
) {
883 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
884 memset(last_grf_write
, 0, sizeof(last_grf_write
));
885 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
886 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
893 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
897 /* If this instruction sets anything not referenced by swizzle, then we'd
898 * totally break it when we reswizzle.
900 if (dst
.writemask
& ~swizzle_mask
)
909 /* Check if there happens to be no reswizzling required. */
910 for (int c
= 0; c
< 4; c
++) {
911 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
912 /* Skip components of the swizzle not used by the dst. */
913 if (!(dst_writemask
& (1 << c
)))
916 /* We don't do the reswizzling yet, so just sanity check that we
927 * For any channels in the swizzle's source that were populated by this
928 * instruction, rewrite the instruction to put the appropriate result directly
931 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
934 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
936 int new_writemask
= 0;
942 for (int c
= 0; c
< 4; c
++) {
943 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
944 /* Skip components of the swizzle not used by the dst. */
945 if (!(dst_writemask
& (1 << c
)))
947 /* If we were populating this component, then populate the
948 * corresponding channel of the new dst.
950 if (dst
.writemask
& bit
)
951 new_writemask
|= (1 << c
);
953 dst
.writemask
= new_writemask
;
956 for (int c
= 0; c
< 4; c
++) {
957 /* Skip components of the swizzle not used by the dst. */
958 if (!(dst_writemask
& (1 << c
)))
961 /* We don't do the reswizzling yet, so just sanity check that we
964 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
971 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
972 * just written and then MOVed into another reg and making the original write
973 * of the GRF write directly to the final destination instead.
976 vec4_visitor::opt_register_coalesce()
978 bool progress
= false;
981 calculate_live_intervals();
983 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
987 if (inst
->opcode
!= BRW_OPCODE_MOV
||
988 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
990 inst
->src
[0].file
!= GRF
||
991 inst
->dst
.type
!= inst
->src
[0].type
||
992 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
995 bool to_mrf
= (inst
->dst
.file
== MRF
);
997 /* Can't coalesce this GRF if someone else was going to
1000 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1001 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1002 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1003 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1006 /* We need to check interference with the final destination between this
1007 * instruction and the earliest instruction involved in writing the GRF
1008 * we're eliminating. To do that, keep track of which of our source
1009 * channels we've seen initialized.
1011 bool chans_needed
[4] = {false, false, false, false};
1012 int chans_remaining
= 0;
1013 int swizzle_mask
= 0;
1014 for (int i
= 0; i
< 4; i
++) {
1015 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1017 if (!(inst
->dst
.writemask
& (1 << i
)))
1020 swizzle_mask
|= (1 << chan
);
1022 if (!chans_needed
[chan
]) {
1023 chans_needed
[chan
] = true;
1028 /* Now walk up the instruction stream trying to see if we can rewrite
1029 * everything writing to the temporary to write into the destination
1032 vec4_instruction
*scan_inst
;
1033 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
1034 scan_inst
->prev
!= NULL
;
1035 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
1036 if (scan_inst
->dst
.file
== GRF
&&
1037 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1038 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1039 /* Found something writing to the reg we want to coalesce away. */
1041 /* SEND instructions can't have MRF as a destination. */
1042 if (scan_inst
->mlen
)
1045 if (brw
->gen
== 6) {
1046 /* gen6 math instructions must have the destination be
1047 * GRF, so no compute-to-MRF for them.
1049 if (scan_inst
->is_math()) {
1055 /* If we can't handle the swizzle, bail. */
1056 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
1057 inst
->src
[0].swizzle
,
1062 /* Mark which channels we found unconditional writes for. */
1063 if (!scan_inst
->predicate
) {
1064 for (int i
= 0; i
< 4; i
++) {
1065 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1067 chans_needed
[i
] = false;
1073 if (chans_remaining
== 0)
1077 /* We don't handle flow control here. Most computation of values
1078 * that could be coalesced happens just before their use.
1080 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1081 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1082 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1083 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1087 /* You can't read from an MRF, so if someone else reads our MRF's
1088 * source GRF that we wanted to rewrite, that stops us. If it's a
1089 * GRF we're trying to coalesce to, we don't actually handle
1090 * rewriting sources so bail in that case as well.
1092 bool interfered
= false;
1093 for (int i
= 0; i
< 3; i
++) {
1094 if (scan_inst
->src
[i
].file
== GRF
&&
1095 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1096 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1103 /* If somebody else writes our destination here, we can't coalesce
1106 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1107 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1111 /* Check for reads of the register we're trying to coalesce into. We
1112 * can't go rewriting instructions above that to put some other value
1113 * in the register instead.
1115 if (to_mrf
&& scan_inst
->mlen
> 0) {
1116 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1117 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1121 for (int i
= 0; i
< 3; i
++) {
1122 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1123 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1124 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1133 if (chans_remaining
== 0) {
1134 /* If we've made it here, we have an MOV we want to coalesce out, and
1135 * a scan_inst pointing to the earliest instruction involved in
1136 * computing the value. Now go rewrite the instruction stream
1140 while (scan_inst
!= inst
) {
1141 if (scan_inst
->dst
.file
== GRF
&&
1142 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1143 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1144 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1145 inst
->src
[0].swizzle
);
1146 scan_inst
->dst
.file
= inst
->dst
.file
;
1147 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1148 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1149 scan_inst
->saturate
|= inst
->saturate
;
1151 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1159 invalidate_live_intervals();
1165 * Splits virtual GRFs requesting more than one contiguous physical register.
1167 * We initially create large virtual GRFs for temporary structures, arrays,
1168 * and matrices, so that the dereference visitor functions can add reg_offsets
1169 * to work their way down to the actual member being accessed. But when it
1170 * comes to optimization, we'd like to treat each register as individual
1171 * storage if possible.
1173 * So far, the only thing that might prevent splitting is a send message from
1177 vec4_visitor::split_virtual_grfs()
1179 int num_vars
= this->virtual_grf_count
;
1180 int new_virtual_grf
[num_vars
];
1181 bool split_grf
[num_vars
];
1183 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1185 /* Try to split anything > 0 sized. */
1186 for (int i
= 0; i
< num_vars
; i
++) {
1187 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1190 /* Check that the instructions are compatible with the registers we're trying
1193 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1194 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1197 if (inst
->is_send_from_grf()) {
1198 for (int i
= 0; i
< 3; i
++) {
1199 if (inst
->src
[i
].file
== GRF
) {
1200 split_grf
[inst
->src
[i
].reg
] = false;
1206 /* Allocate new space for split regs. Note that the virtual
1207 * numbers will be contiguous.
1209 for (int i
= 0; i
< num_vars
; i
++) {
1213 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1214 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1215 int reg
= virtual_grf_alloc(1);
1216 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1219 this->virtual_grf_sizes
[i
] = 1;
1222 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1223 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1224 inst
->dst
.reg_offset
!= 0) {
1225 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1226 inst
->dst
.reg_offset
- 1);
1227 inst
->dst
.reg_offset
= 0;
1229 for (int i
= 0; i
< 3; i
++) {
1230 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1231 inst
->src
[i
].reg_offset
!= 0) {
1232 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1233 inst
->src
[i
].reg_offset
- 1);
1234 inst
->src
[i
].reg_offset
= 0;
1238 invalidate_live_intervals();
1242 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1244 dump_instruction(be_inst
, stderr
);
1248 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1250 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1252 if (inst
->predicate
) {
1253 fprintf(file
, "(%cf0) ",
1254 inst
->predicate_inverse
? '-' : '+');
1257 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1258 if (inst
->conditional_mod
) {
1259 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1263 switch (inst
->dst
.file
) {
1265 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1268 fprintf(file
, "m%d", inst
->dst
.reg
);
1271 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1272 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1274 fprintf(file
, "null");
1276 case BRW_ARF_ADDRESS
:
1277 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1279 case BRW_ARF_ACCUMULATOR
:
1280 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1283 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1284 inst
->dst
.fixed_hw_reg
.subnr
);
1287 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1288 inst
->dst
.fixed_hw_reg
.subnr
);
1292 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1294 if (inst
->dst
.fixed_hw_reg
.subnr
)
1295 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1298 fprintf(file
, "(null)");
1301 fprintf(file
, "???");
1304 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1306 if (inst
->dst
.writemask
& 1)
1308 if (inst
->dst
.writemask
& 2)
1310 if (inst
->dst
.writemask
& 4)
1312 if (inst
->dst
.writemask
& 8)
1315 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
1317 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1318 if (inst
->src
[i
].negate
)
1320 if (inst
->src
[i
].abs
)
1322 switch (inst
->src
[i
].file
) {
1324 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1327 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1330 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1333 switch (inst
->src
[i
].type
) {
1334 case BRW_REGISTER_TYPE_F
:
1335 fprintf(file
, "%fF", inst
->src
[i
].imm
.f
);
1337 case BRW_REGISTER_TYPE_D
:
1338 fprintf(file
, "%dD", inst
->src
[i
].imm
.i
);
1340 case BRW_REGISTER_TYPE_UD
:
1341 fprintf(file
, "%uU", inst
->src
[i
].imm
.u
);
1344 fprintf(file
, "???");
1349 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1351 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1353 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1354 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1356 fprintf(file
, "null");
1358 case BRW_ARF_ADDRESS
:
1359 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1361 case BRW_ARF_ACCUMULATOR
:
1362 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1365 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1366 inst
->src
[i
].fixed_hw_reg
.subnr
);
1369 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1370 inst
->src
[i
].fixed_hw_reg
.subnr
);
1374 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1376 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1377 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1378 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1382 fprintf(file
, "(null)");
1385 fprintf(file
, "???");
1389 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1390 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1392 if (inst
->src
[i
].file
!= IMM
) {
1393 static const char *chans
[4] = {"x", "y", "z", "w"};
1395 for (int c
= 0; c
< 4; c
++) {
1396 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1400 if (inst
->src
[i
].abs
)
1403 if (inst
->src
[i
].file
!= IMM
) {
1404 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1407 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1408 fprintf(file
, ", ");
1411 fprintf(file
, "\n");
1415 static inline struct brw_reg
1416 attribute_to_hw_reg(int attr
, bool interleaved
)
1419 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1421 return brw_vec8_grf(attr
, 0);
1426 * Replace each register of type ATTR in this->instructions with a reference
1427 * to a fixed HW register.
1429 * If interleaved is true, then each attribute takes up half a register, with
1430 * register N containing attribute 2*N in its first half and attribute 2*N+1
1431 * in its second half (this corresponds to the payload setup used by geometry
1432 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1433 * false, then each attribute takes up a whole register, with register N
1434 * containing attribute N (this corresponds to the payload setup used by
1435 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1438 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1441 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1442 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1443 if (inst
->dst
.file
== ATTR
) {
1444 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1446 /* All attributes used in the shader need to have been assigned a
1447 * hardware register by the caller
1451 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1452 reg
.type
= inst
->dst
.type
;
1453 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1455 inst
->dst
.file
= HW_REG
;
1456 inst
->dst
.fixed_hw_reg
= reg
;
1459 for (int i
= 0; i
< 3; i
++) {
1460 if (inst
->src
[i
].file
!= ATTR
)
1463 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1465 /* All attributes used in the shader need to have been assigned a
1466 * hardware register by the caller
1470 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1471 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1472 reg
.type
= inst
->src
[i
].type
;
1473 if (inst
->src
[i
].abs
)
1475 if (inst
->src
[i
].negate
)
1478 inst
->src
[i
].file
= HW_REG
;
1479 inst
->src
[i
].fixed_hw_reg
= reg
;
1485 vec4_vs_visitor::setup_attributes(int payload_reg
)
1488 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1489 memset(attribute_map
, 0, sizeof(attribute_map
));
1492 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1493 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1494 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1499 /* VertexID is stored by the VF as the last vertex element, but we
1500 * don't represent it with a flag in inputs_read, so we call it
1503 if (vs_prog_data
->uses_vertexid
) {
1504 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1508 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1510 /* The BSpec says we always have to read at least one thing from
1511 * the VF, and it appears that the hardware wedges otherwise.
1513 if (nr_attributes
== 0)
1516 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1518 unsigned vue_entries
=
1519 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1522 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1524 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1526 return payload_reg
+ nr_attributes
;
1530 vec4_visitor::setup_uniforms(int reg
)
1532 prog_data
->dispatch_grf_start_reg
= reg
;
1534 /* The pre-gen6 VS requires that some push constants get loaded no
1535 * matter what, or the GPU would hang.
1537 if (brw
->gen
< 6 && this->uniforms
== 0) {
1538 assert(this->uniforms
< this->uniform_array_size
);
1539 this->uniform_vector_size
[this->uniforms
] = 1;
1541 stage_prog_data
->param
=
1542 reralloc(NULL
, stage_prog_data
->param
, const float *, 4);
1543 for (unsigned int i
= 0; i
< 4; i
++) {
1544 unsigned int slot
= this->uniforms
* 4 + i
;
1545 static float zero
= 0.0;
1546 stage_prog_data
->param
[slot
] = &zero
;
1552 reg
+= ALIGN(uniforms
, 2) / 2;
1555 stage_prog_data
->nr_params
= this->uniforms
* 4;
1557 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1563 vec4_vs_visitor::setup_payload(void)
1567 /* The payload always contains important data in g0, which contains
1568 * the URB handles that are passed on to the URB write at the end
1569 * of the thread. So, we always start push constants at g1.
1573 reg
= setup_uniforms(reg
);
1575 reg
= setup_attributes(reg
);
1577 this->first_non_payload_grf
= reg
;
1581 vec4_visitor::get_timestamp()
1583 assert(brw
->gen
>= 7);
1585 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1588 BRW_REGISTER_TYPE_UD
,
1589 BRW_VERTICAL_STRIDE_0
,
1591 BRW_HORIZONTAL_STRIDE_4
,
1595 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1597 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1598 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1599 * even if it's not enabled in the dispatch.
1601 mov
->force_writemask_all
= true;
1603 return src_reg(dst
);
1607 vec4_visitor::emit_shader_time_begin()
1609 current_annotation
= "shader time start";
1610 shader_start_time
= get_timestamp();
1614 vec4_visitor::emit_shader_time_end()
1616 current_annotation
= "shader time end";
1617 src_reg shader_end_time
= get_timestamp();
1620 /* Check that there weren't any timestamp reset events (assuming these
1621 * were the only two timestamp reads that happened).
1623 src_reg reset_end
= shader_end_time
;
1624 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1625 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1626 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1628 emit(IF(BRW_PREDICATE_NORMAL
));
1630 /* Take the current timestamp and get the delta. */
1631 shader_start_time
.negate
= true;
1632 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1633 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1635 /* If there were no instructions between the two timestamp gets, the diff
1636 * is 2 cycles. Remove that overhead, so I can forget about that when
1637 * trying to determine the time taken for single instructions.
1639 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1641 emit_shader_time_write(st_base
, src_reg(diff
));
1642 emit_shader_time_write(st_written
, src_reg(1u));
1643 emit(BRW_OPCODE_ELSE
);
1644 emit_shader_time_write(st_reset
, src_reg(1u));
1645 emit(BRW_OPCODE_ENDIF
);
1649 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1652 int shader_time_index
=
1653 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1656 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1658 dst_reg offset
= dst
;
1662 offset
.type
= BRW_REGISTER_TYPE_UD
;
1663 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1665 time
.type
= BRW_REGISTER_TYPE_UD
;
1666 emit(MOV(time
, src_reg(value
)));
1668 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1674 sanity_param_count
= prog
->Parameters
->NumParameters
;
1676 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1677 emit_shader_time_begin();
1679 assign_common_binding_table_offsets(0);
1683 /* Generate VS IR for main(). (the visitor only descends into
1684 * functions called "main").
1687 visit_instructions(shader
->base
.ir
);
1689 emit_program_code();
1693 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1694 setup_uniform_clipplane_values();
1698 /* Before any optimization, push array accesses out to scratch
1699 * space where we need them to be. This pass may allocate new
1700 * virtual GRFs, so we want to do it early. It also makes sure
1701 * that we have reladdr computations available for CSE, since we'll
1702 * often do repeated subexpressions for those.
1705 move_grf_array_access_to_scratch();
1706 move_uniform_array_access_to_pull_constants();
1708 /* The ARB_vertex_program frontend emits pull constant loads directly
1709 * rather than using reladdr, so we don't need to walk through all the
1710 * instructions looking for things to move. There isn't anything.
1712 * We do still need to split things to vec4 size.
1714 split_uniform_registers();
1716 pack_uniform_registers();
1717 move_push_constants_to_pull_constants();
1718 split_virtual_grfs();
1723 progress
= dead_code_eliminate() || progress
;
1724 progress
= dead_control_flow_eliminate(this) || progress
;
1725 progress
= opt_copy_propagation() || progress
;
1726 progress
= opt_algebraic() || progress
;
1727 progress
= opt_register_coalesce() || progress
;
1737 /* Debug of register spilling: Go spill everything. */
1738 const int grf_count
= virtual_grf_count
;
1739 float spill_costs
[virtual_grf_count
];
1740 bool no_spill
[virtual_grf_count
];
1741 evaluate_spill_costs(spill_costs
, no_spill
);
1742 for (int i
= 0; i
< grf_count
; i
++) {
1749 while (!reg_allocate()) {
1754 opt_schedule_instructions();
1756 opt_set_dependency_control();
1758 /* If any state parameters were appended, then ParameterValues could have
1759 * been realloced, in which case the driver uniform storage set up by
1760 * _mesa_associate_uniform_storage() would point to freed memory. Make
1761 * sure that didn't happen.
1763 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1768 } /* namespace brw */
1773 * Compile a vertex shader.
1775 * Returns the final assembly and the program's size.
1778 brw_vs_emit(struct brw_context
*brw
,
1779 struct gl_shader_program
*prog
,
1780 struct brw_vs_compile
*c
,
1781 struct brw_vs_prog_data
*prog_data
,
1783 unsigned *final_assembly_size
)
1785 bool start_busy
= false;
1786 double start_time
= 0;
1788 if (unlikely(brw
->perf_debug
)) {
1789 start_busy
= (brw
->batch
.last_bo
&&
1790 drm_intel_bo_busy(brw
->batch
.last_bo
));
1791 start_time
= get_time();
1794 struct brw_shader
*shader
= NULL
;
1796 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1798 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1799 brw_dump_ir(brw
, "vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1801 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1804 prog
->LinkStatus
= false;
1805 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1808 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1814 const unsigned *assembly
= NULL
;
1815 if (brw
->gen
>= 8) {
1816 gen8_vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1817 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1818 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1820 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1821 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1822 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1825 if (unlikely(brw
->perf_debug
) && shader
) {
1826 if (shader
->compiled_once
) {
1827 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1829 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1830 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1831 (get_time() - start_time
) * 1000);
1833 shader
->compiled_once
= true;
1841 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1842 struct brw_vec4_prog_key
*key
,
1843 GLuint id
, struct gl_program
*prog
)
1845 key
->program_string_id
= id
;
1846 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1848 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1849 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1850 if (prog
->ShadowSamplers
& (1 << i
)) {
1851 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1852 key
->tex
.swizzles
[i
] =
1853 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1855 /* Color sampler: assume no swizzling. */
1856 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;