2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
115 src_reg::src_reg(dst_reg reg
)
119 this->file
= reg
.file
;
121 this->reg_offset
= reg
.reg_offset
;
122 this->type
= reg
.type
;
123 this->reladdr
= reg
.reladdr
;
124 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
130 for (int i
= 0; i
< 4; i
++) {
131 if (!(reg
.writemask
& (1 << i
)))
134 swizzles
[next_chan
++] = last
= i
;
137 for (; next_chan
< 4; next_chan
++) {
138 swizzles
[next_chan
] = last
;
141 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
142 swizzles
[2], swizzles
[3]);
148 memset(this, 0, sizeof(*this));
149 this->file
= BAD_FILE
;
150 this->writemask
= WRITEMASK_XYZW
;
158 dst_reg::dst_reg(register_file file
, int reg
)
166 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
173 this->type
= brw_type_for_base_type(type
);
174 this->writemask
= writemask
;
177 dst_reg::dst_reg(struct brw_reg reg
)
182 this->fixed_hw_reg
= reg
;
185 dst_reg::dst_reg(src_reg reg
)
189 this->file
= reg
.file
;
191 this->reg_offset
= reg
.reg_offset
;
192 this->type
= reg
.type
;
193 /* How should we do writemasking when converting from a src_reg? It seems
194 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
195 * what about for src.wx? Just special-case src.xxxx for now.
197 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
198 this->writemask
= WRITEMASK_X
;
200 this->writemask
= WRITEMASK_XYZW
;
201 this->reladdr
= reg
.reladdr
;
202 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
206 vec4_instruction::is_send_from_grf()
209 case SHADER_OPCODE_SHADER_TIME_ADD
:
210 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
218 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
220 if (brw
->gen
== 6 && inst
->is_math())
223 if (inst
->is_send_from_grf())
226 if (!inst
->can_do_source_mods())
233 * Returns how many MRFs an opcode will write over.
235 * Note that this is not the 0 or 1 implied writes in an actual gen
236 * instruction -- the generate_* functions generate additional MOVs
240 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
245 switch (inst
->opcode
) {
246 case SHADER_OPCODE_RCP
:
247 case SHADER_OPCODE_RSQ
:
248 case SHADER_OPCODE_SQRT
:
249 case SHADER_OPCODE_EXP2
:
250 case SHADER_OPCODE_LOG2
:
251 case SHADER_OPCODE_SIN
:
252 case SHADER_OPCODE_COS
:
254 case SHADER_OPCODE_INT_QUOTIENT
:
255 case SHADER_OPCODE_INT_REMAINDER
:
256 case SHADER_OPCODE_POW
:
258 case VS_OPCODE_URB_WRITE
:
260 case VS_OPCODE_PULL_CONSTANT_LOAD
:
262 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
264 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
266 case GS_OPCODE_URB_WRITE
:
267 case GS_OPCODE_THREAD_END
:
269 case SHADER_OPCODE_SHADER_TIME_ADD
:
271 case SHADER_OPCODE_TEX
:
272 case SHADER_OPCODE_TXL
:
273 case SHADER_OPCODE_TXD
:
274 case SHADER_OPCODE_TXF
:
275 case SHADER_OPCODE_TXF_MS
:
276 case SHADER_OPCODE_TXS
:
277 case SHADER_OPCODE_TG4
:
278 case SHADER_OPCODE_TG4_OFFSET
:
279 return inst
->header_present
? 1 : 0;
280 case SHADER_OPCODE_UNTYPED_ATOMIC
:
281 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
284 assert(!"not reached");
290 src_reg::equals(src_reg
*r
)
292 return (file
== r
->file
&&
294 reg_offset
== r
->reg_offset
&&
296 negate
== r
->negate
&&
298 swizzle
== r
->swizzle
&&
299 !reladdr
&& !r
->reladdr
&&
300 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
301 sizeof(fixed_hw_reg
)) == 0 &&
306 * Must be called after calculate_live_intervales() to remove unused
307 * writes to registers -- register allocation will fail otherwise
308 * because something deffed but not used won't be considered to
309 * interfere with other regs.
312 vec4_visitor::dead_code_eliminate()
314 bool progress
= false;
317 calculate_live_intervals();
319 foreach_list_safe(node
, &this->instructions
) {
320 vec4_instruction
*inst
= (vec4_instruction
*)node
;
322 if (inst
->dst
.file
== GRF
&& !inst
->has_side_effects()) {
323 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
324 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
325 /* Don't dead code eliminate instructions that write to the
326 * accumulator as a side-effect. Instead just set the destination
327 * to the null register to free it.
329 switch (inst
->opcode
) {
330 case BRW_OPCODE_ADDC
:
331 case BRW_OPCODE_SUBB
:
332 case BRW_OPCODE_MACH
:
333 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
347 invalidate_live_intervals();
353 vec4_visitor::split_uniform_registers()
355 /* Prior to this, uniforms have been in an array sized according to
356 * the number of vector uniforms present, sparsely filled (so an
357 * aggregate results in reg indices being skipped over). Now we're
358 * going to cut those aggregates up so each .reg index is one
359 * vector. The goal is to make elimination of unused uniform
360 * components easier later.
362 foreach_list(node
, &this->instructions
) {
363 vec4_instruction
*inst
= (vec4_instruction
*)node
;
365 for (int i
= 0 ; i
< 3; i
++) {
366 if (inst
->src
[i
].file
!= UNIFORM
)
369 assert(!inst
->src
[i
].reladdr
);
371 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
372 inst
->src
[i
].reg_offset
= 0;
376 /* Update that everything is now vector-sized. */
377 for (int i
= 0; i
< this->uniforms
; i
++) {
378 this->uniform_size
[i
] = 1;
383 vec4_visitor::pack_uniform_registers()
385 bool uniform_used
[this->uniforms
];
386 int new_loc
[this->uniforms
];
387 int new_chan
[this->uniforms
];
389 memset(uniform_used
, 0, sizeof(uniform_used
));
390 memset(new_loc
, 0, sizeof(new_loc
));
391 memset(new_chan
, 0, sizeof(new_chan
));
393 /* Find which uniform vectors are actually used by the program. We
394 * expect unused vector elements when we've moved array access out
395 * to pull constants, and from some GLSL code generators like wine.
397 foreach_list(node
, &this->instructions
) {
398 vec4_instruction
*inst
= (vec4_instruction
*)node
;
400 for (int i
= 0 ; i
< 3; i
++) {
401 if (inst
->src
[i
].file
!= UNIFORM
)
404 uniform_used
[inst
->src
[i
].reg
] = true;
408 int new_uniform_count
= 0;
410 /* Now, figure out a packing of the live uniform vectors into our
413 for (int src
= 0; src
< uniforms
; src
++) {
414 int size
= this->uniform_vector_size
[src
];
416 if (!uniform_used
[src
]) {
417 this->uniform_vector_size
[src
] = 0;
422 /* Find the lowest place we can slot this uniform in. */
423 for (dst
= 0; dst
< src
; dst
++) {
424 if (this->uniform_vector_size
[dst
] + size
<= 4)
433 new_chan
[src
] = this->uniform_vector_size
[dst
];
435 /* Move the references to the data */
436 for (int j
= 0; j
< size
; j
++) {
437 prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
438 prog_data
->param
[src
* 4 + j
];
441 this->uniform_vector_size
[dst
] += size
;
442 this->uniform_vector_size
[src
] = 0;
445 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
448 this->uniforms
= new_uniform_count
;
450 /* Now, update the instructions for our repacked uniforms. */
451 foreach_list(node
, &this->instructions
) {
452 vec4_instruction
*inst
= (vec4_instruction
*)node
;
454 for (int i
= 0 ; i
< 3; i
++) {
455 int src
= inst
->src
[i
].reg
;
457 if (inst
->src
[i
].file
!= UNIFORM
)
460 inst
->src
[i
].reg
= new_loc
[src
];
462 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
463 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
464 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
465 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
466 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
472 src_reg::is_zero() const
477 if (type
== BRW_REGISTER_TYPE_F
) {
485 src_reg::is_one() const
490 if (type
== BRW_REGISTER_TYPE_F
) {
498 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
500 * While GLSL IR also performs this optimization, we end up with it in
501 * our instruction stream for a couple of reasons. One is that we
502 * sometimes generate silly instructions, for example in array access
503 * where we'll generate "ADD offset, index, base" even if base is 0.
504 * The other is that GLSL IR's constant propagation doesn't track the
505 * components of aggregates, so some VS patterns (initialize matrix to
506 * 0, accumulate in vertex blending factors) end up breaking down to
507 * instructions involving 0.
510 vec4_visitor::opt_algebraic()
512 bool progress
= false;
514 foreach_list(node
, &this->instructions
) {
515 vec4_instruction
*inst
= (vec4_instruction
*)node
;
517 switch (inst
->opcode
) {
519 if (inst
->src
[1].is_zero()) {
520 inst
->opcode
= BRW_OPCODE_MOV
;
521 inst
->src
[1] = src_reg();
527 if (inst
->src
[1].is_zero()) {
528 inst
->opcode
= BRW_OPCODE_MOV
;
529 switch (inst
->src
[0].type
) {
530 case BRW_REGISTER_TYPE_F
:
531 inst
->src
[0] = src_reg(0.0f
);
533 case BRW_REGISTER_TYPE_D
:
534 inst
->src
[0] = src_reg(0);
536 case BRW_REGISTER_TYPE_UD
:
537 inst
->src
[0] = src_reg(0u);
540 assert(!"not reached");
541 inst
->src
[0] = src_reg(0.0f
);
544 inst
->src
[1] = src_reg();
546 } else if (inst
->src
[1].is_one()) {
547 inst
->opcode
= BRW_OPCODE_MOV
;
548 inst
->src
[1] = src_reg();
558 invalidate_live_intervals();
564 * Only a limited number of hardware registers may be used for push
565 * constants, so this turns access to the overflowed constants into
569 vec4_visitor::move_push_constants_to_pull_constants()
571 int pull_constant_loc
[this->uniforms
];
573 /* Only allow 32 registers (256 uniform components) as push constants,
574 * which is the limit on gen6.
576 int max_uniform_components
= 32 * 8;
577 if (this->uniforms
* 4 <= max_uniform_components
)
580 /* Make some sort of choice as to which uniforms get sent to pull
581 * constants. We could potentially do something clever here like
582 * look for the most infrequently used uniform vec4s, but leave
585 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
586 pull_constant_loc
[i
/ 4] = -1;
588 if (i
>= max_uniform_components
) {
589 const float **values
= &prog_data
->param
[i
];
591 /* Try to find an existing copy of this uniform in the pull
592 * constants if it was part of an array access already.
594 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
597 for (matches
= 0; matches
< 4; matches
++) {
598 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
603 pull_constant_loc
[i
/ 4] = j
/ 4;
608 if (pull_constant_loc
[i
/ 4] == -1) {
609 assert(prog_data
->nr_pull_params
% 4 == 0);
610 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
612 for (int j
= 0; j
< 4; j
++) {
613 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
619 /* Now actually rewrite usage of the things we've moved to pull
622 foreach_list_safe(node
, &this->instructions
) {
623 vec4_instruction
*inst
= (vec4_instruction
*)node
;
625 for (int i
= 0 ; i
< 3; i
++) {
626 if (inst
->src
[i
].file
!= UNIFORM
||
627 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
630 int uniform
= inst
->src
[i
].reg
;
632 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
634 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
635 pull_constant_loc
[uniform
]);
637 inst
->src
[i
].file
= temp
.file
;
638 inst
->src
[i
].reg
= temp
.reg
;
639 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
640 inst
->src
[i
].reladdr
= NULL
;
644 /* Repack push constants to remove the now-unused ones. */
645 pack_uniform_registers();
649 * Sets the dependency control fields on instructions after register
650 * allocation and before the generator is run.
652 * When you have a sequence of instructions like:
654 * DP4 temp.x vertex uniform[0]
655 * DP4 temp.y vertex uniform[0]
656 * DP4 temp.z vertex uniform[0]
657 * DP4 temp.w vertex uniform[0]
659 * The hardware doesn't know that it can actually run the later instructions
660 * while the previous ones are in flight, producing stalls. However, we have
661 * manual fields we can set in the instructions that let it do so.
664 vec4_visitor::opt_set_dependency_control()
666 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
667 uint8_t grf_channels_written
[BRW_MAX_GRF
];
668 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
669 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
671 cfg_t
cfg(&instructions
);
673 assert(prog_data
->total_grf
||
674 !"Must be called after register allocation");
676 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
677 bblock_t
*bblock
= cfg
.blocks
[i
];
678 vec4_instruction
*inst
;
680 memset(last_grf_write
, 0, sizeof(last_grf_write
));
681 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
683 for (inst
= (vec4_instruction
*)bblock
->start
;
684 inst
!= (vec4_instruction
*)bblock
->end
->next
;
685 inst
= (vec4_instruction
*)inst
->next
) {
686 /* If we read from a register that we were doing dependency control
687 * on, don't do dependency control across the read.
689 for (int i
= 0; i
< 3; i
++) {
690 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
691 if (inst
->src
[i
].file
== GRF
) {
692 last_grf_write
[reg
] = NULL
;
693 } else if (inst
->src
[i
].file
== HW_REG
) {
694 memset(last_grf_write
, 0, sizeof(last_grf_write
));
697 assert(inst
->src
[i
].file
!= MRF
);
700 /* In the presence of send messages, totally interrupt dependency
701 * control. They're long enough that the chance of dependency
702 * control around them just doesn't matter.
705 memset(last_grf_write
, 0, sizeof(last_grf_write
));
706 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
710 /* It looks like setting dependency control on a predicated
711 * instruction hangs the GPU.
713 if (inst
->predicate
) {
714 memset(last_grf_write
, 0, sizeof(last_grf_write
));
715 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
719 /* Now, see if we can do dependency control for this instruction
720 * against a previous one writing to its destination.
722 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
723 if (inst
->dst
.file
== GRF
) {
724 if (last_grf_write
[reg
] &&
725 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
726 last_grf_write
[reg
]->no_dd_clear
= true;
727 inst
->no_dd_check
= true;
729 grf_channels_written
[reg
] = 0;
732 last_grf_write
[reg
] = inst
;
733 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
734 } else if (inst
->dst
.file
== MRF
) {
735 if (last_mrf_write
[reg
] &&
736 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
737 last_mrf_write
[reg
]->no_dd_clear
= true;
738 inst
->no_dd_check
= true;
740 mrf_channels_written
[reg
] = 0;
743 last_mrf_write
[reg
] = inst
;
744 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
745 } else if (inst
->dst
.reg
== HW_REG
) {
746 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
747 memset(last_grf_write
, 0, sizeof(last_grf_write
));
748 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
749 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
756 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
760 /* If this instruction sets anything not referenced by swizzle, then we'd
761 * totally break it when we reswizzle.
763 if (dst
.writemask
& ~swizzle_mask
)
772 /* Check if there happens to be no reswizzling required. */
773 for (int c
= 0; c
< 4; c
++) {
774 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
775 /* Skip components of the swizzle not used by the dst. */
776 if (!(dst_writemask
& (1 << c
)))
779 /* We don't do the reswizzling yet, so just sanity check that we
790 * For any channels in the swizzle's source that were populated by this
791 * instruction, rewrite the instruction to put the appropriate result directly
794 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
797 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
799 int new_writemask
= 0;
805 for (int c
= 0; c
< 4; c
++) {
806 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
807 /* Skip components of the swizzle not used by the dst. */
808 if (!(dst_writemask
& (1 << c
)))
810 /* If we were populating this component, then populate the
811 * corresponding channel of the new dst.
813 if (dst
.writemask
& bit
)
814 new_writemask
|= (1 << c
);
816 dst
.writemask
= new_writemask
;
819 for (int c
= 0; c
< 4; c
++) {
820 /* Skip components of the swizzle not used by the dst. */
821 if (!(dst_writemask
& (1 << c
)))
824 /* We don't do the reswizzling yet, so just sanity check that we
827 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
834 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
835 * just written and then MOVed into another reg and making the original write
836 * of the GRF write directly to the final destination instead.
839 vec4_visitor::opt_register_coalesce()
841 bool progress
= false;
844 calculate_live_intervals();
846 foreach_list_safe(node
, &this->instructions
) {
847 vec4_instruction
*inst
= (vec4_instruction
*)node
;
852 if (inst
->opcode
!= BRW_OPCODE_MOV
||
853 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
855 inst
->src
[0].file
!= GRF
||
856 inst
->dst
.type
!= inst
->src
[0].type
||
857 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
860 bool to_mrf
= (inst
->dst
.file
== MRF
);
862 /* Can't coalesce this GRF if someone else was going to
865 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
868 /* We need to check interference with the final destination between this
869 * instruction and the earliest instruction involved in writing the GRF
870 * we're eliminating. To do that, keep track of which of our source
871 * channels we've seen initialized.
873 bool chans_needed
[4] = {false, false, false, false};
874 int chans_remaining
= 0;
875 int swizzle_mask
= 0;
876 for (int i
= 0; i
< 4; i
++) {
877 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
879 if (!(inst
->dst
.writemask
& (1 << i
)))
882 swizzle_mask
|= (1 << chan
);
884 if (!chans_needed
[chan
]) {
885 chans_needed
[chan
] = true;
890 /* Now walk up the instruction stream trying to see if we can rewrite
891 * everything writing to the temporary to write into the destination
894 vec4_instruction
*scan_inst
;
895 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
896 scan_inst
->prev
!= NULL
;
897 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
898 if (scan_inst
->dst
.file
== GRF
&&
899 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
900 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
901 /* Found something writing to the reg we want to coalesce away. */
903 /* SEND instructions can't have MRF as a destination. */
908 /* gen6 math instructions must have the destination be
909 * GRF, so no compute-to-MRF for them.
911 if (scan_inst
->is_math()) {
917 /* If we can't handle the swizzle, bail. */
918 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
919 inst
->src
[0].swizzle
,
924 /* Mark which channels we found unconditional writes for. */
925 if (!scan_inst
->predicate
) {
926 for (int i
= 0; i
< 4; i
++) {
927 if (scan_inst
->dst
.writemask
& (1 << i
) &&
929 chans_needed
[i
] = false;
935 if (chans_remaining
== 0)
939 /* We don't handle flow control here. Most computation of values
940 * that could be coalesced happens just before their use.
942 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
943 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
944 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
945 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
949 /* You can't read from an MRF, so if someone else reads our MRF's
950 * source GRF that we wanted to rewrite, that stops us. If it's a
951 * GRF we're trying to coalesce to, we don't actually handle
952 * rewriting sources so bail in that case as well.
954 bool interfered
= false;
955 for (int i
= 0; i
< 3; i
++) {
956 if (scan_inst
->src
[i
].file
== GRF
&&
957 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
958 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
965 /* If somebody else writes our destination here, we can't coalesce
968 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
969 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
973 /* Check for reads of the register we're trying to coalesce into. We
974 * can't go rewriting instructions above that to put some other value
975 * in the register instead.
977 if (to_mrf
&& scan_inst
->mlen
> 0) {
978 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
979 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
983 for (int i
= 0; i
< 3; i
++) {
984 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
985 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
986 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
995 if (chans_remaining
== 0) {
996 /* If we've made it here, we have an MOV we want to coalesce out, and
997 * a scan_inst pointing to the earliest instruction involved in
998 * computing the value. Now go rewrite the instruction stream
1002 while (scan_inst
!= inst
) {
1003 if (scan_inst
->dst
.file
== GRF
&&
1004 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1005 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1006 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1007 inst
->src
[0].swizzle
);
1008 scan_inst
->dst
.file
= inst
->dst
.file
;
1009 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1010 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1011 scan_inst
->saturate
|= inst
->saturate
;
1013 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1021 invalidate_live_intervals();
1027 * Splits virtual GRFs requesting more than one contiguous physical register.
1029 * We initially create large virtual GRFs for temporary structures, arrays,
1030 * and matrices, so that the dereference visitor functions can add reg_offsets
1031 * to work their way down to the actual member being accessed. But when it
1032 * comes to optimization, we'd like to treat each register as individual
1033 * storage if possible.
1035 * So far, the only thing that might prevent splitting is a send message from
1039 vec4_visitor::split_virtual_grfs()
1041 int num_vars
= this->virtual_grf_count
;
1042 int new_virtual_grf
[num_vars
];
1043 bool split_grf
[num_vars
];
1045 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1047 /* Try to split anything > 0 sized. */
1048 for (int i
= 0; i
< num_vars
; i
++) {
1049 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1052 /* Check that the instructions are compatible with the registers we're trying
1055 foreach_list(node
, &this->instructions
) {
1056 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1058 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1061 if (inst
->is_send_from_grf()) {
1062 for (int i
= 0; i
< 3; i
++) {
1063 if (inst
->src
[i
].file
== GRF
) {
1064 split_grf
[inst
->src
[i
].reg
] = false;
1070 /* Allocate new space for split regs. Note that the virtual
1071 * numbers will be contiguous.
1073 for (int i
= 0; i
< num_vars
; i
++) {
1077 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1078 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1079 int reg
= virtual_grf_alloc(1);
1080 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1083 this->virtual_grf_sizes
[i
] = 1;
1086 foreach_list(node
, &this->instructions
) {
1087 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1089 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1090 inst
->dst
.reg_offset
!= 0) {
1091 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1092 inst
->dst
.reg_offset
- 1);
1093 inst
->dst
.reg_offset
= 0;
1095 for (int i
= 0; i
< 3; i
++) {
1096 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1097 inst
->src
[i
].reg_offset
!= 0) {
1098 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1099 inst
->src
[i
].reg_offset
- 1);
1100 inst
->src
[i
].reg_offset
= 0;
1104 invalidate_live_intervals();
1108 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1110 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1112 printf("%s", brw_instruction_name(inst
->opcode
));
1113 if (inst
->conditional_mod
) {
1114 printf("%s", conditional_modifier
[inst
->conditional_mod
]);
1118 switch (inst
->dst
.file
) {
1120 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1123 printf("m%d", inst
->dst
.reg
);
1126 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1127 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1131 case BRW_ARF_ADDRESS
:
1132 printf("a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1134 case BRW_ARF_ACCUMULATOR
:
1135 printf("acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1138 printf("f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1139 inst
->dst
.fixed_hw_reg
.subnr
);
1142 printf("arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1143 inst
->dst
.fixed_hw_reg
.subnr
);
1147 printf("hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1149 if (inst
->dst
.fixed_hw_reg
.subnr
)
1150 printf("+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1159 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1161 if (inst
->dst
.writemask
& 1)
1163 if (inst
->dst
.writemask
& 2)
1165 if (inst
->dst
.writemask
& 4)
1167 if (inst
->dst
.writemask
& 8)
1170 printf(":%s, ", reg_encoding
[inst
->dst
.type
]);
1172 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1173 if (inst
->src
[i
].negate
)
1175 if (inst
->src
[i
].abs
)
1177 switch (inst
->src
[i
].file
) {
1179 printf("vgrf%d", inst
->src
[i
].reg
);
1182 printf("attr%d", inst
->src
[i
].reg
);
1185 printf("u%d", inst
->src
[i
].reg
);
1188 switch (inst
->src
[i
].type
) {
1189 case BRW_REGISTER_TYPE_F
:
1190 printf("%fF", inst
->src
[i
].imm
.f
);
1192 case BRW_REGISTER_TYPE_D
:
1193 printf("%dD", inst
->src
[i
].imm
.i
);
1195 case BRW_REGISTER_TYPE_UD
:
1196 printf("%uU", inst
->src
[i
].imm
.u
);
1204 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1206 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1208 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1209 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1213 case BRW_ARF_ADDRESS
:
1214 printf("a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1216 case BRW_ARF_ACCUMULATOR
:
1217 printf("acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1220 printf("f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1221 inst
->src
[i
].fixed_hw_reg
.subnr
);
1224 printf("arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1225 inst
->src
[i
].fixed_hw_reg
.subnr
);
1229 printf("hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1231 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1232 printf("+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1233 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1244 if (inst
->src
[i
].reg_offset
)
1245 printf(".%d", inst
->src
[i
].reg_offset
);
1247 if (inst
->src
[i
].file
!= IMM
) {
1248 static const char *chans
[4] = {"x", "y", "z", "w"};
1250 for (int c
= 0; c
< 4; c
++) {
1251 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1255 if (inst
->src
[i
].abs
)
1258 if (inst
->src
[i
].file
!= IMM
) {
1259 printf(":%s", reg_encoding
[inst
->src
[i
].type
]);
1262 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1270 static inline struct brw_reg
1271 attribute_to_hw_reg(int attr
, bool interleaved
)
1274 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1276 return brw_vec8_grf(attr
, 0);
1281 * Replace each register of type ATTR in this->instructions with a reference
1282 * to a fixed HW register.
1284 * If interleaved is true, then each attribute takes up half a register, with
1285 * register N containing attribute 2*N in its first half and attribute 2*N+1
1286 * in its second half (this corresponds to the payload setup used by geometry
1287 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1288 * false, then each attribute takes up a whole register, with register N
1289 * containing attribute N (this corresponds to the payload setup used by
1290 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1293 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1296 foreach_list(node
, &this->instructions
) {
1297 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1299 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1300 if (inst
->dst
.file
== ATTR
) {
1301 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1303 /* All attributes used in the shader need to have been assigned a
1304 * hardware register by the caller
1308 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1309 reg
.type
= inst
->dst
.type
;
1310 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1312 inst
->dst
.file
= HW_REG
;
1313 inst
->dst
.fixed_hw_reg
= reg
;
1316 for (int i
= 0; i
< 3; i
++) {
1317 if (inst
->src
[i
].file
!= ATTR
)
1320 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1322 /* All attributes used in the shader need to have been assigned a
1323 * hardware register by the caller
1327 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1328 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1329 reg
.type
= inst
->src
[i
].type
;
1330 if (inst
->src
[i
].abs
)
1332 if (inst
->src
[i
].negate
)
1335 inst
->src
[i
].file
= HW_REG
;
1336 inst
->src
[i
].fixed_hw_reg
= reg
;
1342 vec4_vs_visitor::setup_attributes(int payload_reg
)
1345 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1346 memset(attribute_map
, 0, sizeof(attribute_map
));
1349 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1350 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1351 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1356 /* VertexID is stored by the VF as the last vertex element, but we
1357 * don't represent it with a flag in inputs_read, so we call it
1360 if (vs_prog_data
->uses_vertexid
) {
1361 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1365 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1367 /* The BSpec says we always have to read at least one thing from
1368 * the VF, and it appears that the hardware wedges otherwise.
1370 if (nr_attributes
== 0)
1373 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1375 unsigned vue_entries
=
1376 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1379 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1381 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1383 return payload_reg
+ nr_attributes
;
1387 vec4_visitor::setup_uniforms(int reg
)
1389 prog_data
->dispatch_grf_start_reg
= reg
;
1391 /* The pre-gen6 VS requires that some push constants get loaded no
1392 * matter what, or the GPU would hang.
1394 if (brw
->gen
< 6 && this->uniforms
== 0) {
1395 this->uniform_vector_size
[this->uniforms
] = 1;
1397 prog_data
->param
= reralloc(NULL
, prog_data
->param
, const float *, 4);
1398 for (unsigned int i
= 0; i
< 4; i
++) {
1399 unsigned int slot
= this->uniforms
* 4 + i
;
1400 static float zero
= 0.0;
1401 prog_data
->param
[slot
] = &zero
;
1407 reg
+= ALIGN(uniforms
, 2) / 2;
1410 prog_data
->nr_params
= this->uniforms
* 4;
1412 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1418 vec4_vs_visitor::setup_payload(void)
1422 /* The payload always contains important data in g0, which contains
1423 * the URB handles that are passed on to the URB write at the end
1424 * of the thread. So, we always start push constants at g1.
1428 reg
= setup_uniforms(reg
);
1430 reg
= setup_attributes(reg
);
1432 this->first_non_payload_grf
= reg
;
1436 vec4_visitor::get_timestamp()
1438 assert(brw
->gen
>= 7);
1440 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1443 BRW_REGISTER_TYPE_UD
,
1444 BRW_VERTICAL_STRIDE_0
,
1446 BRW_HORIZONTAL_STRIDE_4
,
1450 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1452 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1453 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1454 * even if it's not enabled in the dispatch.
1456 mov
->force_writemask_all
= true;
1458 return src_reg(dst
);
1462 vec4_visitor::emit_shader_time_begin()
1464 current_annotation
= "shader time start";
1465 shader_start_time
= get_timestamp();
1469 vec4_visitor::emit_shader_time_end()
1471 current_annotation
= "shader time end";
1472 src_reg shader_end_time
= get_timestamp();
1475 /* Check that there weren't any timestamp reset events (assuming these
1476 * were the only two timestamp reads that happened).
1478 src_reg reset_end
= shader_end_time
;
1479 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1480 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1481 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1483 emit(IF(BRW_PREDICATE_NORMAL
));
1485 /* Take the current timestamp and get the delta. */
1486 shader_start_time
.negate
= true;
1487 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1488 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1490 /* If there were no instructions between the two timestamp gets, the diff
1491 * is 2 cycles. Remove that overhead, so I can forget about that when
1492 * trying to determine the time taken for single instructions.
1494 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1496 emit_shader_time_write(ST_VS
, src_reg(diff
));
1497 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1498 emit(BRW_OPCODE_ELSE
);
1499 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1500 emit(BRW_OPCODE_ENDIF
);
1504 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1507 int shader_time_index
=
1508 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1511 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1513 dst_reg offset
= dst
;
1517 offset
.type
= BRW_REGISTER_TYPE_UD
;
1518 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1520 time
.type
= BRW_REGISTER_TYPE_UD
;
1521 emit(MOV(time
, src_reg(value
)));
1523 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1529 sanity_param_count
= prog
->Parameters
->NumParameters
;
1531 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1532 emit_shader_time_begin();
1534 assign_common_binding_table_offsets(0);
1538 /* Generate VS IR for main(). (the visitor only descends into
1539 * functions called "main").
1542 visit_instructions(shader
->ir
);
1544 emit_program_code();
1548 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1549 setup_uniform_clipplane_values();
1553 /* Before any optimization, push array accesses out to scratch
1554 * space where we need them to be. This pass may allocate new
1555 * virtual GRFs, so we want to do it early. It also makes sure
1556 * that we have reladdr computations available for CSE, since we'll
1557 * often do repeated subexpressions for those.
1560 move_grf_array_access_to_scratch();
1561 move_uniform_array_access_to_pull_constants();
1563 /* The ARB_vertex_program frontend emits pull constant loads directly
1564 * rather than using reladdr, so we don't need to walk through all the
1565 * instructions looking for things to move. There isn't anything.
1567 * We do still need to split things to vec4 size.
1569 split_uniform_registers();
1571 pack_uniform_registers();
1572 move_push_constants_to_pull_constants();
1573 split_virtual_grfs();
1578 progress
= dead_code_eliminate() || progress
;
1579 progress
= dead_control_flow_eliminate(this) || progress
;
1580 progress
= opt_copy_propagation() || progress
;
1581 progress
= opt_algebraic() || progress
;
1582 progress
= opt_register_coalesce() || progress
;
1592 /* Debug of register spilling: Go spill everything. */
1593 const int grf_count
= virtual_grf_count
;
1594 float spill_costs
[virtual_grf_count
];
1595 bool no_spill
[virtual_grf_count
];
1596 evaluate_spill_costs(spill_costs
, no_spill
);
1597 for (int i
= 0; i
< grf_count
; i
++) {
1604 while (!reg_allocate()) {
1609 opt_schedule_instructions();
1611 opt_set_dependency_control();
1613 /* If any state parameters were appended, then ParameterValues could have
1614 * been realloced, in which case the driver uniform storage set up by
1615 * _mesa_associate_uniform_storage() would point to freed memory. Make
1616 * sure that didn't happen.
1618 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1623 } /* namespace brw */
1628 * Compile a vertex shader.
1630 * Returns the final assembly and the program's size.
1633 brw_vs_emit(struct brw_context
*brw
,
1634 struct gl_shader_program
*prog
,
1635 struct brw_vs_compile
*c
,
1636 struct brw_vs_prog_data
*prog_data
,
1638 unsigned *final_assembly_size
)
1640 bool start_busy
= false;
1641 float start_time
= 0;
1643 if (unlikely(brw
->perf_debug
)) {
1644 start_busy
= (brw
->batch
.last_bo
&&
1645 drm_intel_bo_busy(brw
->batch
.last_bo
));
1646 start_time
= get_time();
1649 struct brw_shader
*shader
= NULL
;
1651 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1653 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1655 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1656 _mesa_print_ir(shader
->ir
, NULL
);
1659 printf("ARB_vertex_program %d for native vertex shader\n",
1660 c
->vp
->program
.Base
.Id
);
1661 _mesa_print_program(&c
->vp
->program
.Base
);
1665 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1668 prog
->LinkStatus
= false;
1669 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1672 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1678 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
, mem_ctx
,
1679 INTEL_DEBUG
& DEBUG_VS
);
1680 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1681 final_assembly_size
);
1683 if (unlikely(brw
->perf_debug
) && shader
) {
1684 if (shader
->compiled_once
) {
1685 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1687 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1688 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1689 (get_time() - start_time
) * 1000);
1691 shader
->compiled_once
= true;
1699 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1700 struct brw_vec4_prog_key
*key
,
1701 GLuint id
, struct gl_program
*prog
)
1703 key
->program_string_id
= id
;
1704 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1706 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1707 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1708 if (prog
->ShadowSamplers
& (1 << i
)) {
1709 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1710 key
->tex
.swizzles
[i
] =
1711 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1713 /* Color sampler: assume no swizzling. */
1714 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
1721 brw_vec4_prog_data_compare(const struct brw_vec4_prog_data
*a
,
1722 const struct brw_vec4_prog_data
*b
)
1724 /* Compare all the struct (including the base) up to the pointers. */
1725 if (memcmp(a
, b
, offsetof(struct brw_vec4_prog_data
, param
)))
1728 if (memcmp(a
->param
, b
->param
, a
->nr_params
* sizeof(void *)))
1731 if (memcmp(a
->pull_param
, b
->pull_param
, a
->nr_pull_params
* sizeof(void *)))
1739 brw_vec4_prog_data_free(const struct brw_vec4_prog_data
*prog_data
)
1741 ralloc_free((void *)prog_data
->param
);
1742 ralloc_free((void *)prog_data
->pull_param
);