2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
94 this->fixed_hw_reg
.dw1
.f
= f
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
103 this->fixed_hw_reg
.dw1
.ud
= u
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
112 this->fixed_hw_reg
.dw1
.d
= i
;
115 src_reg::src_reg(struct brw_reg reg
)
120 this->fixed_hw_reg
= reg
;
121 this->type
= reg
.type
;
124 src_reg::src_reg(dst_reg reg
)
128 this->file
= reg
.file
;
130 this->reg_offset
= reg
.reg_offset
;
131 this->type
= reg
.type
;
132 this->reladdr
= reg
.reladdr
;
133 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 for (int i
= 0; i
< 4; i
++) {
140 if (!(reg
.writemask
& (1 << i
)))
143 swizzles
[next_chan
++] = last
= i
;
146 for (; next_chan
< 4; next_chan
++) {
147 swizzles
[next_chan
] = last
;
150 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
151 swizzles
[2], swizzles
[3]);
157 memset(this, 0, sizeof(*this));
158 this->file
= BAD_FILE
;
159 this->writemask
= WRITEMASK_XYZW
;
167 dst_reg::dst_reg(register_file file
, int reg
)
175 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
182 this->type
= brw_type_for_base_type(type
);
183 this->writemask
= writemask
;
186 dst_reg::dst_reg(struct brw_reg reg
)
191 this->fixed_hw_reg
= reg
;
192 this->type
= reg
.type
;
195 dst_reg::dst_reg(src_reg reg
)
199 this->file
= reg
.file
;
201 this->reg_offset
= reg
.reg_offset
;
202 this->type
= reg
.type
;
203 /* How should we do writemasking when converting from a src_reg? It seems
204 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
205 * what about for src.wx? Just special-case src.xxxx for now.
207 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
208 this->writemask
= WRITEMASK_X
;
210 this->writemask
= WRITEMASK_XYZW
;
211 this->reladdr
= reg
.reladdr
;
212 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
216 vec4_instruction::is_send_from_grf()
219 case SHADER_OPCODE_SHADER_TIME_ADD
:
220 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
228 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
230 if (brw
->gen
== 6 && is_math())
233 if (is_send_from_grf())
236 if (!backend_instruction::can_do_source_mods())
243 * Returns how many MRFs an opcode will write over.
245 * Note that this is not the 0 or 1 implied writes in an actual gen
246 * instruction -- the generate_* functions generate additional MOVs
250 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
255 switch (inst
->opcode
) {
256 case SHADER_OPCODE_RCP
:
257 case SHADER_OPCODE_RSQ
:
258 case SHADER_OPCODE_SQRT
:
259 case SHADER_OPCODE_EXP2
:
260 case SHADER_OPCODE_LOG2
:
261 case SHADER_OPCODE_SIN
:
262 case SHADER_OPCODE_COS
:
264 case SHADER_OPCODE_INT_QUOTIENT
:
265 case SHADER_OPCODE_INT_REMAINDER
:
266 case SHADER_OPCODE_POW
:
268 case VS_OPCODE_URB_WRITE
:
270 case VS_OPCODE_PULL_CONSTANT_LOAD
:
272 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
274 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
276 case GS_OPCODE_URB_WRITE
:
277 case GS_OPCODE_THREAD_END
:
279 case SHADER_OPCODE_SHADER_TIME_ADD
:
281 case SHADER_OPCODE_TEX
:
282 case SHADER_OPCODE_TXL
:
283 case SHADER_OPCODE_TXD
:
284 case SHADER_OPCODE_TXF
:
285 case SHADER_OPCODE_TXF_CMS
:
286 case SHADER_OPCODE_TXF_MCS
:
287 case SHADER_OPCODE_TXS
:
288 case SHADER_OPCODE_TG4
:
289 case SHADER_OPCODE_TG4_OFFSET
:
290 return inst
->header_present
? 1 : 0;
291 case SHADER_OPCODE_UNTYPED_ATOMIC
:
292 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
295 unreachable("not reached");
300 src_reg::equals(const src_reg
&r
) const
302 return (file
== r
.file
&&
304 reg_offset
== r
.reg_offset
&&
306 negate
== r
.negate
&&
308 swizzle
== r
.swizzle
&&
309 !reladdr
&& !r
.reladdr
&&
310 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
311 sizeof(fixed_hw_reg
)) == 0);
315 try_eliminate_instruction(vec4_instruction
*inst
, int new_writemask
,
316 const struct brw_context
*brw
)
318 if (inst
->has_side_effects())
321 if (new_writemask
== 0) {
322 /* Don't dead code eliminate instructions that write to the
323 * accumulator as a side-effect. Instead just set the destination
324 * to the null register to free it.
326 if (inst
->writes_accumulator
|| inst
->writes_flag()) {
327 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
333 } else if (inst
->dst
.writemask
!= new_writemask
) {
334 switch (inst
->opcode
) {
335 case SHADER_OPCODE_TXF_CMS
:
336 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
337 case VS_OPCODE_PULL_CONSTANT_LOAD
:
338 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
341 /* Do not set a writemask on Gen6 for math instructions, those are
342 * executed using align1 mode that does not support a destination mask.
344 if (!(brw
->gen
== 6 && inst
->is_math()) && !inst
->is_tex()) {
345 inst
->dst
.writemask
= new_writemask
;
355 * Must be called after calculate_live_intervals() to remove unused
356 * writes to registers -- register allocation will fail otherwise
357 * because something deffed but not used won't be considered to
358 * interfere with other regs.
361 vec4_visitor::dead_code_eliminate()
363 bool progress
= false;
366 calculate_live_intervals();
368 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
371 bool inst_writes_flag
= false;
372 if (inst
->dst
.file
!= GRF
) {
373 if (inst
->dst
.is_null() && inst
->writes_flag()) {
374 inst_writes_flag
= true;
380 if (inst
->dst
.file
== GRF
) {
381 int write_mask
= inst
->dst
.writemask
;
383 for (int c
= 0; c
< 4; c
++) {
384 if (write_mask
& (1 << c
)) {
385 assert(this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] >= pc
);
386 if (this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] == pc
) {
387 write_mask
&= ~(1 << c
);
392 progress
= try_eliminate_instruction(inst
, write_mask
, brw
) ||
396 if (inst
->predicate
|| inst
->prev
== NULL
)
400 if (inst_writes_flag
) {
401 /* Arbitrarily chosen, other than not being an xyzw writemask. */
402 #define FLAG_WRITEMASK (1 << 5)
403 dead_channels
= inst
->reads_flag() ? 0 : FLAG_WRITEMASK
;
405 dead_channels
= inst
->dst
.writemask
;
407 for (int i
= 0; i
< 3; i
++) {
408 if (inst
->src
[i
].file
!= GRF
||
409 inst
->src
[i
].reg
!= inst
->dst
.reg
)
412 for (int j
= 0; j
< 4; j
++) {
413 int swiz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
414 dead_channels
&= ~(1 << swiz
);
419 for (exec_node
*node
= inst
->prev
, *prev
= node
->prev
;
420 prev
!= NULL
&& dead_channels
!= 0;
421 node
= prev
, prev
= prev
->prev
) {
422 vec4_instruction
*scan_inst
= (vec4_instruction
*)node
;
424 if (scan_inst
->is_control_flow())
427 if (inst_writes_flag
) {
428 if (scan_inst
->dst
.is_null() && scan_inst
->writes_flag()) {
432 } else if (scan_inst
->reads_flag()) {
437 if (inst
->dst
.file
== scan_inst
->dst
.file
&&
438 inst
->dst
.reg
== scan_inst
->dst
.reg
&&
439 inst
->dst
.reg_offset
== scan_inst
->dst
.reg_offset
) {
440 int new_writemask
= scan_inst
->dst
.writemask
& ~dead_channels
;
442 progress
= try_eliminate_instruction(scan_inst
, new_writemask
, brw
) ||
446 for (int i
= 0; i
< 3; i
++) {
447 if (scan_inst
->src
[i
].file
!= inst
->dst
.file
||
448 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
)
451 for (int j
= 0; j
< 4; j
++) {
452 int swiz
= BRW_GET_SWZ(scan_inst
->src
[i
].swizzle
, j
);
453 dead_channels
&= ~(1 << swiz
);
460 invalidate_live_intervals();
466 vec4_visitor::split_uniform_registers()
468 /* Prior to this, uniforms have been in an array sized according to
469 * the number of vector uniforms present, sparsely filled (so an
470 * aggregate results in reg indices being skipped over). Now we're
471 * going to cut those aggregates up so each .reg index is one
472 * vector. The goal is to make elimination of unused uniform
473 * components easier later.
475 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
476 for (int i
= 0 ; i
< 3; i
++) {
477 if (inst
->src
[i
].file
!= UNIFORM
)
480 assert(!inst
->src
[i
].reladdr
);
482 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
483 inst
->src
[i
].reg_offset
= 0;
487 /* Update that everything is now vector-sized. */
488 for (int i
= 0; i
< this->uniforms
; i
++) {
489 this->uniform_size
[i
] = 1;
494 vec4_visitor::pack_uniform_registers()
496 bool uniform_used
[this->uniforms
];
497 int new_loc
[this->uniforms
];
498 int new_chan
[this->uniforms
];
500 memset(uniform_used
, 0, sizeof(uniform_used
));
501 memset(new_loc
, 0, sizeof(new_loc
));
502 memset(new_chan
, 0, sizeof(new_chan
));
504 /* Find which uniform vectors are actually used by the program. We
505 * expect unused vector elements when we've moved array access out
506 * to pull constants, and from some GLSL code generators like wine.
508 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
509 for (int i
= 0 ; i
< 3; i
++) {
510 if (inst
->src
[i
].file
!= UNIFORM
)
513 uniform_used
[inst
->src
[i
].reg
] = true;
517 int new_uniform_count
= 0;
519 /* Now, figure out a packing of the live uniform vectors into our
522 for (int src
= 0; src
< uniforms
; src
++) {
523 assert(src
< uniform_array_size
);
524 int size
= this->uniform_vector_size
[src
];
526 if (!uniform_used
[src
]) {
527 this->uniform_vector_size
[src
] = 0;
532 /* Find the lowest place we can slot this uniform in. */
533 for (dst
= 0; dst
< src
; dst
++) {
534 if (this->uniform_vector_size
[dst
] + size
<= 4)
543 new_chan
[src
] = this->uniform_vector_size
[dst
];
545 /* Move the references to the data */
546 for (int j
= 0; j
< size
; j
++) {
547 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
548 stage_prog_data
->param
[src
* 4 + j
];
551 this->uniform_vector_size
[dst
] += size
;
552 this->uniform_vector_size
[src
] = 0;
555 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
558 this->uniforms
= new_uniform_count
;
560 /* Now, update the instructions for our repacked uniforms. */
561 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
562 for (int i
= 0 ; i
< 3; i
++) {
563 int src
= inst
->src
[i
].reg
;
565 if (inst
->src
[i
].file
!= UNIFORM
)
568 inst
->src
[i
].reg
= new_loc
[src
];
570 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
571 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
572 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
573 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
574 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
580 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
582 * While GLSL IR also performs this optimization, we end up with it in
583 * our instruction stream for a couple of reasons. One is that we
584 * sometimes generate silly instructions, for example in array access
585 * where we'll generate "ADD offset, index, base" even if base is 0.
586 * The other is that GLSL IR's constant propagation doesn't track the
587 * components of aggregates, so some VS patterns (initialize matrix to
588 * 0, accumulate in vertex blending factors) end up breaking down to
589 * instructions involving 0.
592 vec4_visitor::opt_algebraic()
594 bool progress
= false;
596 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
597 switch (inst
->opcode
) {
599 if (inst
->src
[1].is_zero()) {
600 inst
->opcode
= BRW_OPCODE_MOV
;
601 inst
->src
[1] = src_reg();
607 if (inst
->src
[1].is_zero()) {
608 inst
->opcode
= BRW_OPCODE_MOV
;
609 switch (inst
->src
[0].type
) {
610 case BRW_REGISTER_TYPE_F
:
611 inst
->src
[0] = src_reg(0.0f
);
613 case BRW_REGISTER_TYPE_D
:
614 inst
->src
[0] = src_reg(0);
616 case BRW_REGISTER_TYPE_UD
:
617 inst
->src
[0] = src_reg(0u);
620 unreachable("not reached");
622 inst
->src
[1] = src_reg();
624 } else if (inst
->src
[1].is_one()) {
625 inst
->opcode
= BRW_OPCODE_MOV
;
626 inst
->src
[1] = src_reg();
636 invalidate_live_intervals();
642 * Only a limited number of hardware registers may be used for push
643 * constants, so this turns access to the overflowed constants into
647 vec4_visitor::move_push_constants_to_pull_constants()
649 int pull_constant_loc
[this->uniforms
];
651 /* Only allow 32 registers (256 uniform components) as push constants,
652 * which is the limit on gen6.
654 * If changing this value, note the limitation about total_regs in
657 int max_uniform_components
= 32 * 8;
658 if (this->uniforms
* 4 <= max_uniform_components
)
661 /* Make some sort of choice as to which uniforms get sent to pull
662 * constants. We could potentially do something clever here like
663 * look for the most infrequently used uniform vec4s, but leave
666 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
667 pull_constant_loc
[i
/ 4] = -1;
669 if (i
>= max_uniform_components
) {
670 const float **values
= &stage_prog_data
->param
[i
];
672 /* Try to find an existing copy of this uniform in the pull
673 * constants if it was part of an array access already.
675 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
678 for (matches
= 0; matches
< 4; matches
++) {
679 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
684 pull_constant_loc
[i
/ 4] = j
/ 4;
689 if (pull_constant_loc
[i
/ 4] == -1) {
690 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
691 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
693 for (int j
= 0; j
< 4; j
++) {
694 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
701 /* Now actually rewrite usage of the things we've moved to pull
704 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
705 for (int i
= 0 ; i
< 3; i
++) {
706 if (inst
->src
[i
].file
!= UNIFORM
||
707 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
710 int uniform
= inst
->src
[i
].reg
;
712 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
714 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
715 pull_constant_loc
[uniform
]);
717 inst
->src
[i
].file
= temp
.file
;
718 inst
->src
[i
].reg
= temp
.reg
;
719 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
720 inst
->src
[i
].reladdr
= NULL
;
724 /* Repack push constants to remove the now-unused ones. */
725 pack_uniform_registers();
729 * Sets the dependency control fields on instructions after register
730 * allocation and before the generator is run.
732 * When you have a sequence of instructions like:
734 * DP4 temp.x vertex uniform[0]
735 * DP4 temp.y vertex uniform[0]
736 * DP4 temp.z vertex uniform[0]
737 * DP4 temp.w vertex uniform[0]
739 * The hardware doesn't know that it can actually run the later instructions
740 * while the previous ones are in flight, producing stalls. However, we have
741 * manual fields we can set in the instructions that let it do so.
744 vec4_visitor::opt_set_dependency_control()
746 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
747 uint8_t grf_channels_written
[BRW_MAX_GRF
];
748 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
749 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
753 assert(prog_data
->total_grf
||
754 !"Must be called after register allocation");
756 for (int i
= 0; i
< cfg
->num_blocks
; i
++) {
757 bblock_t
*bblock
= cfg
->blocks
[i
];
759 memset(last_grf_write
, 0, sizeof(last_grf_write
));
760 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
762 foreach_inst_in_block (vec4_instruction
, inst
, bblock
) {
763 /* If we read from a register that we were doing dependency control
764 * on, don't do dependency control across the read.
766 for (int i
= 0; i
< 3; i
++) {
767 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
768 if (inst
->src
[i
].file
== GRF
) {
769 last_grf_write
[reg
] = NULL
;
770 } else if (inst
->src
[i
].file
== HW_REG
) {
771 memset(last_grf_write
, 0, sizeof(last_grf_write
));
774 assert(inst
->src
[i
].file
!= MRF
);
777 /* In the presence of send messages, totally interrupt dependency
778 * control. They're long enough that the chance of dependency
779 * control around them just doesn't matter.
782 memset(last_grf_write
, 0, sizeof(last_grf_write
));
783 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
787 /* It looks like setting dependency control on a predicated
788 * instruction hangs the GPU.
790 if (inst
->predicate
) {
791 memset(last_grf_write
, 0, sizeof(last_grf_write
));
792 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
796 /* Dependency control does not work well over math instructions.
798 if (inst
->is_math()) {
799 memset(last_grf_write
, 0, sizeof(last_grf_write
));
800 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
804 /* Now, see if we can do dependency control for this instruction
805 * against a previous one writing to its destination.
807 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
808 if (inst
->dst
.file
== GRF
) {
809 if (last_grf_write
[reg
] &&
810 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
811 last_grf_write
[reg
]->no_dd_clear
= true;
812 inst
->no_dd_check
= true;
814 grf_channels_written
[reg
] = 0;
817 last_grf_write
[reg
] = inst
;
818 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
819 } else if (inst
->dst
.file
== MRF
) {
820 if (last_mrf_write
[reg
] &&
821 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
822 last_mrf_write
[reg
]->no_dd_clear
= true;
823 inst
->no_dd_check
= true;
825 mrf_channels_written
[reg
] = 0;
828 last_mrf_write
[reg
] = inst
;
829 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
830 } else if (inst
->dst
.reg
== HW_REG
) {
831 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
832 memset(last_grf_write
, 0, sizeof(last_grf_write
));
833 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
834 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
841 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
845 /* If this instruction sets anything not referenced by swizzle, then we'd
846 * totally break it when we reswizzle.
848 if (dst
.writemask
& ~swizzle_mask
)
857 /* Check if there happens to be no reswizzling required. */
858 for (int c
= 0; c
< 4; c
++) {
859 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
860 /* Skip components of the swizzle not used by the dst. */
861 if (!(dst_writemask
& (1 << c
)))
864 /* We don't do the reswizzling yet, so just sanity check that we
875 * For any channels in the swizzle's source that were populated by this
876 * instruction, rewrite the instruction to put the appropriate result directly
879 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
882 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
884 int new_writemask
= 0;
890 for (int c
= 0; c
< 4; c
++) {
891 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
892 /* Skip components of the swizzle not used by the dst. */
893 if (!(dst_writemask
& (1 << c
)))
895 /* If we were populating this component, then populate the
896 * corresponding channel of the new dst.
898 if (dst
.writemask
& bit
)
899 new_writemask
|= (1 << c
);
901 dst
.writemask
= new_writemask
;
904 for (int c
= 0; c
< 4; c
++) {
905 /* Skip components of the swizzle not used by the dst. */
906 if (!(dst_writemask
& (1 << c
)))
909 /* We don't do the reswizzling yet, so just sanity check that we
912 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
919 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
920 * just written and then MOVed into another reg and making the original write
921 * of the GRF write directly to the final destination instead.
924 vec4_visitor::opt_register_coalesce()
926 bool progress
= false;
929 calculate_live_intervals();
931 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
935 if (inst
->opcode
!= BRW_OPCODE_MOV
||
936 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
938 inst
->src
[0].file
!= GRF
||
939 inst
->dst
.type
!= inst
->src
[0].type
||
940 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
943 bool to_mrf
= (inst
->dst
.file
== MRF
);
945 /* Can't coalesce this GRF if someone else was going to
948 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
949 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
950 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
951 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
954 /* We need to check interference with the final destination between this
955 * instruction and the earliest instruction involved in writing the GRF
956 * we're eliminating. To do that, keep track of which of our source
957 * channels we've seen initialized.
959 bool chans_needed
[4] = {false, false, false, false};
960 int chans_remaining
= 0;
961 int swizzle_mask
= 0;
962 for (int i
= 0; i
< 4; i
++) {
963 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
965 if (!(inst
->dst
.writemask
& (1 << i
)))
968 swizzle_mask
|= (1 << chan
);
970 if (!chans_needed
[chan
]) {
971 chans_needed
[chan
] = true;
976 /* Now walk up the instruction stream trying to see if we can rewrite
977 * everything writing to the temporary to write into the destination
980 vec4_instruction
*scan_inst
;
981 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
982 scan_inst
->prev
!= NULL
;
983 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
984 if (scan_inst
->dst
.file
== GRF
&&
985 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
986 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
987 /* Found something writing to the reg we want to coalesce away. */
989 /* SEND instructions can't have MRF as a destination. */
994 /* gen6 math instructions must have the destination be
995 * GRF, so no compute-to-MRF for them.
997 if (scan_inst
->is_math()) {
1003 /* If we can't handle the swizzle, bail. */
1004 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
1005 inst
->src
[0].swizzle
,
1010 /* Mark which channels we found unconditional writes for. */
1011 if (!scan_inst
->predicate
) {
1012 for (int i
= 0; i
< 4; i
++) {
1013 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1015 chans_needed
[i
] = false;
1021 if (chans_remaining
== 0)
1025 /* We don't handle flow control here. Most computation of values
1026 * that could be coalesced happens just before their use.
1028 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1029 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1030 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1031 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1035 /* You can't read from an MRF, so if someone else reads our MRF's
1036 * source GRF that we wanted to rewrite, that stops us. If it's a
1037 * GRF we're trying to coalesce to, we don't actually handle
1038 * rewriting sources so bail in that case as well.
1040 bool interfered
= false;
1041 for (int i
= 0; i
< 3; i
++) {
1042 if (scan_inst
->src
[i
].file
== GRF
&&
1043 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1044 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1051 /* If somebody else writes our destination here, we can't coalesce
1054 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1055 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1059 /* Check for reads of the register we're trying to coalesce into. We
1060 * can't go rewriting instructions above that to put some other value
1061 * in the register instead.
1063 if (to_mrf
&& scan_inst
->mlen
> 0) {
1064 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1065 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1069 for (int i
= 0; i
< 3; i
++) {
1070 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1071 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1072 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1081 if (chans_remaining
== 0) {
1082 /* If we've made it here, we have an MOV we want to coalesce out, and
1083 * a scan_inst pointing to the earliest instruction involved in
1084 * computing the value. Now go rewrite the instruction stream
1088 while (scan_inst
!= inst
) {
1089 if (scan_inst
->dst
.file
== GRF
&&
1090 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1091 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1092 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1093 inst
->src
[0].swizzle
);
1094 scan_inst
->dst
.file
= inst
->dst
.file
;
1095 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1096 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1097 scan_inst
->saturate
|= inst
->saturate
;
1099 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1107 invalidate_live_intervals();
1113 * Splits virtual GRFs requesting more than one contiguous physical register.
1115 * We initially create large virtual GRFs for temporary structures, arrays,
1116 * and matrices, so that the dereference visitor functions can add reg_offsets
1117 * to work their way down to the actual member being accessed. But when it
1118 * comes to optimization, we'd like to treat each register as individual
1119 * storage if possible.
1121 * So far, the only thing that might prevent splitting is a send message from
1125 vec4_visitor::split_virtual_grfs()
1127 int num_vars
= this->virtual_grf_count
;
1128 int new_virtual_grf
[num_vars
];
1129 bool split_grf
[num_vars
];
1131 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1133 /* Try to split anything > 0 sized. */
1134 for (int i
= 0; i
< num_vars
; i
++) {
1135 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1138 /* Check that the instructions are compatible with the registers we're trying
1141 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1142 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1145 if (inst
->is_send_from_grf()) {
1146 for (int i
= 0; i
< 3; i
++) {
1147 if (inst
->src
[i
].file
== GRF
) {
1148 split_grf
[inst
->src
[i
].reg
] = false;
1154 /* Allocate new space for split regs. Note that the virtual
1155 * numbers will be contiguous.
1157 for (int i
= 0; i
< num_vars
; i
++) {
1161 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1162 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1163 int reg
= virtual_grf_alloc(1);
1164 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1167 this->virtual_grf_sizes
[i
] = 1;
1170 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1171 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1172 inst
->dst
.reg_offset
!= 0) {
1173 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1174 inst
->dst
.reg_offset
- 1);
1175 inst
->dst
.reg_offset
= 0;
1177 for (int i
= 0; i
< 3; i
++) {
1178 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1179 inst
->src
[i
].reg_offset
!= 0) {
1180 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1181 inst
->src
[i
].reg_offset
- 1);
1182 inst
->src
[i
].reg_offset
= 0;
1186 invalidate_live_intervals();
1190 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1192 dump_instruction(be_inst
, stderr
);
1196 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1198 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1200 if (inst
->predicate
) {
1201 fprintf(file
, "(%cf0) ",
1202 inst
->predicate_inverse
? '-' : '+');
1205 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1206 if (inst
->conditional_mod
) {
1207 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1211 switch (inst
->dst
.file
) {
1213 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1216 fprintf(file
, "m%d", inst
->dst
.reg
);
1219 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1220 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1222 fprintf(file
, "null");
1224 case BRW_ARF_ADDRESS
:
1225 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1227 case BRW_ARF_ACCUMULATOR
:
1228 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1231 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1232 inst
->dst
.fixed_hw_reg
.subnr
);
1235 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1236 inst
->dst
.fixed_hw_reg
.subnr
);
1240 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1242 if (inst
->dst
.fixed_hw_reg
.subnr
)
1243 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1246 fprintf(file
, "(null)");
1249 fprintf(file
, "???");
1252 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1254 if (inst
->dst
.writemask
& 1)
1256 if (inst
->dst
.writemask
& 2)
1258 if (inst
->dst
.writemask
& 4)
1260 if (inst
->dst
.writemask
& 8)
1263 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
1265 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1266 if (inst
->src
[i
].negate
)
1268 if (inst
->src
[i
].abs
)
1270 switch (inst
->src
[i
].file
) {
1272 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1275 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1278 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1281 switch (inst
->src
[i
].type
) {
1282 case BRW_REGISTER_TYPE_F
:
1283 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1285 case BRW_REGISTER_TYPE_D
:
1286 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1288 case BRW_REGISTER_TYPE_UD
:
1289 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1292 fprintf(file
, "???");
1297 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1299 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1301 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1302 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1304 fprintf(file
, "null");
1306 case BRW_ARF_ADDRESS
:
1307 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1309 case BRW_ARF_ACCUMULATOR
:
1310 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1313 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1314 inst
->src
[i
].fixed_hw_reg
.subnr
);
1317 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1318 inst
->src
[i
].fixed_hw_reg
.subnr
);
1322 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1324 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1325 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1326 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1330 fprintf(file
, "(null)");
1333 fprintf(file
, "???");
1337 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1338 if (inst
->src
[i
].reg_offset
!= 0 &&
1339 inst
->src
[i
].file
== GRF
&&
1340 virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1341 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1343 if (inst
->src
[i
].file
!= IMM
) {
1344 static const char *chans
[4] = {"x", "y", "z", "w"};
1346 for (int c
= 0; c
< 4; c
++) {
1347 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1351 if (inst
->src
[i
].abs
)
1354 if (inst
->src
[i
].file
!= IMM
) {
1355 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1358 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1359 fprintf(file
, ", ");
1362 fprintf(file
, "\n");
1366 static inline struct brw_reg
1367 attribute_to_hw_reg(int attr
, bool interleaved
)
1370 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1372 return brw_vec8_grf(attr
, 0);
1377 * Replace each register of type ATTR in this->instructions with a reference
1378 * to a fixed HW register.
1380 * If interleaved is true, then each attribute takes up half a register, with
1381 * register N containing attribute 2*N in its first half and attribute 2*N+1
1382 * in its second half (this corresponds to the payload setup used by geometry
1383 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1384 * false, then each attribute takes up a whole register, with register N
1385 * containing attribute N (this corresponds to the payload setup used by
1386 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1389 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1392 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1393 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1394 if (inst
->dst
.file
== ATTR
) {
1395 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1397 /* All attributes used in the shader need to have been assigned a
1398 * hardware register by the caller
1402 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1403 reg
.type
= inst
->dst
.type
;
1404 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1406 inst
->dst
.file
= HW_REG
;
1407 inst
->dst
.fixed_hw_reg
= reg
;
1410 for (int i
= 0; i
< 3; i
++) {
1411 if (inst
->src
[i
].file
!= ATTR
)
1414 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1416 /* All attributes used in the shader need to have been assigned a
1417 * hardware register by the caller
1421 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1422 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1423 reg
.type
= inst
->src
[i
].type
;
1424 if (inst
->src
[i
].abs
)
1426 if (inst
->src
[i
].negate
)
1429 inst
->src
[i
].file
= HW_REG
;
1430 inst
->src
[i
].fixed_hw_reg
= reg
;
1436 vec4_vs_visitor::setup_attributes(int payload_reg
)
1439 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1440 memset(attribute_map
, 0, sizeof(attribute_map
));
1443 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1444 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1445 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1450 /* VertexID is stored by the VF as the last vertex element, but we
1451 * don't represent it with a flag in inputs_read, so we call it
1454 if (vs_prog_data
->uses_vertexid
) {
1455 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1459 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1461 /* The BSpec says we always have to read at least one thing from
1462 * the VF, and it appears that the hardware wedges otherwise.
1464 if (nr_attributes
== 0)
1467 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1469 unsigned vue_entries
=
1470 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1473 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1475 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1477 return payload_reg
+ nr_attributes
;
1481 vec4_visitor::setup_uniforms(int reg
)
1483 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1485 /* The pre-gen6 VS requires that some push constants get loaded no
1486 * matter what, or the GPU would hang.
1488 if (brw
->gen
< 6 && this->uniforms
== 0) {
1489 assert(this->uniforms
< this->uniform_array_size
);
1490 this->uniform_vector_size
[this->uniforms
] = 1;
1492 stage_prog_data
->param
=
1493 reralloc(NULL
, stage_prog_data
->param
, const float *, 4);
1494 for (unsigned int i
= 0; i
< 4; i
++) {
1495 unsigned int slot
= this->uniforms
* 4 + i
;
1496 static float zero
= 0.0;
1497 stage_prog_data
->param
[slot
] = &zero
;
1503 reg
+= ALIGN(uniforms
, 2) / 2;
1506 stage_prog_data
->nr_params
= this->uniforms
* 4;
1508 prog_data
->curb_read_length
= reg
- prog_data
->base
.dispatch_grf_start_reg
;
1514 vec4_vs_visitor::setup_payload(void)
1518 /* The payload always contains important data in g0, which contains
1519 * the URB handles that are passed on to the URB write at the end
1520 * of the thread. So, we always start push constants at g1.
1524 reg
= setup_uniforms(reg
);
1526 reg
= setup_attributes(reg
);
1528 this->first_non_payload_grf
= reg
;
1532 vec4_visitor::get_timestamp()
1534 assert(brw
->gen
>= 7);
1536 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1539 BRW_REGISTER_TYPE_UD
,
1540 BRW_VERTICAL_STRIDE_0
,
1542 BRW_HORIZONTAL_STRIDE_4
,
1546 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1548 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1549 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1550 * even if it's not enabled in the dispatch.
1552 mov
->force_writemask_all
= true;
1554 return src_reg(dst
);
1558 vec4_visitor::emit_shader_time_begin()
1560 current_annotation
= "shader time start";
1561 shader_start_time
= get_timestamp();
1565 vec4_visitor::emit_shader_time_end()
1567 current_annotation
= "shader time end";
1568 src_reg shader_end_time
= get_timestamp();
1571 /* Check that there weren't any timestamp reset events (assuming these
1572 * were the only two timestamp reads that happened).
1574 src_reg reset_end
= shader_end_time
;
1575 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1576 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1577 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1579 emit(IF(BRW_PREDICATE_NORMAL
));
1581 /* Take the current timestamp and get the delta. */
1582 shader_start_time
.negate
= true;
1583 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1584 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1586 /* If there were no instructions between the two timestamp gets, the diff
1587 * is 2 cycles. Remove that overhead, so I can forget about that when
1588 * trying to determine the time taken for single instructions.
1590 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1592 emit_shader_time_write(st_base
, src_reg(diff
));
1593 emit_shader_time_write(st_written
, src_reg(1u));
1594 emit(BRW_OPCODE_ELSE
);
1595 emit_shader_time_write(st_reset
, src_reg(1u));
1596 emit(BRW_OPCODE_ENDIF
);
1600 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1603 int shader_time_index
=
1604 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1607 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1609 dst_reg offset
= dst
;
1613 offset
.type
= BRW_REGISTER_TYPE_UD
;
1614 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1616 time
.type
= BRW_REGISTER_TYPE_UD
;
1617 emit(MOV(time
, src_reg(value
)));
1619 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1625 sanity_param_count
= prog
->Parameters
->NumParameters
;
1627 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1628 emit_shader_time_begin();
1630 assign_common_binding_table_offsets(0);
1634 /* Generate VS IR for main(). (the visitor only descends into
1635 * functions called "main").
1638 visit_instructions(shader
->base
.ir
);
1640 emit_program_code();
1644 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1645 setup_uniform_clipplane_values();
1649 /* Before any optimization, push array accesses out to scratch
1650 * space where we need them to be. This pass may allocate new
1651 * virtual GRFs, so we want to do it early. It also makes sure
1652 * that we have reladdr computations available for CSE, since we'll
1653 * often do repeated subexpressions for those.
1656 move_grf_array_access_to_scratch();
1657 move_uniform_array_access_to_pull_constants();
1659 /* The ARB_vertex_program frontend emits pull constant loads directly
1660 * rather than using reladdr, so we don't need to walk through all the
1661 * instructions looking for things to move. There isn't anything.
1663 * We do still need to split things to vec4 size.
1665 split_uniform_registers();
1667 pack_uniform_registers();
1668 move_push_constants_to_pull_constants();
1669 split_virtual_grfs();
1671 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1673 #define OPT(pass, args...) do { \
1675 bool this_progress = pass(args); \
1677 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1678 char filename[64]; \
1679 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1680 stage_name, shader_prog->Name, iteration, pass_num); \
1682 backend_visitor::dump_instructions(filename); \
1685 progress = progress || this_progress; \
1689 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1691 snprintf(filename
, 64, "%s-%04d-00-start",
1692 stage_name
, shader_prog
->Name
);
1694 backend_visitor::dump_instructions(filename
);
1704 OPT(dead_code_eliminate
);
1705 OPT(dead_control_flow_eliminate
, this);
1706 OPT(opt_copy_propagation
);
1709 OPT(opt_register_coalesce
);
1719 /* Debug of register spilling: Go spill everything. */
1720 const int grf_count
= virtual_grf_count
;
1721 float spill_costs
[virtual_grf_count
];
1722 bool no_spill
[virtual_grf_count
];
1723 evaluate_spill_costs(spill_costs
, no_spill
);
1724 for (int i
= 0; i
< grf_count
; i
++) {
1731 while (!reg_allocate()) {
1736 opt_schedule_instructions();
1738 opt_set_dependency_control();
1740 /* If any state parameters were appended, then ParameterValues could have
1741 * been realloced, in which case the driver uniform storage set up by
1742 * _mesa_associate_uniform_storage() would point to freed memory. Make
1743 * sure that didn't happen.
1745 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1750 } /* namespace brw */
1755 * Compile a vertex shader.
1757 * Returns the final assembly and the program's size.
1760 brw_vs_emit(struct brw_context
*brw
,
1761 struct gl_shader_program
*prog
,
1762 struct brw_vs_compile
*c
,
1763 struct brw_vs_prog_data
*prog_data
,
1765 unsigned *final_assembly_size
)
1767 bool start_busy
= false;
1768 double start_time
= 0;
1770 if (unlikely(brw
->perf_debug
)) {
1771 start_busy
= (brw
->batch
.last_bo
&&
1772 drm_intel_bo_busy(brw
->batch
.last_bo
));
1773 start_time
= get_time();
1776 struct brw_shader
*shader
= NULL
;
1778 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1780 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1781 brw_dump_ir(brw
, "vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1783 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1786 prog
->LinkStatus
= false;
1787 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1790 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1796 const unsigned *assembly
= NULL
;
1797 if (brw
->gen
>= 8) {
1798 gen8_vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1799 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1800 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1802 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1803 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1804 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1807 if (unlikely(brw
->perf_debug
) && shader
) {
1808 if (shader
->compiled_once
) {
1809 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1811 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1812 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1813 (get_time() - start_time
) * 1000);
1815 shader
->compiled_once
= true;
1823 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1824 struct brw_vec4_prog_key
*key
,
1825 GLuint id
, struct gl_program
*prog
)
1827 key
->program_string_id
= id
;
1828 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1830 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1831 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1832 if (prog
->ShadowSamplers
& (1 << i
)) {
1833 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1834 key
->tex
.swizzles
[i
] =
1835 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1837 /* Color sampler: assume no swizzling. */
1838 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;