2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_print_visitor.h"
28 #include "main/macros.h"
29 #include "main/shaderobj.h"
30 #include "program/prog_print.h"
31 #include "program/prog_parameter.h"
34 #define MAX_INSTRUCTION (1 << 30)
41 * Common helper for constructing swizzles. When only a subset of
42 * channels of a vec4 are used, we don't want to reference the other
43 * channels, as that will tell optimization passes that those other
47 swizzle_for_size(int size
)
49 static const unsigned size_swizzles
[4] = {
50 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
51 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
56 assert((size
>= 1) && (size
<= 4));
57 return size_swizzles
[size
- 1];
63 memset(this, 0, sizeof(*this));
65 this->file
= BAD_FILE
;
68 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
74 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
75 this->swizzle
= swizzle_for_size(type
->vector_elements
);
77 this->swizzle
= SWIZZLE_XYZW
;
80 /** Generic unset register constructor. */
86 src_reg::src_reg(float f
)
91 this->type
= BRW_REGISTER_TYPE_F
;
95 src_reg::src_reg(uint32_t u
)
100 this->type
= BRW_REGISTER_TYPE_UD
;
104 src_reg::src_reg(int32_t i
)
109 this->type
= BRW_REGISTER_TYPE_D
;
113 src_reg::src_reg(dst_reg reg
)
117 this->file
= reg
.file
;
119 this->reg_offset
= reg
.reg_offset
;
120 this->type
= reg
.type
;
121 this->reladdr
= reg
.reladdr
;
122 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
128 for (int i
= 0; i
< 4; i
++) {
129 if (!(reg
.writemask
& (1 << i
)))
132 swizzles
[next_chan
++] = last
= i
;
135 for (; next_chan
< 4; next_chan
++) {
136 swizzles
[next_chan
] = last
;
139 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
140 swizzles
[2], swizzles
[3]);
144 vec4_instruction::is_tex()
146 return (opcode
== SHADER_OPCODE_TEX
||
147 opcode
== SHADER_OPCODE_TXD
||
148 opcode
== SHADER_OPCODE_TXF
||
149 opcode
== SHADER_OPCODE_TXF_MS
||
150 opcode
== SHADER_OPCODE_TXL
||
151 opcode
== SHADER_OPCODE_TXS
);
157 memset(this, 0, sizeof(*this));
158 this->file
= BAD_FILE
;
159 this->writemask
= WRITEMASK_XYZW
;
167 dst_reg::dst_reg(register_file file
, int reg
)
175 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
182 this->type
= brw_type_for_base_type(type
);
183 this->writemask
= writemask
;
186 dst_reg::dst_reg(struct brw_reg reg
)
191 this->fixed_hw_reg
= reg
;
194 dst_reg::dst_reg(src_reg reg
)
198 this->file
= reg
.file
;
200 this->reg_offset
= reg
.reg_offset
;
201 this->type
= reg
.type
;
202 this->writemask
= WRITEMASK_XYZW
;
203 this->reladdr
= reg
.reladdr
;
204 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
208 vec4_instruction::is_math()
210 return (opcode
== SHADER_OPCODE_RCP
||
211 opcode
== SHADER_OPCODE_RSQ
||
212 opcode
== SHADER_OPCODE_SQRT
||
213 opcode
== SHADER_OPCODE_EXP2
||
214 opcode
== SHADER_OPCODE_LOG2
||
215 opcode
== SHADER_OPCODE_SIN
||
216 opcode
== SHADER_OPCODE_COS
||
217 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
218 opcode
== SHADER_OPCODE_INT_REMAINDER
||
219 opcode
== SHADER_OPCODE_POW
);
222 * Returns how many MRFs an opcode will write over.
224 * Note that this is not the 0 or 1 implied writes in an actual gen
225 * instruction -- the generate_* functions generate additional MOVs
229 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
234 switch (inst
->opcode
) {
235 case SHADER_OPCODE_RCP
:
236 case SHADER_OPCODE_RSQ
:
237 case SHADER_OPCODE_SQRT
:
238 case SHADER_OPCODE_EXP2
:
239 case SHADER_OPCODE_LOG2
:
240 case SHADER_OPCODE_SIN
:
241 case SHADER_OPCODE_COS
:
243 case SHADER_OPCODE_POW
:
245 case VS_OPCODE_URB_WRITE
:
247 case VS_OPCODE_PULL_CONSTANT_LOAD
:
249 case VS_OPCODE_SCRATCH_READ
:
251 case VS_OPCODE_SCRATCH_WRITE
:
253 case SHADER_OPCODE_SHADER_TIME_ADD
:
256 assert(!"not reached");
262 src_reg::equals(src_reg
*r
)
264 return (file
== r
->file
&&
266 reg_offset
== r
->reg_offset
&&
268 negate
== r
->negate
&&
270 swizzle
== r
->swizzle
&&
271 !reladdr
&& !r
->reladdr
&&
272 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
273 sizeof(fixed_hw_reg
)) == 0 &&
278 * Must be called after calculate_live_intervales() to remove unused
279 * writes to registers -- register allocation will fail otherwise
280 * because something deffed but not used won't be considered to
281 * interfere with other regs.
284 vec4_visitor::dead_code_eliminate()
286 bool progress
= false;
289 calculate_live_intervals();
291 foreach_list_safe(node
, &this->instructions
) {
292 vec4_instruction
*inst
= (vec4_instruction
*)node
;
294 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
303 live_intervals_valid
= false;
309 vec4_visitor::split_uniform_registers()
311 /* Prior to this, uniforms have been in an array sized according to
312 * the number of vector uniforms present, sparsely filled (so an
313 * aggregate results in reg indices being skipped over). Now we're
314 * going to cut those aggregates up so each .reg index is one
315 * vector. The goal is to make elimination of unused uniform
316 * components easier later.
318 foreach_list(node
, &this->instructions
) {
319 vec4_instruction
*inst
= (vec4_instruction
*)node
;
321 for (int i
= 0 ; i
< 3; i
++) {
322 if (inst
->src
[i
].file
!= UNIFORM
)
325 assert(!inst
->src
[i
].reladdr
);
327 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
328 inst
->src
[i
].reg_offset
= 0;
332 /* Update that everything is now vector-sized. */
333 for (int i
= 0; i
< this->uniforms
; i
++) {
334 this->uniform_size
[i
] = 1;
339 vec4_visitor::pack_uniform_registers()
341 bool uniform_used
[this->uniforms
];
342 int new_loc
[this->uniforms
];
343 int new_chan
[this->uniforms
];
345 memset(uniform_used
, 0, sizeof(uniform_used
));
346 memset(new_loc
, 0, sizeof(new_loc
));
347 memset(new_chan
, 0, sizeof(new_chan
));
349 /* Find which uniform vectors are actually used by the program. We
350 * expect unused vector elements when we've moved array access out
351 * to pull constants, and from some GLSL code generators like wine.
353 foreach_list(node
, &this->instructions
) {
354 vec4_instruction
*inst
= (vec4_instruction
*)node
;
356 for (int i
= 0 ; i
< 3; i
++) {
357 if (inst
->src
[i
].file
!= UNIFORM
)
360 uniform_used
[inst
->src
[i
].reg
] = true;
364 int new_uniform_count
= 0;
366 /* Now, figure out a packing of the live uniform vectors into our
369 for (int src
= 0; src
< uniforms
; src
++) {
370 int size
= this->uniform_vector_size
[src
];
372 if (!uniform_used
[src
]) {
373 this->uniform_vector_size
[src
] = 0;
378 /* Find the lowest place we can slot this uniform in. */
379 for (dst
= 0; dst
< src
; dst
++) {
380 if (this->uniform_vector_size
[dst
] + size
<= 4)
389 new_chan
[src
] = this->uniform_vector_size
[dst
];
391 /* Move the references to the data */
392 for (int j
= 0; j
< size
; j
++) {
393 c
->prog_data
.param
[dst
* 4 + new_chan
[src
] + j
] =
394 c
->prog_data
.param
[src
* 4 + j
];
397 this->uniform_vector_size
[dst
] += size
;
398 this->uniform_vector_size
[src
] = 0;
401 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
404 this->uniforms
= new_uniform_count
;
406 /* Now, update the instructions for our repacked uniforms. */
407 foreach_list(node
, &this->instructions
) {
408 vec4_instruction
*inst
= (vec4_instruction
*)node
;
410 for (int i
= 0 ; i
< 3; i
++) {
411 int src
= inst
->src
[i
].reg
;
413 if (inst
->src
[i
].file
!= UNIFORM
)
416 inst
->src
[i
].reg
= new_loc
[src
];
418 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
419 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
420 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
421 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
422 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
428 src_reg::is_zero() const
433 if (type
== BRW_REGISTER_TYPE_F
) {
441 src_reg::is_one() const
446 if (type
== BRW_REGISTER_TYPE_F
) {
454 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
456 * While GLSL IR also performs this optimization, we end up with it in
457 * our instruction stream for a couple of reasons. One is that we
458 * sometimes generate silly instructions, for example in array access
459 * where we'll generate "ADD offset, index, base" even if base is 0.
460 * The other is that GLSL IR's constant propagation doesn't track the
461 * components of aggregates, so some VS patterns (initialize matrix to
462 * 0, accumulate in vertex blending factors) end up breaking down to
463 * instructions involving 0.
466 vec4_visitor::opt_algebraic()
468 bool progress
= false;
470 foreach_list(node
, &this->instructions
) {
471 vec4_instruction
*inst
= (vec4_instruction
*)node
;
473 switch (inst
->opcode
) {
475 if (inst
->src
[1].is_zero()) {
476 inst
->opcode
= BRW_OPCODE_MOV
;
477 inst
->src
[1] = src_reg();
483 if (inst
->src
[1].is_zero()) {
484 inst
->opcode
= BRW_OPCODE_MOV
;
485 switch (inst
->src
[0].type
) {
486 case BRW_REGISTER_TYPE_F
:
487 inst
->src
[0] = src_reg(0.0f
);
489 case BRW_REGISTER_TYPE_D
:
490 inst
->src
[0] = src_reg(0);
492 case BRW_REGISTER_TYPE_UD
:
493 inst
->src
[0] = src_reg(0u);
496 assert(!"not reached");
497 inst
->src
[0] = src_reg(0.0f
);
500 inst
->src
[1] = src_reg();
502 } else if (inst
->src
[1].is_one()) {
503 inst
->opcode
= BRW_OPCODE_MOV
;
504 inst
->src
[1] = src_reg();
514 this->live_intervals_valid
= false;
520 * Only a limited number of hardware registers may be used for push
521 * constants, so this turns access to the overflowed constants into
525 vec4_visitor::move_push_constants_to_pull_constants()
527 int pull_constant_loc
[this->uniforms
];
529 /* Only allow 32 registers (256 uniform components) as push constants,
530 * which is the limit on gen6.
532 int max_uniform_components
= 32 * 8;
533 if (this->uniforms
* 4 <= max_uniform_components
)
536 /* Make some sort of choice as to which uniforms get sent to pull
537 * constants. We could potentially do something clever here like
538 * look for the most infrequently used uniform vec4s, but leave
541 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
542 pull_constant_loc
[i
/ 4] = -1;
544 if (i
>= max_uniform_components
) {
545 const float **values
= &prog_data
->param
[i
];
547 /* Try to find an existing copy of this uniform in the pull
548 * constants if it was part of an array access already.
550 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
553 for (matches
= 0; matches
< 4; matches
++) {
554 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
559 pull_constant_loc
[i
/ 4] = j
/ 4;
564 if (pull_constant_loc
[i
/ 4] == -1) {
565 assert(prog_data
->nr_pull_params
% 4 == 0);
566 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
568 for (int j
= 0; j
< 4; j
++) {
569 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
575 /* Now actually rewrite usage of the things we've moved to pull
578 foreach_list_safe(node
, &this->instructions
) {
579 vec4_instruction
*inst
= (vec4_instruction
*)node
;
581 for (int i
= 0 ; i
< 3; i
++) {
582 if (inst
->src
[i
].file
!= UNIFORM
||
583 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
586 int uniform
= inst
->src
[i
].reg
;
588 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
590 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
591 pull_constant_loc
[uniform
]);
593 inst
->src
[i
].file
= temp
.file
;
594 inst
->src
[i
].reg
= temp
.reg
;
595 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
596 inst
->src
[i
].reladdr
= NULL
;
600 /* Repack push constants to remove the now-unused ones. */
601 pack_uniform_registers();
605 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
609 /* If this instruction sets anything not referenced by swizzle, then we'd
610 * totally break it when we reswizzle.
612 if (dst
.writemask
& ~swizzle_mask
)
621 /* Check if there happens to be no reswizzling required. */
622 for (int c
= 0; c
< 4; c
++) {
623 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
624 /* Skip components of the swizzle not used by the dst. */
625 if (!(dst_writemask
& (1 << c
)))
628 /* We don't do the reswizzling yet, so just sanity check that we
639 * For any channels in the swizzle's source that were populated by this
640 * instruction, rewrite the instruction to put the appropriate result directly
643 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
646 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
648 int new_writemask
= 0;
654 for (int c
= 0; c
< 4; c
++) {
655 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
656 /* Skip components of the swizzle not used by the dst. */
657 if (!(dst_writemask
& (1 << c
)))
659 /* If we were populating this component, then populate the
660 * corresponding channel of the new dst.
662 if (dst
.writemask
& bit
)
663 new_writemask
|= (1 << c
);
665 dst
.writemask
= new_writemask
;
668 for (int c
= 0; c
< 4; c
++) {
669 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
670 /* Skip components of the swizzle not used by the dst. */
671 if (!(dst_writemask
& (1 << c
)))
674 /* We don't do the reswizzling yet, so just sanity check that we
677 assert(bit
== (1 << c
));
684 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
685 * just written and then MOVed into another reg and making the original write
686 * of the GRF write directly to the final destination instead.
689 vec4_visitor::opt_register_coalesce()
691 bool progress
= false;
694 calculate_live_intervals();
696 foreach_list_safe(node
, &this->instructions
) {
697 vec4_instruction
*inst
= (vec4_instruction
*)node
;
702 if (inst
->opcode
!= BRW_OPCODE_MOV
||
703 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
705 inst
->src
[0].file
!= GRF
||
706 inst
->dst
.type
!= inst
->src
[0].type
||
707 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
710 bool to_mrf
= (inst
->dst
.file
== MRF
);
712 /* Can't coalesce this GRF if someone else was going to
715 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
718 /* We need to check interference with the final destination between this
719 * instruction and the earliest instruction involved in writing the GRF
720 * we're eliminating. To do that, keep track of which of our source
721 * channels we've seen initialized.
723 bool chans_needed
[4] = {false, false, false, false};
724 int chans_remaining
= 0;
725 int swizzle_mask
= 0;
726 for (int i
= 0; i
< 4; i
++) {
727 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
729 if (!(inst
->dst
.writemask
& (1 << i
)))
732 swizzle_mask
|= (1 << chan
);
734 if (!chans_needed
[chan
]) {
735 chans_needed
[chan
] = true;
740 /* Now walk up the instruction stream trying to see if we can rewrite
741 * everything writing to the temporary to write into the destination
744 vec4_instruction
*scan_inst
;
745 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
746 scan_inst
->prev
!= NULL
;
747 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
748 if (scan_inst
->dst
.file
== GRF
&&
749 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
750 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
751 /* Found something writing to the reg we want to coalesce away. */
753 /* SEND instructions can't have MRF as a destination. */
757 if (intel
->gen
== 6) {
758 /* gen6 math instructions must have the destination be
759 * GRF, so no compute-to-MRF for them.
761 if (scan_inst
->is_math()) {
767 /* If we can't handle the swizzle, bail. */
768 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
769 inst
->src
[0].swizzle
,
774 /* Mark which channels we found unconditional writes for. */
775 if (!scan_inst
->predicate
) {
776 for (int i
= 0; i
< 4; i
++) {
777 if (scan_inst
->dst
.writemask
& (1 << i
) &&
779 chans_needed
[i
] = false;
785 if (chans_remaining
== 0)
789 /* We don't handle flow control here. Most computation of values
790 * that could be coalesced happens just before their use.
792 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
793 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
794 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
795 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
799 /* You can't read from an MRF, so if someone else reads our MRF's
800 * source GRF that we wanted to rewrite, that stops us. If it's a
801 * GRF we're trying to coalesce to, we don't actually handle
802 * rewriting sources so bail in that case as well.
804 bool interfered
= false;
805 for (int i
= 0; i
< 3; i
++) {
806 if (scan_inst
->src
[i
].file
== GRF
&&
807 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
808 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
815 /* If somebody else writes our destination here, we can't coalesce
818 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
819 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
823 /* Check for reads of the register we're trying to coalesce into. We
824 * can't go rewriting instructions above that to put some other value
825 * in the register instead.
827 if (to_mrf
&& scan_inst
->mlen
> 0) {
828 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
829 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
833 for (int i
= 0; i
< 3; i
++) {
834 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
835 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
836 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
845 if (chans_remaining
== 0) {
846 /* If we've made it here, we have an MOV we want to coalesce out, and
847 * a scan_inst pointing to the earliest instruction involved in
848 * computing the value. Now go rewrite the instruction stream
852 while (scan_inst
!= inst
) {
853 if (scan_inst
->dst
.file
== GRF
&&
854 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
855 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
856 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
857 inst
->src
[0].swizzle
);
858 scan_inst
->dst
.file
= inst
->dst
.file
;
859 scan_inst
->dst
.reg
= inst
->dst
.reg
;
860 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
861 scan_inst
->saturate
|= inst
->saturate
;
863 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
871 live_intervals_valid
= false;
877 * Splits virtual GRFs requesting more than one contiguous physical register.
879 * We initially create large virtual GRFs for temporary structures, arrays,
880 * and matrices, so that the dereference visitor functions can add reg_offsets
881 * to work their way down to the actual member being accessed.
883 * Unlike in the FS visitor, though, we have no SEND messages that return more
884 * than 1 register. We also don't do any array access in register space,
885 * which would have required contiguous physical registers. Thus, all those
886 * large virtual GRFs can be split up into independent single-register virtual
887 * GRFs, making allocation and optimization easier.
890 vec4_visitor::split_virtual_grfs()
892 int num_vars
= this->virtual_grf_count
;
893 int new_virtual_grf
[num_vars
];
895 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
897 /* Allocate new space for split regs. Note that the virtual
898 * numbers will be contiguous.
900 for (int i
= 0; i
< num_vars
; i
++) {
901 if (this->virtual_grf_sizes
[i
] == 1)
904 new_virtual_grf
[i
] = virtual_grf_alloc(1);
905 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
906 int reg
= virtual_grf_alloc(1);
907 assert(reg
== new_virtual_grf
[i
] + j
- 1);
910 this->virtual_grf_sizes
[i
] = 1;
913 foreach_list(node
, &this->instructions
) {
914 vec4_instruction
*inst
= (vec4_instruction
*)node
;
916 if (inst
->dst
.file
== GRF
&&
917 new_virtual_grf
[inst
->dst
.reg
] &&
918 inst
->dst
.reg_offset
!= 0) {
919 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
920 inst
->dst
.reg_offset
- 1);
921 inst
->dst
.reg_offset
= 0;
923 for (int i
= 0; i
< 3; i
++) {
924 if (inst
->src
[i
].file
== GRF
&&
925 new_virtual_grf
[inst
->src
[i
].reg
] &&
926 inst
->src
[i
].reg_offset
!= 0) {
927 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
928 inst
->src
[i
].reg_offset
- 1);
929 inst
->src
[i
].reg_offset
= 0;
933 this->live_intervals_valid
= false;
937 vec4_visitor::dump_instruction(vec4_instruction
*inst
)
939 if (inst
->opcode
< ARRAY_SIZE(opcode_descs
) &&
940 opcode_descs
[inst
->opcode
].name
) {
941 printf("%s ", opcode_descs
[inst
->opcode
].name
);
943 printf("op%d ", inst
->opcode
);
946 switch (inst
->dst
.file
) {
948 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
951 printf("m%d", inst
->dst
.reg
);
960 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
962 if (inst
->dst
.writemask
& 1)
964 if (inst
->dst
.writemask
& 2)
966 if (inst
->dst
.writemask
& 4)
968 if (inst
->dst
.writemask
& 8)
973 for (int i
= 0; i
< 3; i
++) {
974 switch (inst
->src
[i
].file
) {
976 printf("vgrf%d", inst
->src
[i
].reg
);
979 printf("attr%d", inst
->src
[i
].reg
);
982 printf("u%d", inst
->src
[i
].reg
);
985 switch (inst
->src
[i
].type
) {
986 case BRW_REGISTER_TYPE_F
:
987 printf("%fF", inst
->src
[i
].imm
.f
);
989 case BRW_REGISTER_TYPE_D
:
990 printf("%dD", inst
->src
[i
].imm
.i
);
992 case BRW_REGISTER_TYPE_UD
:
993 printf("%uU", inst
->src
[i
].imm
.u
);
1008 if (inst
->src
[i
].reg_offset
)
1009 printf(".%d", inst
->src
[i
].reg_offset
);
1011 static const char *chans
[4] = {"x", "y", "z", "w"};
1013 for (int c
= 0; c
< 4; c
++) {
1014 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1025 vec4_visitor::dump_instructions()
1028 foreach_list_safe(node
, &this->instructions
) {
1029 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1030 printf("%d: ", ip
++);
1031 dump_instruction(inst
);
1036 vec4_visitor::setup_attributes(int payload_reg
)
1039 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1042 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1043 if (prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1044 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1049 /* VertexID is stored by the VF as the last vertex element, but we
1050 * don't represent it with a flag in inputs_read, so we call it
1053 if (prog_data
->uses_vertexid
) {
1054 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1058 foreach_list(node
, &this->instructions
) {
1059 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1061 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1062 if (inst
->dst
.file
== ATTR
) {
1063 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1065 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1066 reg
.type
= inst
->dst
.type
;
1067 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1069 inst
->dst
.file
= HW_REG
;
1070 inst
->dst
.fixed_hw_reg
= reg
;
1073 for (int i
= 0; i
< 3; i
++) {
1074 if (inst
->src
[i
].file
!= ATTR
)
1077 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1079 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1080 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1081 reg
.type
= inst
->src
[i
].type
;
1082 if (inst
->src
[i
].abs
)
1084 if (inst
->src
[i
].negate
)
1087 inst
->src
[i
].file
= HW_REG
;
1088 inst
->src
[i
].fixed_hw_reg
= reg
;
1092 /* The BSpec says we always have to read at least one thing from
1093 * the VF, and it appears that the hardware wedges otherwise.
1095 if (nr_attributes
== 0)
1098 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1100 unsigned vue_entries
= MAX2(nr_attributes
, c
->prog_data
.vue_map
.num_slots
);
1102 if (intel
->gen
== 6)
1103 c
->prog_data
.urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1105 c
->prog_data
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1107 return payload_reg
+ nr_attributes
;
1111 vec4_visitor::setup_uniforms(int reg
)
1113 /* The pre-gen6 VS requires that some push constants get loaded no
1114 * matter what, or the GPU would hang.
1116 if (intel
->gen
< 6 && this->uniforms
== 0) {
1117 this->uniform_vector_size
[this->uniforms
] = 1;
1119 for (unsigned int i
= 0; i
< 4; i
++) {
1120 unsigned int slot
= this->uniforms
* 4 + i
;
1121 static float zero
= 0.0;
1122 c
->prog_data
.param
[slot
] = &zero
;
1128 reg
+= ALIGN(uniforms
, 2) / 2;
1131 c
->prog_data
.nr_params
= this->uniforms
* 4;
1133 c
->prog_data
.curb_read_length
= reg
- 1;
1139 vec4_visitor::setup_payload(void)
1143 /* The payload always contains important data in g0, which contains
1144 * the URB handles that are passed on to the URB write at the end
1145 * of the thread. So, we always start push constants at g1.
1149 reg
= setup_uniforms(reg
);
1151 reg
= setup_attributes(reg
);
1153 this->first_non_payload_grf
= reg
;
1157 vec4_visitor::get_timestamp()
1159 assert(intel
->gen
>= 7);
1161 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1164 BRW_REGISTER_TYPE_UD
,
1165 BRW_VERTICAL_STRIDE_0
,
1167 BRW_HORIZONTAL_STRIDE_4
,
1171 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1173 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1174 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1175 * even if it's not enabled in the dispatch.
1177 mov
->force_writemask_all
= true;
1179 return src_reg(dst
);
1183 vec4_visitor::emit_shader_time_begin()
1185 current_annotation
= "shader time start";
1186 shader_start_time
= get_timestamp();
1190 vec4_visitor::emit_shader_time_end()
1192 current_annotation
= "shader time end";
1193 src_reg shader_end_time
= get_timestamp();
1196 /* Check that there weren't any timestamp reset events (assuming these
1197 * were the only two timestamp reads that happened).
1199 src_reg reset_end
= shader_end_time
;
1200 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1201 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1202 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1204 emit(IF(BRW_PREDICATE_NORMAL
));
1206 /* Take the current timestamp and get the delta. */
1207 shader_start_time
.negate
= true;
1208 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1209 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1211 /* If there were no instructions between the two timestamp gets, the diff
1212 * is 2 cycles. Remove that overhead, so I can forget about that when
1213 * trying to determine the time taken for single instructions.
1215 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1217 emit_shader_time_write(ST_VS
, src_reg(diff
));
1218 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1219 emit(BRW_OPCODE_ELSE
);
1220 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1221 emit(BRW_OPCODE_ENDIF
);
1225 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1228 /* Choose an index in the buffer and set up tracking information for our
1231 int shader_time_index
= brw
->shader_time
.num_entries
++;
1232 assert(shader_time_index
<= brw
->shader_time
.max_entries
);
1233 brw
->shader_time
.types
[shader_time_index
] = type
;
1235 _mesa_reference_shader_program(ctx
,
1236 &brw
->shader_time
.programs
[shader_time_index
],
1242 dst_reg offset_mrf
= dst_reg(MRF
, base_mrf
);
1243 offset_mrf
.type
= BRW_REGISTER_TYPE_UD
;
1244 emit(MOV(offset_mrf
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1246 dst_reg time_mrf
= dst_reg(MRF
, base_mrf
+ 1);
1247 time_mrf
.type
= BRW_REGISTER_TYPE_UD
;
1248 emit(MOV(time_mrf
, src_reg(value
)));
1250 vec4_instruction
*inst
;
1251 inst
= emit(SHADER_OPCODE_SHADER_TIME_ADD
);
1252 inst
->base_mrf
= base_mrf
;
1259 sanity_param_count
= vp
->Base
.Parameters
->NumParameters
;
1261 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1262 emit_shader_time_begin();
1264 emit_attribute_fixups();
1266 /* Generate VS IR for main(). (the visitor only descends into
1267 * functions called "main").
1270 visit_instructions(shader
->ir
);
1272 emit_vertex_program_code();
1276 if (c
->key
.userclip_active
&& !c
->key
.uses_clip_distance
)
1277 setup_uniform_clipplane_values();
1279 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1280 emit_shader_time_end();
1284 /* Before any optimization, push array accesses out to scratch
1285 * space where we need them to be. This pass may allocate new
1286 * virtual GRFs, so we want to do it early. It also makes sure
1287 * that we have reladdr computations available for CSE, since we'll
1288 * often do repeated subexpressions for those.
1291 move_grf_array_access_to_scratch();
1292 move_uniform_array_access_to_pull_constants();
1294 /* The ARB_vertex_program frontend emits pull constant loads directly
1295 * rather than using reladdr, so we don't need to walk through all the
1296 * instructions looking for things to move. There isn't anything.
1298 * We do still need to split things to vec4 size.
1300 split_uniform_registers();
1302 pack_uniform_registers();
1303 move_push_constants_to_pull_constants();
1304 split_virtual_grfs();
1309 progress
= dead_code_eliminate() || progress
;
1310 progress
= opt_copy_propagation() || progress
;
1311 progress
= opt_algebraic() || progress
;
1312 progress
= opt_register_coalesce() || progress
;
1322 /* Debug of register spilling: Go spill everything. */
1323 const int grf_count
= virtual_grf_count
;
1324 float spill_costs
[virtual_grf_count
];
1325 bool no_spill
[virtual_grf_count
];
1326 evaluate_spill_costs(spill_costs
, no_spill
);
1327 for (int i
= 0; i
< grf_count
; i
++) {
1334 while (!reg_allocate()) {
1339 /* If any state parameters were appended, then ParameterValues could have
1340 * been realloced, in which case the driver uniform storage set up by
1341 * _mesa_associate_uniform_storage() would point to freed memory. Make
1342 * sure that didn't happen.
1344 assert(sanity_param_count
== vp
->Base
.Parameters
->NumParameters
);
1349 } /* namespace brw */
1354 * Compile a vertex shader.
1356 * Returns the final assembly and the program's size.
1359 brw_vs_emit(struct brw_context
*brw
,
1360 struct gl_shader_program
*prog
,
1361 struct brw_vs_compile
*c
,
1363 unsigned *final_assembly_size
)
1365 struct intel_context
*intel
= &brw
->intel
;
1366 bool start_busy
= false;
1367 float start_time
= 0;
1369 if (unlikely(intel
->perf_debug
)) {
1370 start_busy
= (intel
->batch
.last_bo
&&
1371 drm_intel_bo_busy(intel
->batch
.last_bo
));
1372 start_time
= get_time();
1375 struct brw_shader
*shader
= NULL
;
1377 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1379 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1381 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1382 _mesa_print_ir(shader
->ir
, NULL
);
1385 printf("ARB_vertex_program %d for native vertex shader\n",
1386 c
->vp
->program
.Base
.Id
);
1387 _mesa_print_program(&c
->vp
->program
.Base
);
1391 vec4_visitor
v(brw
, c
, prog
, shader
, mem_ctx
);
1393 prog
->LinkStatus
= false;
1394 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1398 vec4_generator
g(brw
, c
, prog
, mem_ctx
);
1399 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1400 final_assembly_size
);
1402 if (unlikely(intel
->perf_debug
) && shader
) {
1403 if (shader
->compiled_once
) {
1404 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1406 if (start_busy
&& !drm_intel_bo_busy(intel
->batch
.last_bo
)) {
1407 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1408 (get_time() - start_time
) * 1000);
1410 shader
->compiled_once
= true;