2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
31 #include "program/prog_parameter.h"
33 #define MAX_INSTRUCTION (1 << 30)
42 memset(this, 0, sizeof(*this));
44 this->file
= BAD_FILE
;
47 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
53 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
54 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
56 this->swizzle
= BRW_SWIZZLE_XYZW
;
58 this->type
= brw_type_for_base_type(type
);
61 /** Generic unset register constructor. */
67 src_reg::src_reg(struct ::brw_reg reg
) :
74 src_reg::src_reg(const dst_reg
®
) :
77 this->reladdr
= reg
.reladdr
;
78 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
84 memset(this, 0, sizeof(*this));
85 this->file
= BAD_FILE
;
86 this->writemask
= WRITEMASK_XYZW
;
94 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
102 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
109 this->type
= brw_type_for_base_type(type
);
110 this->writemask
= writemask
;
113 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
121 this->writemask
= writemask
;
124 dst_reg::dst_reg(struct ::brw_reg reg
) :
127 this->reg_offset
= 0;
128 this->reladdr
= NULL
;
131 dst_reg::dst_reg(const src_reg
®
) :
134 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
135 this->reladdr
= reg
.reladdr
;
139 dst_reg::equals(const dst_reg
&r
) const
141 return (this->backend_reg::equals(r
) &&
142 (reladdr
== r
.reladdr
||
143 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
147 vec4_instruction::is_send_from_grf()
150 case SHADER_OPCODE_SHADER_TIME_ADD
:
151 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
152 case SHADER_OPCODE_UNTYPED_ATOMIC
:
153 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
154 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
155 case SHADER_OPCODE_TYPED_ATOMIC
:
156 case SHADER_OPCODE_TYPED_SURFACE_READ
:
157 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
165 * Returns true if this instruction's sources and destinations cannot
166 * safely be the same register.
168 * In most cases, a register can be written over safely by the same
169 * instruction that is its last use. For a single instruction, the
170 * sources are dereferenced before writing of the destination starts
173 * However, there are a few cases where this can be problematic:
175 * - Virtual opcodes that translate to multiple instructions in the
176 * code generator: if src == dst and one instruction writes the
177 * destination before a later instruction reads the source, then
178 * src will have been clobbered.
180 * The register allocator uses this information to set up conflicts between
181 * GRF sources and the destination.
184 vec4_instruction::has_source_and_destination_hazard() const
187 /* Most opcodes in the vec4 world use MRFs. */
194 vec4_instruction::regs_read(unsigned arg
) const
196 if (src
[arg
].file
== BAD_FILE
)
200 case SHADER_OPCODE_SHADER_TIME_ADD
:
201 case SHADER_OPCODE_UNTYPED_ATOMIC
:
202 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
203 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
204 case SHADER_OPCODE_TYPED_ATOMIC
:
205 case SHADER_OPCODE_TYPED_SURFACE_READ
:
206 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
207 return arg
== 0 ? mlen
: 1;
209 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
210 return arg
== 1 ? mlen
: 1;
218 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
220 if (devinfo
->gen
== 6 && is_math())
223 if (is_send_from_grf())
226 if (!backend_instruction::can_do_source_mods())
233 vec4_instruction::can_change_types() const
235 return dst
.type
== src
[0].type
&&
236 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
237 (opcode
== BRW_OPCODE_MOV
||
238 (opcode
== BRW_OPCODE_SEL
&&
239 dst
.type
== src
[1].type
&&
240 predicate
!= BRW_PREDICATE_NONE
&&
241 !src
[1].abs
&& !src
[1].negate
));
245 * Returns how many MRFs an opcode will write over.
247 * Note that this is not the 0 or 1 implied writes in an actual gen
248 * instruction -- the generate_* functions generate additional MOVs
252 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
254 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
257 switch (inst
->opcode
) {
258 case SHADER_OPCODE_RCP
:
259 case SHADER_OPCODE_RSQ
:
260 case SHADER_OPCODE_SQRT
:
261 case SHADER_OPCODE_EXP2
:
262 case SHADER_OPCODE_LOG2
:
263 case SHADER_OPCODE_SIN
:
264 case SHADER_OPCODE_COS
:
266 case SHADER_OPCODE_INT_QUOTIENT
:
267 case SHADER_OPCODE_INT_REMAINDER
:
268 case SHADER_OPCODE_POW
:
270 case VS_OPCODE_URB_WRITE
:
272 case VS_OPCODE_PULL_CONSTANT_LOAD
:
274 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
276 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
278 case GS_OPCODE_URB_WRITE
:
279 case GS_OPCODE_URB_WRITE_ALLOCATE
:
280 case GS_OPCODE_THREAD_END
:
282 case GS_OPCODE_FF_SYNC
:
284 case SHADER_OPCODE_SHADER_TIME_ADD
:
286 case SHADER_OPCODE_TEX
:
287 case SHADER_OPCODE_TXL
:
288 case SHADER_OPCODE_TXD
:
289 case SHADER_OPCODE_TXF
:
290 case SHADER_OPCODE_TXF_CMS
:
291 case SHADER_OPCODE_TXF_CMS_W
:
292 case SHADER_OPCODE_TXF_MCS
:
293 case SHADER_OPCODE_TXS
:
294 case SHADER_OPCODE_TG4
:
295 case SHADER_OPCODE_TG4_OFFSET
:
296 case SHADER_OPCODE_SAMPLEINFO
:
297 case VS_OPCODE_GET_BUFFER_SIZE
:
298 return inst
->header_size
;
300 unreachable("not reached");
305 src_reg::equals(const src_reg
&r
) const
307 return (this->backend_reg::equals(r
) &&
308 !reladdr
&& !r
.reladdr
);
312 vec4_visitor::opt_vector_float()
314 bool progress
= false;
316 int last_reg
= -1, last_reg_offset
= -1;
317 enum brw_reg_file last_reg_file
= BAD_FILE
;
319 int remaining_channels
= 0;
322 vec4_instruction
*imm_inst
[4];
324 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
325 if (last_reg
!= inst
->dst
.nr
||
326 last_reg_offset
!= inst
->dst
.reg_offset
||
327 last_reg_file
!= inst
->dst
.file
) {
328 last_reg
= inst
->dst
.nr
;
329 last_reg_offset
= inst
->dst
.reg_offset
;
330 last_reg_file
= inst
->dst
.file
;
331 remaining_channels
= WRITEMASK_XYZW
;
336 if (inst
->opcode
!= BRW_OPCODE_MOV
||
337 inst
->dst
.writemask
== WRITEMASK_XYZW
||
338 inst
->src
[0].file
!= IMM
)
341 int vf
= brw_float_to_vf(inst
->src
[0].f
);
345 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
347 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
349 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
351 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
354 imm_inst
[inst_count
++] = inst
;
356 remaining_channels
&= ~inst
->dst
.writemask
;
357 if (remaining_channels
== 0) {
359 memcpy(&vf
, imm
, sizeof(vf
));
360 vec4_instruction
*mov
= MOV(inst
->dst
, brw_imm_vf(vf
));
361 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
362 mov
->dst
.writemask
= WRITEMASK_XYZW
;
363 inst
->insert_after(block
, mov
);
366 for (int i
= 0; i
< inst_count
; i
++) {
367 imm_inst
[i
]->remove(block
);
374 invalidate_live_intervals();
379 /* Replaces unused channels of a swizzle with channels that are used.
381 * For instance, this pass transforms
383 * mov vgrf4.yz, vgrf5.wxzy
387 * mov vgrf4.yz, vgrf5.xxzx
389 * This eliminates false uses of some channels, letting dead code elimination
390 * remove the instructions that wrote them.
393 vec4_visitor::opt_reduce_swizzle()
395 bool progress
= false;
397 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
398 if (inst
->dst
.file
== BAD_FILE
||
399 inst
->dst
.file
== ARF
||
400 inst
->dst
.file
== FIXED_GRF
||
401 inst
->is_send_from_grf())
406 /* Determine which channels of the sources are read. */
407 switch (inst
->opcode
) {
408 case VEC4_OPCODE_PACK_BYTES
:
410 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
411 * but all four of src1.
413 swizzle
= brw_swizzle_for_size(4);
416 swizzle
= brw_swizzle_for_size(3);
419 swizzle
= brw_swizzle_for_size(2);
422 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
426 /* Update sources' swizzles. */
427 for (int i
= 0; i
< 3; i
++) {
428 if (inst
->src
[i
].file
!= VGRF
&&
429 inst
->src
[i
].file
!= ATTR
&&
430 inst
->src
[i
].file
!= UNIFORM
)
433 const unsigned new_swizzle
=
434 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
435 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
436 inst
->src
[i
].swizzle
= new_swizzle
;
443 invalidate_live_intervals();
449 vec4_visitor::split_uniform_registers()
451 /* Prior to this, uniforms have been in an array sized according to
452 * the number of vector uniforms present, sparsely filled (so an
453 * aggregate results in reg indices being skipped over). Now we're
454 * going to cut those aggregates up so each .nr index is one
455 * vector. The goal is to make elimination of unused uniform
456 * components easier later.
458 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
459 for (int i
= 0 ; i
< 3; i
++) {
460 if (inst
->src
[i
].file
!= UNIFORM
)
463 assert(!inst
->src
[i
].reladdr
);
465 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
466 inst
->src
[i
].reg_offset
= 0;
470 /* Update that everything is now vector-sized. */
471 for (int i
= 0; i
< this->uniforms
; i
++) {
472 this->uniform_size
[i
] = 1;
477 vec4_visitor::pack_uniform_registers()
479 uint8_t chans_used
[this->uniforms
];
480 int new_loc
[this->uniforms
];
481 int new_chan
[this->uniforms
];
483 memset(chans_used
, 0, sizeof(chans_used
));
484 memset(new_loc
, 0, sizeof(new_loc
));
485 memset(new_chan
, 0, sizeof(new_chan
));
487 /* Find which uniform vectors are actually used by the program. We
488 * expect unused vector elements when we've moved array access out
489 * to pull constants, and from some GLSL code generators like wine.
491 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
493 switch (inst
->opcode
) {
494 case VEC4_OPCODE_PACK_BYTES
:
506 readmask
= inst
->dst
.writemask
;
510 for (int i
= 0 ; i
< 3; i
++) {
511 if (inst
->src
[i
].file
!= UNIFORM
)
514 int reg
= inst
->src
[i
].nr
;
515 for (int c
= 0; c
< 4; c
++) {
516 if (!(readmask
& (1 << c
)))
519 chans_used
[reg
] = MAX2(chans_used
[reg
],
520 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
525 int new_uniform_count
= 0;
527 /* Now, figure out a packing of the live uniform vectors into our
530 for (int src
= 0; src
< uniforms
; src
++) {
531 assert(src
< uniform_array_size
);
532 int size
= chans_used
[src
];
538 /* Find the lowest place we can slot this uniform in. */
539 for (dst
= 0; dst
< src
; dst
++) {
540 if (chans_used
[dst
] + size
<= 4)
549 new_chan
[src
] = chans_used
[dst
];
551 /* Move the references to the data */
552 for (int j
= 0; j
< size
; j
++) {
553 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
554 stage_prog_data
->param
[src
* 4 + j
];
557 chans_used
[dst
] += size
;
561 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
564 this->uniforms
= new_uniform_count
;
566 /* Now, update the instructions for our repacked uniforms. */
567 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
568 for (int i
= 0 ; i
< 3; i
++) {
569 int src
= inst
->src
[i
].nr
;
571 if (inst
->src
[i
].file
!= UNIFORM
)
574 inst
->src
[i
].nr
= new_loc
[src
];
575 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
576 new_chan
[src
], new_chan
[src
]);
582 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
584 * While GLSL IR also performs this optimization, we end up with it in
585 * our instruction stream for a couple of reasons. One is that we
586 * sometimes generate silly instructions, for example in array access
587 * where we'll generate "ADD offset, index, base" even if base is 0.
588 * The other is that GLSL IR's constant propagation doesn't track the
589 * components of aggregates, so some VS patterns (initialize matrix to
590 * 0, accumulate in vertex blending factors) end up breaking down to
591 * instructions involving 0.
594 vec4_visitor::opt_algebraic()
596 bool progress
= false;
598 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
599 switch (inst
->opcode
) {
601 if (inst
->src
[0].file
!= IMM
)
604 if (inst
->saturate
) {
605 if (inst
->dst
.type
!= inst
->src
[0].type
)
606 assert(!"unimplemented: saturate mixed types");
608 if (brw_saturate_immediate(inst
->dst
.type
,
609 &inst
->src
[0].as_brw_reg())) {
610 inst
->saturate
= false;
616 case VEC4_OPCODE_UNPACK_UNIFORM
:
617 if (inst
->src
[0].file
!= UNIFORM
) {
618 inst
->opcode
= BRW_OPCODE_MOV
;
624 if (inst
->src
[1].is_zero()) {
625 inst
->opcode
= BRW_OPCODE_MOV
;
626 inst
->src
[1] = src_reg();
632 if (inst
->src
[1].is_zero()) {
633 inst
->opcode
= BRW_OPCODE_MOV
;
634 switch (inst
->src
[0].type
) {
635 case BRW_REGISTER_TYPE_F
:
636 inst
->src
[0] = brw_imm_f(0.0f
);
638 case BRW_REGISTER_TYPE_D
:
639 inst
->src
[0] = brw_imm_d(0);
641 case BRW_REGISTER_TYPE_UD
:
642 inst
->src
[0] = brw_imm_ud(0u);
645 unreachable("not reached");
647 inst
->src
[1] = src_reg();
649 } else if (inst
->src
[1].is_one()) {
650 inst
->opcode
= BRW_OPCODE_MOV
;
651 inst
->src
[1] = src_reg();
653 } else if (inst
->src
[1].is_negative_one()) {
654 inst
->opcode
= BRW_OPCODE_MOV
;
655 inst
->src
[0].negate
= !inst
->src
[0].negate
;
656 inst
->src
[1] = src_reg();
661 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
663 inst
->src
[0].negate
&&
664 inst
->src
[1].is_zero()) {
665 inst
->src
[0].abs
= false;
666 inst
->src
[0].negate
= false;
667 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
672 case SHADER_OPCODE_RCP
: {
673 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
674 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
675 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
676 inst
->opcode
= SHADER_OPCODE_RSQ
;
677 inst
->src
[0] = prev
->src
[0];
683 case SHADER_OPCODE_BROADCAST
:
684 if (is_uniform(inst
->src
[0]) ||
685 inst
->src
[1].is_zero()) {
686 inst
->opcode
= BRW_OPCODE_MOV
;
687 inst
->src
[1] = src_reg();
688 inst
->force_writemask_all
= true;
699 invalidate_live_intervals();
705 * Only a limited number of hardware registers may be used for push
706 * constants, so this turns access to the overflowed constants into
710 vec4_visitor::move_push_constants_to_pull_constants()
712 int pull_constant_loc
[this->uniforms
];
714 /* Only allow 32 registers (256 uniform components) as push constants,
715 * which is the limit on gen6.
717 * If changing this value, note the limitation about total_regs in
720 int max_uniform_components
= 32 * 8;
721 if (this->uniforms
* 4 <= max_uniform_components
)
724 /* Make some sort of choice as to which uniforms get sent to pull
725 * constants. We could potentially do something clever here like
726 * look for the most infrequently used uniform vec4s, but leave
729 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
730 pull_constant_loc
[i
/ 4] = -1;
732 if (i
>= max_uniform_components
) {
733 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
735 /* Try to find an existing copy of this uniform in the pull
736 * constants if it was part of an array access already.
738 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
741 for (matches
= 0; matches
< 4; matches
++) {
742 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
747 pull_constant_loc
[i
/ 4] = j
/ 4;
752 if (pull_constant_loc
[i
/ 4] == -1) {
753 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
754 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
756 for (int j
= 0; j
< 4; j
++) {
757 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
764 /* Now actually rewrite usage of the things we've moved to pull
767 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
768 for (int i
= 0 ; i
< 3; i
++) {
769 if (inst
->src
[i
].file
!= UNIFORM
||
770 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
773 int uniform
= inst
->src
[i
].nr
;
775 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
777 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
778 pull_constant_loc
[uniform
]);
780 inst
->src
[i
].file
= temp
.file
;
781 inst
->src
[i
].nr
= temp
.nr
;
782 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
783 inst
->src
[i
].reladdr
= NULL
;
787 /* Repack push constants to remove the now-unused ones. */
788 pack_uniform_registers();
791 /* Conditions for which we want to avoid setting the dependency control bits */
793 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
795 #define IS_DWORD(reg) \
796 (reg.type == BRW_REGISTER_TYPE_UD || \
797 reg.type == BRW_REGISTER_TYPE_D)
799 /* "When source or destination datatype is 64b or operation is integer DWord
800 * multiply, DepCtrl must not be used."
801 * May apply to future SoCs as well.
803 if (devinfo
->is_cherryview
) {
804 if (inst
->opcode
== BRW_OPCODE_MUL
&&
805 IS_DWORD(inst
->src
[0]) &&
806 IS_DWORD(inst
->src
[1]))
811 if (devinfo
->gen
>= 8) {
812 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
818 * In the presence of send messages, totally interrupt dependency
819 * control. They're long enough that the chance of dependency
820 * control around them just doesn't matter.
823 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
824 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
825 * completes the scoreboard clear must have a non-zero execution mask. This
826 * means, if any kind of predication can change the execution mask or channel
827 * enable of the last instruction, the optimization must be avoided. This is
828 * to avoid instructions being shot down the pipeline when no writes are
832 * Dependency control does not work well over math instructions.
833 * NB: Discovered empirically
835 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
839 * Sets the dependency control fields on instructions after register
840 * allocation and before the generator is run.
842 * When you have a sequence of instructions like:
844 * DP4 temp.x vertex uniform[0]
845 * DP4 temp.y vertex uniform[0]
846 * DP4 temp.z vertex uniform[0]
847 * DP4 temp.w vertex uniform[0]
849 * The hardware doesn't know that it can actually run the later instructions
850 * while the previous ones are in flight, producing stalls. However, we have
851 * manual fields we can set in the instructions that let it do so.
854 vec4_visitor::opt_set_dependency_control()
856 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
857 uint8_t grf_channels_written
[BRW_MAX_GRF
];
858 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
859 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
861 assert(prog_data
->total_grf
||
862 !"Must be called after register allocation");
864 foreach_block (block
, cfg
) {
865 memset(last_grf_write
, 0, sizeof(last_grf_write
));
866 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
868 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
869 /* If we read from a register that we were doing dependency control
870 * on, don't do dependency control across the read.
872 for (int i
= 0; i
< 3; i
++) {
873 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
874 if (inst
->src
[i
].file
== VGRF
) {
875 last_grf_write
[reg
] = NULL
;
876 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
877 memset(last_grf_write
, 0, sizeof(last_grf_write
));
880 assert(inst
->src
[i
].file
!= MRF
);
883 if (is_dep_ctrl_unsafe(inst
)) {
884 memset(last_grf_write
, 0, sizeof(last_grf_write
));
885 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
889 /* Now, see if we can do dependency control for this instruction
890 * against a previous one writing to its destination.
892 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
893 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
894 if (last_grf_write
[reg
] &&
895 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
896 last_grf_write
[reg
]->no_dd_clear
= true;
897 inst
->no_dd_check
= true;
899 grf_channels_written
[reg
] = 0;
902 last_grf_write
[reg
] = inst
;
903 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
904 } else if (inst
->dst
.file
== MRF
) {
905 if (last_mrf_write
[reg
] &&
906 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
907 last_mrf_write
[reg
]->no_dd_clear
= true;
908 inst
->no_dd_check
= true;
910 mrf_channels_written
[reg
] = 0;
913 last_mrf_write
[reg
] = inst
;
914 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
921 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
926 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
927 * or writemasking are not allowed.
929 if (devinfo
->gen
== 6 && is_math() &&
930 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
933 /* If this instruction sets anything not referenced by swizzle, then we'd
934 * totally break it when we reswizzle.
936 if (dst
.writemask
& ~swizzle_mask
)
942 for (int i
= 0; i
< 3; i
++) {
943 if (src
[i
].is_accumulator())
951 * For any channels in the swizzle's source that were populated by this
952 * instruction, rewrite the instruction to put the appropriate result directly
955 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
958 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
960 /* Destination write mask doesn't correspond to source swizzle for the dot
961 * product and pack_bytes instructions.
963 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
964 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
965 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
966 for (int i
= 0; i
< 3; i
++) {
967 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
970 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
974 /* Apply the specified swizzle and writemask to the original mask of
975 * written components.
977 dst
.writemask
= dst_writemask
&
978 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
982 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
983 * just written and then MOVed into another reg and making the original write
984 * of the GRF write directly to the final destination instead.
987 vec4_visitor::opt_register_coalesce()
989 bool progress
= false;
992 calculate_live_intervals();
994 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
998 if (inst
->opcode
!= BRW_OPCODE_MOV
||
999 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1001 inst
->src
[0].file
!= VGRF
||
1002 inst
->dst
.type
!= inst
->src
[0].type
||
1003 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1006 /* Remove no-op MOVs */
1007 if (inst
->dst
.file
== inst
->src
[0].file
&&
1008 inst
->dst
.nr
== inst
->src
[0].nr
&&
1009 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1010 bool is_nop_mov
= true;
1012 for (unsigned c
= 0; c
< 4; c
++) {
1013 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1016 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1023 inst
->remove(block
);
1028 bool to_mrf
= (inst
->dst
.file
== MRF
);
1030 /* Can't coalesce this GRF if someone else was going to
1033 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1036 /* We need to check interference with the final destination between this
1037 * instruction and the earliest instruction involved in writing the GRF
1038 * we're eliminating. To do that, keep track of which of our source
1039 * channels we've seen initialized.
1041 const unsigned chans_needed
=
1042 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1043 inst
->dst
.writemask
);
1044 unsigned chans_remaining
= chans_needed
;
1046 /* Now walk up the instruction stream trying to see if we can rewrite
1047 * everything writing to the temporary to write into the destination
1050 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1051 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1053 _scan_inst
= scan_inst
;
1055 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1056 /* Found something writing to the reg we want to coalesce away. */
1058 /* SEND instructions can't have MRF as a destination. */
1059 if (scan_inst
->mlen
)
1062 if (devinfo
->gen
== 6) {
1063 /* gen6 math instructions must have the destination be
1064 * VGRF, so no compute-to-MRF for them.
1066 if (scan_inst
->is_math()) {
1072 /* This doesn't handle saturation on the instruction we
1073 * want to coalesce away if the register types do not match.
1074 * But if scan_inst is a non type-converting 'mov', we can fix
1077 if (inst
->saturate
&&
1078 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1079 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1080 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1083 /* If we can't handle the swizzle, bail. */
1084 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1085 inst
->src
[0].swizzle
,
1090 /* This doesn't handle coalescing of multiple registers. */
1091 if (scan_inst
->regs_written
> 1)
1094 /* Mark which channels we found unconditional writes for. */
1095 if (!scan_inst
->predicate
)
1096 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1098 if (chans_remaining
== 0)
1102 /* You can't read from an MRF, so if someone else reads our MRF's
1103 * source GRF that we wanted to rewrite, that stops us. If it's a
1104 * GRF we're trying to coalesce to, we don't actually handle
1105 * rewriting sources so bail in that case as well.
1107 bool interfered
= false;
1108 for (int i
= 0; i
< 3; i
++) {
1109 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1110 scan_inst
->regs_read(i
)))
1116 /* If somebody else writes the same channels of our destination here,
1117 * we can't coalesce before that.
1119 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1120 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1124 /* Check for reads of the register we're trying to coalesce into. We
1125 * can't go rewriting instructions above that to put some other value
1126 * in the register instead.
1128 if (to_mrf
&& scan_inst
->mlen
> 0) {
1129 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1130 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1134 for (int i
= 0; i
< 3; i
++) {
1135 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1136 scan_inst
->regs_read(i
)))
1144 if (chans_remaining
== 0) {
1145 /* If we've made it here, we have an MOV we want to coalesce out, and
1146 * a scan_inst pointing to the earliest instruction involved in
1147 * computing the value. Now go rewrite the instruction stream
1150 vec4_instruction
*scan_inst
= _scan_inst
;
1151 while (scan_inst
!= inst
) {
1152 if (scan_inst
->dst
.file
== VGRF
&&
1153 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1154 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1155 scan_inst
->reswizzle(inst
->dst
.writemask
,
1156 inst
->src
[0].swizzle
);
1157 scan_inst
->dst
.file
= inst
->dst
.file
;
1158 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1159 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1160 if (inst
->saturate
&&
1161 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1162 /* If we have reached this point, scan_inst is a non
1163 * type-converting 'mov' and we can modify its register types
1164 * to match the ones in inst. Otherwise, we could have an
1165 * incorrect saturation result.
1167 scan_inst
->dst
.type
= inst
->dst
.type
;
1168 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1170 scan_inst
->saturate
|= inst
->saturate
;
1172 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1174 inst
->remove(block
);
1180 invalidate_live_intervals();
1186 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1187 * flow. We could probably do better here with some form of divergence
1191 vec4_visitor::eliminate_find_live_channel()
1193 bool progress
= false;
1196 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1197 switch (inst
->opcode
) {
1203 case BRW_OPCODE_ENDIF
:
1204 case BRW_OPCODE_WHILE
:
1208 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1210 inst
->opcode
= BRW_OPCODE_MOV
;
1211 inst
->src
[0] = brw_imm_d(0);
1212 inst
->force_writemask_all
= true;
1226 * Splits virtual GRFs requesting more than one contiguous physical register.
1228 * We initially create large virtual GRFs for temporary structures, arrays,
1229 * and matrices, so that the dereference visitor functions can add reg_offsets
1230 * to work their way down to the actual member being accessed. But when it
1231 * comes to optimization, we'd like to treat each register as individual
1232 * storage if possible.
1234 * So far, the only thing that might prevent splitting is a send message from
1238 vec4_visitor::split_virtual_grfs()
1240 int num_vars
= this->alloc
.count
;
1241 int new_virtual_grf
[num_vars
];
1242 bool split_grf
[num_vars
];
1244 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1246 /* Try to split anything > 0 sized. */
1247 for (int i
= 0; i
< num_vars
; i
++) {
1248 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1251 /* Check that the instructions are compatible with the registers we're trying
1254 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1255 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1256 split_grf
[inst
->dst
.nr
] = false;
1258 for (int i
= 0; i
< 3; i
++) {
1259 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1260 split_grf
[inst
->src
[i
].nr
] = false;
1264 /* Allocate new space for split regs. Note that the virtual
1265 * numbers will be contiguous.
1267 for (int i
= 0; i
< num_vars
; i
++) {
1271 new_virtual_grf
[i
] = alloc
.allocate(1);
1272 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1273 unsigned reg
= alloc
.allocate(1);
1274 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1277 this->alloc
.sizes
[i
] = 1;
1280 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1281 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1282 inst
->dst
.reg_offset
!= 0) {
1283 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1284 inst
->dst
.reg_offset
- 1);
1285 inst
->dst
.reg_offset
= 0;
1287 for (int i
= 0; i
< 3; i
++) {
1288 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1289 inst
->src
[i
].reg_offset
!= 0) {
1290 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1291 inst
->src
[i
].reg_offset
- 1);
1292 inst
->src
[i
].reg_offset
= 0;
1296 invalidate_live_intervals();
1300 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1302 dump_instruction(be_inst
, stderr
);
1306 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1308 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1310 if (inst
->predicate
) {
1311 fprintf(file
, "(%cf0.%d%s) ",
1312 inst
->predicate_inverse
? '-' : '+',
1314 pred_ctrl_align16
[inst
->predicate
]);
1317 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1319 fprintf(file
, ".sat");
1320 if (inst
->conditional_mod
) {
1321 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1322 if (!inst
->predicate
&&
1323 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1324 inst
->opcode
!= BRW_OPCODE_IF
&&
1325 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1326 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1331 switch (inst
->dst
.file
) {
1333 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1336 fprintf(file
, "g%d", inst
->dst
.nr
);
1339 fprintf(file
, "m%d", inst
->dst
.nr
);
1342 switch (inst
->dst
.nr
) {
1344 fprintf(file
, "null");
1346 case BRW_ARF_ADDRESS
:
1347 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1349 case BRW_ARF_ACCUMULATOR
:
1350 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1353 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1356 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1359 if (inst
->dst
.subnr
)
1360 fprintf(file
, "+%d", inst
->dst
.subnr
);
1363 fprintf(file
, "(null)");
1368 unreachable("not reached");
1370 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1372 if (inst
->dst
.writemask
& 1)
1374 if (inst
->dst
.writemask
& 2)
1376 if (inst
->dst
.writemask
& 4)
1378 if (inst
->dst
.writemask
& 8)
1381 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1383 if (inst
->src
[0].file
!= BAD_FILE
)
1384 fprintf(file
, ", ");
1386 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1387 if (inst
->src
[i
].negate
)
1389 if (inst
->src
[i
].abs
)
1391 switch (inst
->src
[i
].file
) {
1393 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1396 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1399 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1402 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1405 switch (inst
->src
[i
].type
) {
1406 case BRW_REGISTER_TYPE_F
:
1407 fprintf(file
, "%fF", inst
->src
[i
].f
);
1409 case BRW_REGISTER_TYPE_D
:
1410 fprintf(file
, "%dD", inst
->src
[i
].d
);
1412 case BRW_REGISTER_TYPE_UD
:
1413 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1415 case BRW_REGISTER_TYPE_VF
:
1416 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1417 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1418 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1419 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1420 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1423 fprintf(file
, "???");
1428 switch (inst
->src
[i
].nr
) {
1430 fprintf(file
, "null");
1432 case BRW_ARF_ADDRESS
:
1433 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1435 case BRW_ARF_ACCUMULATOR
:
1436 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1439 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1442 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1445 if (inst
->src
[i
].subnr
)
1446 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1449 fprintf(file
, "(null)");
1452 unreachable("not reached");
1455 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1456 if (inst
->src
[i
].reg_offset
!= 0 &&
1457 inst
->src
[i
].file
== VGRF
&&
1458 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1459 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1461 if (inst
->src
[i
].file
!= IMM
) {
1462 static const char *chans
[4] = {"x", "y", "z", "w"};
1464 for (int c
= 0; c
< 4; c
++) {
1465 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1469 if (inst
->src
[i
].abs
)
1472 if (inst
->src
[i
].file
!= IMM
) {
1473 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1476 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1477 fprintf(file
, ", ");
1480 if (inst
->force_writemask_all
)
1481 fprintf(file
, " NoMask");
1483 fprintf(file
, "\n");
1487 static inline struct brw_reg
1488 attribute_to_hw_reg(int attr
, bool interleaved
)
1491 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1493 return brw_vec8_grf(attr
, 0);
1498 * Replace each register of type ATTR in this->instructions with a reference
1499 * to a fixed HW register.
1501 * If interleaved is true, then each attribute takes up half a register, with
1502 * register N containing attribute 2*N in its first half and attribute 2*N+1
1503 * in its second half (this corresponds to the payload setup used by geometry
1504 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1505 * false, then each attribute takes up a whole register, with register N
1506 * containing attribute N (this corresponds to the payload setup used by
1507 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1510 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1513 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1514 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1515 if (inst
->dst
.file
== ATTR
) {
1516 int grf
= attribute_map
[inst
->dst
.nr
+ inst
->dst
.reg_offset
];
1518 /* All attributes used in the shader need to have been assigned a
1519 * hardware register by the caller
1523 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1524 reg
.type
= inst
->dst
.type
;
1525 reg
.writemask
= inst
->dst
.writemask
;
1530 for (int i
= 0; i
< 3; i
++) {
1531 if (inst
->src
[i
].file
!= ATTR
)
1534 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1536 /* All attributes used in the shader need to have been assigned a
1537 * hardware register by the caller
1541 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1542 reg
.swizzle
= inst
->src
[i
].swizzle
;
1543 reg
.type
= inst
->src
[i
].type
;
1544 if (inst
->src
[i
].abs
)
1546 if (inst
->src
[i
].negate
)
1555 vec4_vs_visitor::setup_attributes(int payload_reg
)
1558 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1559 memset(attribute_map
, 0, sizeof(attribute_map
));
1562 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1563 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1564 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1569 /* VertexID is stored by the VF as the last vertex element, but we
1570 * don't represent it with a flag in inputs_read, so we call it
1573 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1574 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1577 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1579 return payload_reg
+ vs_prog_data
->nr_attributes
;
1583 vec4_visitor::setup_uniforms(int reg
)
1585 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1587 /* The pre-gen6 VS requires that some push constants get loaded no
1588 * matter what, or the GPU would hang.
1590 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1591 assert(this->uniforms
< this->uniform_array_size
);
1593 stage_prog_data
->param
=
1594 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1595 for (unsigned int i
= 0; i
< 4; i
++) {
1596 unsigned int slot
= this->uniforms
* 4 + i
;
1597 static gl_constant_value zero
= { 0.0 };
1598 stage_prog_data
->param
[slot
] = &zero
;
1604 reg
+= ALIGN(uniforms
, 2) / 2;
1607 stage_prog_data
->nr_params
= this->uniforms
* 4;
1609 prog_data
->base
.curb_read_length
=
1610 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1616 vec4_vs_visitor::setup_payload(void)
1620 /* The payload always contains important data in g0, which contains
1621 * the URB handles that are passed on to the URB write at the end
1622 * of the thread. So, we always start push constants at g1.
1626 reg
= setup_uniforms(reg
);
1628 reg
= setup_attributes(reg
);
1630 this->first_non_payload_grf
= reg
;
1634 vec4_visitor::get_timestamp()
1636 assert(devinfo
->gen
>= 7);
1638 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1643 BRW_REGISTER_TYPE_UD
,
1644 BRW_VERTICAL_STRIDE_0
,
1646 BRW_HORIZONTAL_STRIDE_4
,
1650 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1652 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1653 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1654 * even if it's not enabled in the dispatch.
1656 mov
->force_writemask_all
= true;
1658 return src_reg(dst
);
1662 vec4_visitor::emit_shader_time_begin()
1664 current_annotation
= "shader time start";
1665 shader_start_time
= get_timestamp();
1669 vec4_visitor::emit_shader_time_end()
1671 current_annotation
= "shader time end";
1672 src_reg shader_end_time
= get_timestamp();
1675 /* Check that there weren't any timestamp reset events (assuming these
1676 * were the only two timestamp reads that happened).
1678 src_reg reset_end
= shader_end_time
;
1679 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1680 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1681 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1683 emit(IF(BRW_PREDICATE_NORMAL
));
1685 /* Take the current timestamp and get the delta. */
1686 shader_start_time
.negate
= true;
1687 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1688 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1690 /* If there were no instructions between the two timestamp gets, the diff
1691 * is 2 cycles. Remove that overhead, so I can forget about that when
1692 * trying to determine the time taken for single instructions.
1694 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1696 emit_shader_time_write(0, src_reg(diff
));
1697 emit_shader_time_write(1, brw_imm_ud(1u));
1698 emit(BRW_OPCODE_ELSE
);
1699 emit_shader_time_write(2, brw_imm_ud(1u));
1700 emit(BRW_OPCODE_ENDIF
);
1704 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1707 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1709 dst_reg offset
= dst
;
1713 offset
.type
= BRW_REGISTER_TYPE_UD
;
1714 int index
= shader_time_index
* 3 + shader_time_subindex
;
1715 emit(MOV(offset
, brw_imm_d(index
* SHADER_TIME_STRIDE
)));
1717 time
.type
= BRW_REGISTER_TYPE_UD
;
1718 emit(MOV(time
, value
));
1720 vec4_instruction
*inst
=
1721 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1726 vec4_visitor::convert_to_hw_regs()
1728 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1729 for (int i
= 0; i
< 3; i
++) {
1730 struct src_reg
&src
= inst
->src
[i
];
1734 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1735 reg
.type
= src
.type
;
1736 reg
.swizzle
= src
.swizzle
;
1738 reg
.negate
= src
.negate
;
1742 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1743 (src
.nr
+ src
.reg_offset
) / 2,
1744 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1746 reg
.type
= src
.type
;
1747 reg
.swizzle
= src
.swizzle
;
1749 reg
.negate
= src
.negate
;
1751 /* This should have been moved to pull constants. */
1752 assert(!src
.reladdr
);
1761 /* Probably unused. */
1762 reg
= brw_null_reg();
1767 unreachable("not reached");
1772 dst_reg
&dst
= inst
->dst
;
1775 switch (inst
->dst
.file
) {
1777 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1778 reg
.type
= dst
.type
;
1779 reg
.writemask
= dst
.writemask
;
1783 assert(((dst
.nr
+ dst
.reg_offset
) & ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
1784 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1785 reg
.type
= dst
.type
;
1786 reg
.writemask
= dst
.writemask
;
1791 reg
= dst
.as_brw_reg();
1795 reg
= brw_null_reg();
1801 unreachable("not reached");
1811 if (shader_time_index
>= 0)
1812 emit_shader_time_begin();
1825 /* Before any optimization, push array accesses out to scratch
1826 * space where we need them to be. This pass may allocate new
1827 * virtual GRFs, so we want to do it early. It also makes sure
1828 * that we have reladdr computations available for CSE, since we'll
1829 * often do repeated subexpressions for those.
1831 move_grf_array_access_to_scratch();
1832 move_uniform_array_access_to_pull_constants();
1834 pack_uniform_registers();
1835 move_push_constants_to_pull_constants();
1836 split_virtual_grfs();
1838 #define OPT(pass, args...) ({ \
1840 bool this_progress = pass(args); \
1842 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1843 char filename[64]; \
1844 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1845 stage_abbrev, nir->info.name, iteration, pass_num); \
1847 backend_shader::dump_instructions(filename); \
1850 progress = progress || this_progress; \
1855 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1857 snprintf(filename
, 64, "%s-%s-00-start",
1858 stage_abbrev
, nir
->info
.name
);
1860 backend_shader::dump_instructions(filename
);
1871 OPT(opt_predicated_break
, this);
1872 OPT(opt_reduce_swizzle
);
1873 OPT(dead_code_eliminate
);
1874 OPT(dead_control_flow_eliminate
, this);
1875 OPT(opt_copy_propagation
);
1876 OPT(opt_cmod_propagation
);
1879 OPT(opt_register_coalesce
);
1880 OPT(eliminate_find_live_channel
);
1885 if (OPT(opt_vector_float
)) {
1887 OPT(opt_copy_propagation
, false);
1888 OPT(opt_copy_propagation
, true);
1889 OPT(dead_code_eliminate
);
1897 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1898 /* Debug of register spilling: Go spill everything. */
1899 const int grf_count
= alloc
.count
;
1900 float spill_costs
[alloc
.count
];
1901 bool no_spill
[alloc
.count
];
1902 evaluate_spill_costs(spill_costs
, no_spill
);
1903 for (int i
= 0; i
< grf_count
; i
++) {
1910 bool allocated_without_spills
= reg_allocate();
1912 if (!allocated_without_spills
) {
1913 compiler
->shader_perf_log(log_data
,
1914 "%s shader triggered register spilling. "
1915 "Try reducing the number of live vec4 values "
1916 "to improve performance.\n",
1919 while (!reg_allocate()) {
1925 opt_schedule_instructions();
1927 opt_set_dependency_control();
1929 convert_to_hw_regs();
1931 if (last_scratch
> 0) {
1932 prog_data
->base
.total_scratch
=
1933 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1939 } /* namespace brw */
1944 * Compile a vertex shader.
1946 * Returns the final assembly and the program's size.
1949 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1951 const struct brw_vs_prog_key
*key
,
1952 struct brw_vs_prog_data
*prog_data
,
1953 const nir_shader
*src_shader
,
1954 gl_clip_plane
*clip_planes
,
1955 bool use_legacy_snorm_formula
,
1956 int shader_time_index
,
1957 unsigned *final_assembly_size
,
1960 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
1961 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
1962 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
1963 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
,
1964 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
1966 const unsigned *assembly
= NULL
;
1968 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
1970 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
1971 * incoming vertex attribute. So, add an extra slot.
1973 if (shader
->info
.system_values_read
&
1974 (BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
1975 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
1979 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
1980 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
1981 * vec4 mode, the hardware appears to wedge unless we read something.
1983 if (compiler
->scalar_stage
[MESA_SHADER_VERTEX
])
1984 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
1986 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
1988 prog_data
->nr_attributes
= nr_attributes
;
1990 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
1991 * (overwriting the original contents), we need to make sure the size is
1992 * the larger of the two.
1994 const unsigned vue_entries
=
1995 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
1997 if (compiler
->devinfo
->gen
== 6)
1998 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2000 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2002 if (compiler
->scalar_stage
[MESA_SHADER_VERTEX
]) {
2003 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2005 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2006 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2007 shader
, 8, shader_time_index
);
2008 if (!v
.run_vs(clip_planes
)) {
2010 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2015 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2016 &prog_data
->base
.base
, v
.promoted_constants
,
2017 v
.runtime_check_aads_emit
, "VS");
2018 if (INTEL_DEBUG
& DEBUG_VS
) {
2019 const char *debug_name
=
2020 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2021 shader
->info
.label
? shader
->info
.label
: "unnamed",
2024 g
.enable_debug(debug_name
);
2026 g
.generate_code(v
.cfg
, 8);
2027 assembly
= g
.get_assembly(final_assembly_size
);
2031 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2033 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2034 shader
, clip_planes
, mem_ctx
,
2035 shader_time_index
, use_legacy_snorm_formula
);
2038 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2043 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2044 shader
, &prog_data
->base
, v
.cfg
,
2045 final_assembly_size
);