2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "main/macros.h"
30 #include "main/shaderobj.h"
31 #include "program/prog_print.h"
32 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
42 * Common helper for constructing swizzles. When only a subset of
43 * channels of a vec4 are used, we don't want to reference the other
44 * channels, as that will tell optimization passes that those other
48 swizzle_for_size(int size
)
50 static const unsigned size_swizzles
[4] = {
51 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
57 assert((size
>= 1) && (size
<= 4));
58 return size_swizzles
[size
- 1];
64 memset(this, 0, sizeof(*this));
66 this->file
= BAD_FILE
;
69 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
75 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
76 this->swizzle
= swizzle_for_size(type
->vector_elements
);
78 this->swizzle
= SWIZZLE_XYZW
;
81 /** Generic unset register constructor. */
87 src_reg::src_reg(float f
)
92 this->type
= BRW_REGISTER_TYPE_F
;
96 src_reg::src_reg(uint32_t u
)
101 this->type
= BRW_REGISTER_TYPE_UD
;
105 src_reg::src_reg(int32_t i
)
110 this->type
= BRW_REGISTER_TYPE_D
;
114 src_reg::src_reg(dst_reg reg
)
118 this->file
= reg
.file
;
120 this->reg_offset
= reg
.reg_offset
;
121 this->type
= reg
.type
;
122 this->reladdr
= reg
.reladdr
;
123 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
129 for (int i
= 0; i
< 4; i
++) {
130 if (!(reg
.writemask
& (1 << i
)))
133 swizzles
[next_chan
++] = last
= i
;
136 for (; next_chan
< 4; next_chan
++) {
137 swizzles
[next_chan
] = last
;
140 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
141 swizzles
[2], swizzles
[3]);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(struct brw_reg reg
)
181 this->fixed_hw_reg
= reg
;
184 dst_reg::dst_reg(src_reg reg
)
188 this->file
= reg
.file
;
190 this->reg_offset
= reg
.reg_offset
;
191 this->type
= reg
.type
;
192 /* How should we do writemasking when converting from a src_reg? It seems
193 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
194 * what about for src.wx? Just special-case src.xxxx for now.
196 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
197 this->writemask
= WRITEMASK_X
;
199 this->writemask
= WRITEMASK_XYZW
;
200 this->reladdr
= reg
.reladdr
;
201 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
205 vec4_instruction::is_send_from_grf()
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
217 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
219 if (brw
->gen
== 6 && inst
->is_math())
222 if (inst
->is_send_from_grf())
229 * Returns how many MRFs an opcode will write over.
231 * Note that this is not the 0 or 1 implied writes in an actual gen
232 * instruction -- the generate_* functions generate additional MOVs
236 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
241 switch (inst
->opcode
) {
242 case SHADER_OPCODE_RCP
:
243 case SHADER_OPCODE_RSQ
:
244 case SHADER_OPCODE_SQRT
:
245 case SHADER_OPCODE_EXP2
:
246 case SHADER_OPCODE_LOG2
:
247 case SHADER_OPCODE_SIN
:
248 case SHADER_OPCODE_COS
:
250 case SHADER_OPCODE_INT_QUOTIENT
:
251 case SHADER_OPCODE_INT_REMAINDER
:
252 case SHADER_OPCODE_POW
:
254 case VS_OPCODE_URB_WRITE
:
256 case VS_OPCODE_PULL_CONSTANT_LOAD
:
258 case VS_OPCODE_SCRATCH_READ
:
260 case VS_OPCODE_SCRATCH_WRITE
:
262 case SHADER_OPCODE_SHADER_TIME_ADD
:
264 case SHADER_OPCODE_TEX
:
265 case SHADER_OPCODE_TXL
:
266 case SHADER_OPCODE_TXD
:
267 case SHADER_OPCODE_TXF
:
268 case SHADER_OPCODE_TXF_MS
:
269 case SHADER_OPCODE_TXS
:
270 return inst
->header_present
? 1 : 0;
272 assert(!"not reached");
278 src_reg::equals(src_reg
*r
)
280 return (file
== r
->file
&&
282 reg_offset
== r
->reg_offset
&&
284 negate
== r
->negate
&&
286 swizzle
== r
->swizzle
&&
287 !reladdr
&& !r
->reladdr
&&
288 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
289 sizeof(fixed_hw_reg
)) == 0 &&
294 * Must be called after calculate_live_intervales() to remove unused
295 * writes to registers -- register allocation will fail otherwise
296 * because something deffed but not used won't be considered to
297 * interfere with other regs.
300 vec4_visitor::dead_code_eliminate()
302 bool progress
= false;
305 calculate_live_intervals();
307 foreach_list_safe(node
, &this->instructions
) {
308 vec4_instruction
*inst
= (vec4_instruction
*)node
;
310 if (inst
->dst
.file
== GRF
) {
311 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
312 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
322 live_intervals_valid
= false;
328 vec4_visitor::split_uniform_registers()
330 /* Prior to this, uniforms have been in an array sized according to
331 * the number of vector uniforms present, sparsely filled (so an
332 * aggregate results in reg indices being skipped over). Now we're
333 * going to cut those aggregates up so each .reg index is one
334 * vector. The goal is to make elimination of unused uniform
335 * components easier later.
337 foreach_list(node
, &this->instructions
) {
338 vec4_instruction
*inst
= (vec4_instruction
*)node
;
340 for (int i
= 0 ; i
< 3; i
++) {
341 if (inst
->src
[i
].file
!= UNIFORM
)
344 assert(!inst
->src
[i
].reladdr
);
346 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
347 inst
->src
[i
].reg_offset
= 0;
351 /* Update that everything is now vector-sized. */
352 for (int i
= 0; i
< this->uniforms
; i
++) {
353 this->uniform_size
[i
] = 1;
358 vec4_visitor::pack_uniform_registers()
360 bool uniform_used
[this->uniforms
];
361 int new_loc
[this->uniforms
];
362 int new_chan
[this->uniforms
];
364 memset(uniform_used
, 0, sizeof(uniform_used
));
365 memset(new_loc
, 0, sizeof(new_loc
));
366 memset(new_chan
, 0, sizeof(new_chan
));
368 /* Find which uniform vectors are actually used by the program. We
369 * expect unused vector elements when we've moved array access out
370 * to pull constants, and from some GLSL code generators like wine.
372 foreach_list(node
, &this->instructions
) {
373 vec4_instruction
*inst
= (vec4_instruction
*)node
;
375 for (int i
= 0 ; i
< 3; i
++) {
376 if (inst
->src
[i
].file
!= UNIFORM
)
379 uniform_used
[inst
->src
[i
].reg
] = true;
383 int new_uniform_count
= 0;
385 /* Now, figure out a packing of the live uniform vectors into our
388 for (int src
= 0; src
< uniforms
; src
++) {
389 int size
= this->uniform_vector_size
[src
];
391 if (!uniform_used
[src
]) {
392 this->uniform_vector_size
[src
] = 0;
397 /* Find the lowest place we can slot this uniform in. */
398 for (dst
= 0; dst
< src
; dst
++) {
399 if (this->uniform_vector_size
[dst
] + size
<= 4)
408 new_chan
[src
] = this->uniform_vector_size
[dst
];
410 /* Move the references to the data */
411 for (int j
= 0; j
< size
; j
++) {
412 prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
413 prog_data
->param
[src
* 4 + j
];
416 this->uniform_vector_size
[dst
] += size
;
417 this->uniform_vector_size
[src
] = 0;
420 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
423 this->uniforms
= new_uniform_count
;
425 /* Now, update the instructions for our repacked uniforms. */
426 foreach_list(node
, &this->instructions
) {
427 vec4_instruction
*inst
= (vec4_instruction
*)node
;
429 for (int i
= 0 ; i
< 3; i
++) {
430 int src
= inst
->src
[i
].reg
;
432 if (inst
->src
[i
].file
!= UNIFORM
)
435 inst
->src
[i
].reg
= new_loc
[src
];
437 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
438 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
439 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
440 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
441 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
447 src_reg::is_zero() const
452 if (type
== BRW_REGISTER_TYPE_F
) {
460 src_reg::is_one() const
465 if (type
== BRW_REGISTER_TYPE_F
) {
473 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
475 * While GLSL IR also performs this optimization, we end up with it in
476 * our instruction stream for a couple of reasons. One is that we
477 * sometimes generate silly instructions, for example in array access
478 * where we'll generate "ADD offset, index, base" even if base is 0.
479 * The other is that GLSL IR's constant propagation doesn't track the
480 * components of aggregates, so some VS patterns (initialize matrix to
481 * 0, accumulate in vertex blending factors) end up breaking down to
482 * instructions involving 0.
485 vec4_visitor::opt_algebraic()
487 bool progress
= false;
489 foreach_list(node
, &this->instructions
) {
490 vec4_instruction
*inst
= (vec4_instruction
*)node
;
492 switch (inst
->opcode
) {
494 if (inst
->src
[1].is_zero()) {
495 inst
->opcode
= BRW_OPCODE_MOV
;
496 inst
->src
[1] = src_reg();
502 if (inst
->src
[1].is_zero()) {
503 inst
->opcode
= BRW_OPCODE_MOV
;
504 switch (inst
->src
[0].type
) {
505 case BRW_REGISTER_TYPE_F
:
506 inst
->src
[0] = src_reg(0.0f
);
508 case BRW_REGISTER_TYPE_D
:
509 inst
->src
[0] = src_reg(0);
511 case BRW_REGISTER_TYPE_UD
:
512 inst
->src
[0] = src_reg(0u);
515 assert(!"not reached");
516 inst
->src
[0] = src_reg(0.0f
);
519 inst
->src
[1] = src_reg();
521 } else if (inst
->src
[1].is_one()) {
522 inst
->opcode
= BRW_OPCODE_MOV
;
523 inst
->src
[1] = src_reg();
533 this->live_intervals_valid
= false;
539 * Only a limited number of hardware registers may be used for push
540 * constants, so this turns access to the overflowed constants into
544 vec4_visitor::move_push_constants_to_pull_constants()
546 int pull_constant_loc
[this->uniforms
];
548 /* Only allow 32 registers (256 uniform components) as push constants,
549 * which is the limit on gen6.
551 int max_uniform_components
= 32 * 8;
552 if (this->uniforms
* 4 <= max_uniform_components
)
555 /* Make some sort of choice as to which uniforms get sent to pull
556 * constants. We could potentially do something clever here like
557 * look for the most infrequently used uniform vec4s, but leave
560 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
561 pull_constant_loc
[i
/ 4] = -1;
563 if (i
>= max_uniform_components
) {
564 const float **values
= &prog_data
->param
[i
];
566 /* Try to find an existing copy of this uniform in the pull
567 * constants if it was part of an array access already.
569 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
572 for (matches
= 0; matches
< 4; matches
++) {
573 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
578 pull_constant_loc
[i
/ 4] = j
/ 4;
583 if (pull_constant_loc
[i
/ 4] == -1) {
584 assert(prog_data
->nr_pull_params
% 4 == 0);
585 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
587 for (int j
= 0; j
< 4; j
++) {
588 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
594 /* Now actually rewrite usage of the things we've moved to pull
597 foreach_list_safe(node
, &this->instructions
) {
598 vec4_instruction
*inst
= (vec4_instruction
*)node
;
600 for (int i
= 0 ; i
< 3; i
++) {
601 if (inst
->src
[i
].file
!= UNIFORM
||
602 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
605 int uniform
= inst
->src
[i
].reg
;
607 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
609 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
610 pull_constant_loc
[uniform
]);
612 inst
->src
[i
].file
= temp
.file
;
613 inst
->src
[i
].reg
= temp
.reg
;
614 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
615 inst
->src
[i
].reladdr
= NULL
;
619 /* Repack push constants to remove the now-unused ones. */
620 pack_uniform_registers();
624 * Sets the dependency control fields on instructions after register
625 * allocation and before the generator is run.
627 * When you have a sequence of instructions like:
629 * DP4 temp.x vertex uniform[0]
630 * DP4 temp.y vertex uniform[0]
631 * DP4 temp.z vertex uniform[0]
632 * DP4 temp.w vertex uniform[0]
634 * The hardware doesn't know that it can actually run the later instructions
635 * while the previous ones are in flight, producing stalls. However, we have
636 * manual fields we can set in the instructions that let it do so.
639 vec4_visitor::opt_set_dependency_control()
641 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
642 uint8_t grf_channels_written
[BRW_MAX_GRF
];
643 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
644 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
648 assert(prog_data
->total_grf
||
649 !"Must be called after register allocation");
651 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
652 bblock_t
*bblock
= cfg
.blocks
[i
];
653 vec4_instruction
*inst
;
655 memset(last_grf_write
, 0, sizeof(last_grf_write
));
656 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
658 for (inst
= (vec4_instruction
*)bblock
->start
;
659 inst
!= (vec4_instruction
*)bblock
->end
->next
;
660 inst
= (vec4_instruction
*)inst
->next
) {
661 /* If we read from a register that we were doing dependency control
662 * on, don't do dependency control across the read.
664 for (int i
= 0; i
< 3; i
++) {
665 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
666 if (inst
->src
[i
].file
== GRF
) {
667 last_grf_write
[reg
] = NULL
;
668 } else if (inst
->src
[i
].file
== HW_REG
) {
669 memset(last_grf_write
, 0, sizeof(last_grf_write
));
672 assert(inst
->src
[i
].file
!= MRF
);
675 /* In the presence of send messages, totally interrupt dependency
676 * control. They're long enough that the chance of dependency
677 * control around them just doesn't matter.
680 memset(last_grf_write
, 0, sizeof(last_grf_write
));
681 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
685 /* It looks like setting dependency control on a predicated
686 * instruction hangs the GPU.
688 if (inst
->predicate
) {
689 memset(last_grf_write
, 0, sizeof(last_grf_write
));
690 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
694 /* Now, see if we can do dependency control for this instruction
695 * against a previous one writing to its destination.
697 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
698 if (inst
->dst
.file
== GRF
) {
699 if (last_grf_write
[reg
] &&
700 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
701 last_grf_write
[reg
]->no_dd_clear
= true;
702 inst
->no_dd_check
= true;
704 grf_channels_written
[reg
] = 0;
707 last_grf_write
[reg
] = inst
;
708 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
709 } else if (inst
->dst
.file
== MRF
) {
710 if (last_mrf_write
[reg
] &&
711 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
712 last_mrf_write
[reg
]->no_dd_clear
= true;
713 inst
->no_dd_check
= true;
715 mrf_channels_written
[reg
] = 0;
718 last_mrf_write
[reg
] = inst
;
719 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
720 } else if (inst
->dst
.reg
== HW_REG
) {
721 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
722 memset(last_grf_write
, 0, sizeof(last_grf_write
));
723 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
724 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
731 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
735 /* If this instruction sets anything not referenced by swizzle, then we'd
736 * totally break it when we reswizzle.
738 if (dst
.writemask
& ~swizzle_mask
)
747 /* Check if there happens to be no reswizzling required. */
748 for (int c
= 0; c
< 4; c
++) {
749 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
750 /* Skip components of the swizzle not used by the dst. */
751 if (!(dst_writemask
& (1 << c
)))
754 /* We don't do the reswizzling yet, so just sanity check that we
765 * For any channels in the swizzle's source that were populated by this
766 * instruction, rewrite the instruction to put the appropriate result directly
769 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
772 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
774 int new_writemask
= 0;
780 for (int c
= 0; c
< 4; c
++) {
781 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
782 /* Skip components of the swizzle not used by the dst. */
783 if (!(dst_writemask
& (1 << c
)))
785 /* If we were populating this component, then populate the
786 * corresponding channel of the new dst.
788 if (dst
.writemask
& bit
)
789 new_writemask
|= (1 << c
);
791 dst
.writemask
= new_writemask
;
794 for (int c
= 0; c
< 4; c
++) {
795 /* Skip components of the swizzle not used by the dst. */
796 if (!(dst_writemask
& (1 << c
)))
799 /* We don't do the reswizzling yet, so just sanity check that we
802 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
809 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
810 * just written and then MOVed into another reg and making the original write
811 * of the GRF write directly to the final destination instead.
814 vec4_visitor::opt_register_coalesce()
816 bool progress
= false;
819 calculate_live_intervals();
821 foreach_list_safe(node
, &this->instructions
) {
822 vec4_instruction
*inst
= (vec4_instruction
*)node
;
827 if (inst
->opcode
!= BRW_OPCODE_MOV
||
828 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
830 inst
->src
[0].file
!= GRF
||
831 inst
->dst
.type
!= inst
->src
[0].type
||
832 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
835 bool to_mrf
= (inst
->dst
.file
== MRF
);
837 /* Can't coalesce this GRF if someone else was going to
840 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
843 /* We need to check interference with the final destination between this
844 * instruction and the earliest instruction involved in writing the GRF
845 * we're eliminating. To do that, keep track of which of our source
846 * channels we've seen initialized.
848 bool chans_needed
[4] = {false, false, false, false};
849 int chans_remaining
= 0;
850 int swizzle_mask
= 0;
851 for (int i
= 0; i
< 4; i
++) {
852 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
854 if (!(inst
->dst
.writemask
& (1 << i
)))
857 swizzle_mask
|= (1 << chan
);
859 if (!chans_needed
[chan
]) {
860 chans_needed
[chan
] = true;
865 /* Now walk up the instruction stream trying to see if we can rewrite
866 * everything writing to the temporary to write into the destination
869 vec4_instruction
*scan_inst
;
870 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
871 scan_inst
->prev
!= NULL
;
872 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
873 if (scan_inst
->dst
.file
== GRF
&&
874 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
875 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
876 /* Found something writing to the reg we want to coalesce away. */
878 /* SEND instructions can't have MRF as a destination. */
883 /* gen6 math instructions must have the destination be
884 * GRF, so no compute-to-MRF for them.
886 if (scan_inst
->is_math()) {
892 /* If we can't handle the swizzle, bail. */
893 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
894 inst
->src
[0].swizzle
,
899 /* Mark which channels we found unconditional writes for. */
900 if (!scan_inst
->predicate
) {
901 for (int i
= 0; i
< 4; i
++) {
902 if (scan_inst
->dst
.writemask
& (1 << i
) &&
904 chans_needed
[i
] = false;
910 if (chans_remaining
== 0)
914 /* We don't handle flow control here. Most computation of values
915 * that could be coalesced happens just before their use.
917 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
918 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
919 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
920 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
924 /* You can't read from an MRF, so if someone else reads our MRF's
925 * source GRF that we wanted to rewrite, that stops us. If it's a
926 * GRF we're trying to coalesce to, we don't actually handle
927 * rewriting sources so bail in that case as well.
929 bool interfered
= false;
930 for (int i
= 0; i
< 3; i
++) {
931 if (scan_inst
->src
[i
].file
== GRF
&&
932 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
933 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
940 /* If somebody else writes our destination here, we can't coalesce
943 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
944 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
948 /* Check for reads of the register we're trying to coalesce into. We
949 * can't go rewriting instructions above that to put some other value
950 * in the register instead.
952 if (to_mrf
&& scan_inst
->mlen
> 0) {
953 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
954 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
958 for (int i
= 0; i
< 3; i
++) {
959 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
960 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
961 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
970 if (chans_remaining
== 0) {
971 /* If we've made it here, we have an MOV we want to coalesce out, and
972 * a scan_inst pointing to the earliest instruction involved in
973 * computing the value. Now go rewrite the instruction stream
977 while (scan_inst
!= inst
) {
978 if (scan_inst
->dst
.file
== GRF
&&
979 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
980 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
981 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
982 inst
->src
[0].swizzle
);
983 scan_inst
->dst
.file
= inst
->dst
.file
;
984 scan_inst
->dst
.reg
= inst
->dst
.reg
;
985 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
986 scan_inst
->saturate
|= inst
->saturate
;
988 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
996 live_intervals_valid
= false;
1002 * Splits virtual GRFs requesting more than one contiguous physical register.
1004 * We initially create large virtual GRFs for temporary structures, arrays,
1005 * and matrices, so that the dereference visitor functions can add reg_offsets
1006 * to work their way down to the actual member being accessed. But when it
1007 * comes to optimization, we'd like to treat each register as individual
1008 * storage if possible.
1010 * So far, the only thing that might prevent splitting is a send message from
1014 vec4_visitor::split_virtual_grfs()
1016 int num_vars
= this->virtual_grf_count
;
1017 int new_virtual_grf
[num_vars
];
1018 bool split_grf
[num_vars
];
1020 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1022 /* Try to split anything > 0 sized. */
1023 for (int i
= 0; i
< num_vars
; i
++) {
1024 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1027 /* Check that the instructions are compatible with the registers we're trying
1030 foreach_list(node
, &this->instructions
) {
1031 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1033 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1034 * contiguous. Assume that the GRF for the SEND is always in src[0].
1036 if (inst
->is_send_from_grf()) {
1037 split_grf
[inst
->src
[0].reg
] = false;
1041 /* Allocate new space for split regs. Note that the virtual
1042 * numbers will be contiguous.
1044 for (int i
= 0; i
< num_vars
; i
++) {
1048 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1049 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1050 int reg
= virtual_grf_alloc(1);
1051 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1054 this->virtual_grf_sizes
[i
] = 1;
1057 foreach_list(node
, &this->instructions
) {
1058 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1060 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1061 inst
->dst
.reg_offset
!= 0) {
1062 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1063 inst
->dst
.reg_offset
- 1);
1064 inst
->dst
.reg_offset
= 0;
1066 for (int i
= 0; i
< 3; i
++) {
1067 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1068 inst
->src
[i
].reg_offset
!= 0) {
1069 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1070 inst
->src
[i
].reg_offset
- 1);
1071 inst
->src
[i
].reg_offset
= 0;
1075 this->live_intervals_valid
= false;
1079 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1081 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1083 printf("%s ", brw_instruction_name(inst
->opcode
));
1085 switch (inst
->dst
.file
) {
1087 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1090 printf("m%d", inst
->dst
.reg
);
1099 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1101 if (inst
->dst
.writemask
& 1)
1103 if (inst
->dst
.writemask
& 2)
1105 if (inst
->dst
.writemask
& 4)
1107 if (inst
->dst
.writemask
& 8)
1112 for (int i
= 0; i
< 3; i
++) {
1113 switch (inst
->src
[i
].file
) {
1115 printf("vgrf%d", inst
->src
[i
].reg
);
1118 printf("attr%d", inst
->src
[i
].reg
);
1121 printf("u%d", inst
->src
[i
].reg
);
1124 switch (inst
->src
[i
].type
) {
1125 case BRW_REGISTER_TYPE_F
:
1126 printf("%fF", inst
->src
[i
].imm
.f
);
1128 case BRW_REGISTER_TYPE_D
:
1129 printf("%dD", inst
->src
[i
].imm
.i
);
1131 case BRW_REGISTER_TYPE_UD
:
1132 printf("%uU", inst
->src
[i
].imm
.u
);
1147 if (inst
->src
[i
].reg_offset
)
1148 printf(".%d", inst
->src
[i
].reg_offset
);
1150 static const char *chans
[4] = {"x", "y", "z", "w"};
1152 for (int c
= 0; c
< 4; c
++) {
1153 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1164 * Replace each register of type ATTR in this->instructions with a reference
1165 * to a fixed HW register.
1168 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
)
1170 foreach_list(node
, &this->instructions
) {
1171 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1173 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1174 if (inst
->dst
.file
== ATTR
) {
1175 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1177 /* All attributes used in the shader need to have been assigned a
1178 * hardware register by the caller
1182 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1183 reg
.type
= inst
->dst
.type
;
1184 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1186 inst
->dst
.file
= HW_REG
;
1187 inst
->dst
.fixed_hw_reg
= reg
;
1190 for (int i
= 0; i
< 3; i
++) {
1191 if (inst
->src
[i
].file
!= ATTR
)
1194 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1196 /* All attributes used in the shader need to have been assigned a
1197 * hardware register by the caller
1201 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1202 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1203 reg
.type
= inst
->src
[i
].type
;
1204 if (inst
->src
[i
].abs
)
1206 if (inst
->src
[i
].negate
)
1209 inst
->src
[i
].file
= HW_REG
;
1210 inst
->src
[i
].fixed_hw_reg
= reg
;
1216 vec4_vs_visitor::setup_attributes(int payload_reg
)
1219 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1220 memset(attribute_map
, 0, sizeof(attribute_map
));
1223 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1224 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1225 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1230 /* VertexID is stored by the VF as the last vertex element, but we
1231 * don't represent it with a flag in inputs_read, so we call it
1234 if (vs_prog_data
->uses_vertexid
) {
1235 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1239 lower_attributes_to_hw_regs(attribute_map
);
1241 /* The BSpec says we always have to read at least one thing from
1242 * the VF, and it appears that the hardware wedges otherwise.
1244 if (nr_attributes
== 0)
1247 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1249 unsigned vue_entries
=
1250 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1253 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1255 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1257 return payload_reg
+ nr_attributes
;
1261 vec4_visitor::setup_uniforms(int reg
)
1263 prog_data
->dispatch_grf_start_reg
= reg
;
1265 /* The pre-gen6 VS requires that some push constants get loaded no
1266 * matter what, or the GPU would hang.
1268 if (brw
->gen
< 6 && this->uniforms
== 0) {
1269 this->uniform_vector_size
[this->uniforms
] = 1;
1271 for (unsigned int i
= 0; i
< 4; i
++) {
1272 unsigned int slot
= this->uniforms
* 4 + i
;
1273 static float zero
= 0.0;
1274 prog_data
->param
[slot
] = &zero
;
1280 reg
+= ALIGN(uniforms
, 2) / 2;
1283 prog_data
->nr_params
= this->uniforms
* 4;
1285 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1291 vec4_vs_visitor::setup_payload(void)
1295 /* The payload always contains important data in g0, which contains
1296 * the URB handles that are passed on to the URB write at the end
1297 * of the thread. So, we always start push constants at g1.
1301 reg
= setup_uniforms(reg
);
1303 reg
= setup_attributes(reg
);
1305 this->first_non_payload_grf
= reg
;
1309 vec4_visitor::get_timestamp()
1311 assert(brw
->gen
>= 7);
1313 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1316 BRW_REGISTER_TYPE_UD
,
1317 BRW_VERTICAL_STRIDE_0
,
1319 BRW_HORIZONTAL_STRIDE_4
,
1323 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1325 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1326 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1327 * even if it's not enabled in the dispatch.
1329 mov
->force_writemask_all
= true;
1331 return src_reg(dst
);
1335 vec4_visitor::emit_shader_time_begin()
1337 current_annotation
= "shader time start";
1338 shader_start_time
= get_timestamp();
1342 vec4_visitor::emit_shader_time_end()
1344 current_annotation
= "shader time end";
1345 src_reg shader_end_time
= get_timestamp();
1348 /* Check that there weren't any timestamp reset events (assuming these
1349 * were the only two timestamp reads that happened).
1351 src_reg reset_end
= shader_end_time
;
1352 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1353 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1354 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1356 emit(IF(BRW_PREDICATE_NORMAL
));
1358 /* Take the current timestamp and get the delta. */
1359 shader_start_time
.negate
= true;
1360 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1361 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1363 /* If there were no instructions between the two timestamp gets, the diff
1364 * is 2 cycles. Remove that overhead, so I can forget about that when
1365 * trying to determine the time taken for single instructions.
1367 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1369 emit_shader_time_write(ST_VS
, src_reg(diff
));
1370 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1371 emit(BRW_OPCODE_ELSE
);
1372 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1373 emit(BRW_OPCODE_ENDIF
);
1377 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1380 int shader_time_index
=
1381 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1384 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1386 dst_reg offset
= dst
;
1390 offset
.type
= BRW_REGISTER_TYPE_UD
;
1391 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1393 time
.type
= BRW_REGISTER_TYPE_UD
;
1394 emit(MOV(time
, src_reg(value
)));
1396 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1402 sanity_param_count
= prog
->Parameters
->NumParameters
;
1404 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1405 emit_shader_time_begin();
1409 /* Generate VS IR for main(). (the visitor only descends into
1410 * functions called "main").
1413 visit_instructions(shader
->ir
);
1415 emit_program_code();
1419 if (key
->userclip_active
&& !key
->uses_clip_distance
)
1420 setup_uniform_clipplane_values();
1424 /* Before any optimization, push array accesses out to scratch
1425 * space where we need them to be. This pass may allocate new
1426 * virtual GRFs, so we want to do it early. It also makes sure
1427 * that we have reladdr computations available for CSE, since we'll
1428 * often do repeated subexpressions for those.
1431 move_grf_array_access_to_scratch();
1432 move_uniform_array_access_to_pull_constants();
1434 /* The ARB_vertex_program frontend emits pull constant loads directly
1435 * rather than using reladdr, so we don't need to walk through all the
1436 * instructions looking for things to move. There isn't anything.
1438 * We do still need to split things to vec4 size.
1440 split_uniform_registers();
1442 pack_uniform_registers();
1443 move_push_constants_to_pull_constants();
1444 split_virtual_grfs();
1449 progress
= dead_code_eliminate() || progress
;
1450 progress
= opt_copy_propagation() || progress
;
1451 progress
= opt_algebraic() || progress
;
1452 progress
= opt_register_coalesce() || progress
;
1462 /* Debug of register spilling: Go spill everything. */
1463 const int grf_count
= virtual_grf_count
;
1464 float spill_costs
[virtual_grf_count
];
1465 bool no_spill
[virtual_grf_count
];
1466 evaluate_spill_costs(spill_costs
, no_spill
);
1467 for (int i
= 0; i
< grf_count
; i
++) {
1474 while (!reg_allocate()) {
1479 opt_schedule_instructions();
1481 opt_set_dependency_control();
1483 /* If any state parameters were appended, then ParameterValues could have
1484 * been realloced, in which case the driver uniform storage set up by
1485 * _mesa_associate_uniform_storage() would point to freed memory. Make
1486 * sure that didn't happen.
1488 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1493 } /* namespace brw */
1498 * Compile a vertex shader.
1500 * Returns the final assembly and the program's size.
1503 brw_vs_emit(struct brw_context
*brw
,
1504 struct gl_shader_program
*prog
,
1505 struct brw_vs_compile
*c
,
1506 struct brw_vs_prog_data
*prog_data
,
1508 unsigned *final_assembly_size
)
1510 bool start_busy
= false;
1511 float start_time
= 0;
1513 if (unlikely(brw
->perf_debug
)) {
1514 start_busy
= (brw
->batch
.last_bo
&&
1515 drm_intel_bo_busy(brw
->batch
.last_bo
));
1516 start_time
= get_time();
1519 struct brw_shader
*shader
= NULL
;
1521 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1523 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1525 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1526 _mesa_print_ir(shader
->ir
, NULL
);
1529 printf("ARB_vertex_program %d for native vertex shader\n",
1530 c
->vp
->program
.Base
.Id
);
1531 _mesa_print_program(&c
->vp
->program
.Base
);
1535 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1538 prog
->LinkStatus
= false;
1539 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1542 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1548 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
, mem_ctx
,
1549 INTEL_DEBUG
& DEBUG_VS
);
1550 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1551 final_assembly_size
);
1553 if (unlikely(brw
->perf_debug
) && shader
) {
1554 if (shader
->compiled_once
) {
1555 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1557 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1558 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1559 (get_time() - start_time
) * 1000);
1561 shader
->compiled_once
= true;
1569 brw_vec4_prog_data_compare(const struct brw_vec4_prog_data
*a
,
1570 const struct brw_vec4_prog_data
*b
)
1572 /* Compare all the struct up to the pointers. */
1573 if (memcmp(a
, b
, offsetof(struct brw_vec4_prog_data
, param
)))
1576 if (memcmp(a
->param
, b
->param
, a
->nr_params
* sizeof(void *)))
1579 if (memcmp(a
->pull_param
, b
->pull_param
, a
->nr_pull_params
* sizeof(void *)))
1587 brw_vec4_prog_data_free(const struct brw_vec4_prog_data
*prog_data
)
1589 ralloc_free((void *)prog_data
->param
);
1590 ralloc_free((void *)prog_data
->pull_param
);