2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_builder.h"
30 #include "brw_vec4_live_variables.h"
31 #include "brw_dead_control_flow.h"
32 #include "program/prog_parameter.h"
34 #define MAX_INSTRUCTION (1 << 30)
43 memset(this, 0, sizeof(*this));
45 this->file
= BAD_FILE
;
48 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
54 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
55 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
57 this->swizzle
= BRW_SWIZZLE_XYZW
;
59 this->type
= brw_type_for_base_type(type
);
62 /** Generic unset register constructor. */
68 src_reg::src_reg(struct ::brw_reg reg
) :
75 src_reg::src_reg(const dst_reg
®
) :
78 this->reladdr
= reg
.reladdr
;
79 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
85 memset(this, 0, sizeof(*this));
86 this->file
= BAD_FILE
;
87 this->writemask
= WRITEMASK_XYZW
;
95 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
103 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
110 this->type
= brw_type_for_base_type(type
);
111 this->writemask
= writemask
;
114 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
122 this->writemask
= writemask
;
125 dst_reg::dst_reg(struct ::brw_reg reg
) :
128 this->reg_offset
= 0;
129 this->reladdr
= NULL
;
132 dst_reg::dst_reg(const src_reg
®
) :
135 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
136 this->reladdr
= reg
.reladdr
;
140 dst_reg::equals(const dst_reg
&r
) const
142 return (this->backend_reg::equals(r
) &&
143 (reladdr
== r
.reladdr
||
144 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
148 vec4_instruction::is_send_from_grf()
151 case SHADER_OPCODE_SHADER_TIME_ADD
:
152 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
153 case SHADER_OPCODE_UNTYPED_ATOMIC
:
154 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
155 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
156 case SHADER_OPCODE_TYPED_ATOMIC
:
157 case SHADER_OPCODE_TYPED_SURFACE_READ
:
158 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
159 case VEC4_OPCODE_URB_READ
:
160 case TCS_OPCODE_URB_WRITE
:
161 case TCS_OPCODE_RELEASE_INPUT
:
162 case SHADER_OPCODE_BARRIER
:
170 * Returns true if this instruction's sources and destinations cannot
171 * safely be the same register.
173 * In most cases, a register can be written over safely by the same
174 * instruction that is its last use. For a single instruction, the
175 * sources are dereferenced before writing of the destination starts
178 * However, there are a few cases where this can be problematic:
180 * - Virtual opcodes that translate to multiple instructions in the
181 * code generator: if src == dst and one instruction writes the
182 * destination before a later instruction reads the source, then
183 * src will have been clobbered.
185 * The register allocator uses this information to set up conflicts between
186 * GRF sources and the destination.
189 vec4_instruction::has_source_and_destination_hazard() const
192 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
193 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
194 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
202 vec4_instruction::regs_read(unsigned arg
) const
204 if (src
[arg
].file
== BAD_FILE
)
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case SHADER_OPCODE_UNTYPED_ATOMIC
:
210 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
211 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
212 case SHADER_OPCODE_TYPED_ATOMIC
:
213 case SHADER_OPCODE_TYPED_SURFACE_READ
:
214 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
215 case TCS_OPCODE_URB_WRITE
:
216 return arg
== 0 ? mlen
: 1;
218 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
219 return arg
== 1 ? mlen
: 1;
227 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
229 if (devinfo
->gen
== 6 && is_math())
232 if (is_send_from_grf())
235 if (!backend_instruction::can_do_source_mods())
242 vec4_instruction::can_change_types() const
244 return dst
.type
== src
[0].type
&&
245 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
246 (opcode
== BRW_OPCODE_MOV
||
247 (opcode
== BRW_OPCODE_SEL
&&
248 dst
.type
== src
[1].type
&&
249 predicate
!= BRW_PREDICATE_NONE
&&
250 !src
[1].abs
&& !src
[1].negate
));
254 * Returns how many MRFs an opcode will write over.
256 * Note that this is not the 0 or 1 implied writes in an actual gen
257 * instruction -- the generate_* functions generate additional MOVs
261 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
263 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
266 switch (inst
->opcode
) {
267 case SHADER_OPCODE_RCP
:
268 case SHADER_OPCODE_RSQ
:
269 case SHADER_OPCODE_SQRT
:
270 case SHADER_OPCODE_EXP2
:
271 case SHADER_OPCODE_LOG2
:
272 case SHADER_OPCODE_SIN
:
273 case SHADER_OPCODE_COS
:
275 case SHADER_OPCODE_INT_QUOTIENT
:
276 case SHADER_OPCODE_INT_REMAINDER
:
277 case SHADER_OPCODE_POW
:
278 case TCS_OPCODE_THREAD_END
:
280 case VS_OPCODE_URB_WRITE
:
282 case VS_OPCODE_PULL_CONSTANT_LOAD
:
284 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
286 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
288 case GS_OPCODE_URB_WRITE
:
289 case GS_OPCODE_URB_WRITE_ALLOCATE
:
290 case GS_OPCODE_THREAD_END
:
292 case GS_OPCODE_FF_SYNC
:
294 case TCS_OPCODE_URB_WRITE
:
296 case SHADER_OPCODE_SHADER_TIME_ADD
:
298 case SHADER_OPCODE_TEX
:
299 case SHADER_OPCODE_TXL
:
300 case SHADER_OPCODE_TXD
:
301 case SHADER_OPCODE_TXF
:
302 case SHADER_OPCODE_TXF_CMS
:
303 case SHADER_OPCODE_TXF_CMS_W
:
304 case SHADER_OPCODE_TXF_MCS
:
305 case SHADER_OPCODE_TXS
:
306 case SHADER_OPCODE_TG4
:
307 case SHADER_OPCODE_TG4_OFFSET
:
308 case SHADER_OPCODE_SAMPLEINFO
:
309 case VS_OPCODE_GET_BUFFER_SIZE
:
310 return inst
->header_size
;
312 unreachable("not reached");
317 src_reg::equals(const src_reg
&r
) const
319 return (this->backend_reg::equals(r
) &&
320 !reladdr
&& !r
.reladdr
);
324 vec4_visitor::vectorize_mov(bblock_t
*block
, vec4_instruction
*inst
,
325 uint8_t imm
[4], vec4_instruction
*imm_inst
[4],
326 int inst_count
, unsigned writemask
)
332 memcpy(&vf
, imm
, sizeof(vf
));
333 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
334 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
335 mov
->dst
.writemask
= writemask
;
336 inst
->insert_before(block
, mov
);
338 for (int i
= 0; i
< inst_count
; i
++) {
339 imm_inst
[i
]->remove(block
);
346 vec4_visitor::opt_vector_float()
348 bool progress
= false;
350 int last_reg
= -1, last_reg_offset
= -1;
351 enum brw_reg_file last_reg_file
= BAD_FILE
;
353 uint8_t imm
[4] = { 0 };
355 vec4_instruction
*imm_inst
[4];
356 unsigned writemask
= 0;
358 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
359 if (last_reg
!= inst
->dst
.nr
||
360 last_reg_offset
!= inst
->dst
.reg_offset
||
361 last_reg_file
!= inst
->dst
.file
) {
362 progress
|= vectorize_mov(block
, inst
, imm
, imm_inst
, inst_count
,
366 last_reg
= inst
->dst
.nr
;
367 last_reg_offset
= inst
->dst
.reg_offset
;
368 last_reg_file
= inst
->dst
.file
;
370 for (int i
= 0; i
< 4; i
++) {
375 if (inst
->opcode
!= BRW_OPCODE_MOV
||
376 inst
->dst
.writemask
== WRITEMASK_XYZW
||
377 inst
->src
[0].file
!= IMM
||
378 inst
->predicate
!= BRW_PREDICATE_NONE
) {
379 progress
|= vectorize_mov(block
, inst
, imm
, imm_inst
, inst_count
,
386 int vf
= brw_float_to_vf(inst
->src
[0].f
);
390 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
392 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
394 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
396 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
399 writemask
|= inst
->dst
.writemask
;
400 imm_inst
[inst_count
++] = inst
;
404 invalidate_live_intervals();
409 /* Replaces unused channels of a swizzle with channels that are used.
411 * For instance, this pass transforms
413 * mov vgrf4.yz, vgrf5.wxzy
417 * mov vgrf4.yz, vgrf5.xxzx
419 * This eliminates false uses of some channels, letting dead code elimination
420 * remove the instructions that wrote them.
423 vec4_visitor::opt_reduce_swizzle()
425 bool progress
= false;
427 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
428 if (inst
->dst
.file
== BAD_FILE
||
429 inst
->dst
.file
== ARF
||
430 inst
->dst
.file
== FIXED_GRF
||
431 inst
->is_send_from_grf())
436 /* Determine which channels of the sources are read. */
437 switch (inst
->opcode
) {
438 case VEC4_OPCODE_PACK_BYTES
:
440 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
441 * but all four of src1.
443 swizzle
= brw_swizzle_for_size(4);
446 swizzle
= brw_swizzle_for_size(3);
449 swizzle
= brw_swizzle_for_size(2);
452 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
456 /* Update sources' swizzles. */
457 for (int i
= 0; i
< 3; i
++) {
458 if (inst
->src
[i
].file
!= VGRF
&&
459 inst
->src
[i
].file
!= ATTR
&&
460 inst
->src
[i
].file
!= UNIFORM
)
463 const unsigned new_swizzle
=
464 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
465 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
466 inst
->src
[i
].swizzle
= new_swizzle
;
473 invalidate_live_intervals();
479 vec4_visitor::split_uniform_registers()
481 /* Prior to this, uniforms have been in an array sized according to
482 * the number of vector uniforms present, sparsely filled (so an
483 * aggregate results in reg indices being skipped over). Now we're
484 * going to cut those aggregates up so each .nr index is one
485 * vector. The goal is to make elimination of unused uniform
486 * components easier later.
488 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
489 for (int i
= 0 ; i
< 3; i
++) {
490 if (inst
->src
[i
].file
!= UNIFORM
)
493 assert(!inst
->src
[i
].reladdr
);
495 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
496 inst
->src
[i
].reg_offset
= 0;
500 /* Update that everything is now vector-sized. */
501 for (int i
= 0; i
< this->uniforms
; i
++) {
502 this->uniform_size
[i
] = 1;
507 vec4_visitor::pack_uniform_registers()
509 uint8_t chans_used
[this->uniforms
];
510 int new_loc
[this->uniforms
];
511 int new_chan
[this->uniforms
];
513 memset(chans_used
, 0, sizeof(chans_used
));
514 memset(new_loc
, 0, sizeof(new_loc
));
515 memset(new_chan
, 0, sizeof(new_chan
));
517 /* Find which uniform vectors are actually used by the program. We
518 * expect unused vector elements when we've moved array access out
519 * to pull constants, and from some GLSL code generators like wine.
521 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
523 switch (inst
->opcode
) {
524 case VEC4_OPCODE_PACK_BYTES
:
536 readmask
= inst
->dst
.writemask
;
540 for (int i
= 0 ; i
< 3; i
++) {
541 if (inst
->src
[i
].file
!= UNIFORM
)
544 int reg
= inst
->src
[i
].nr
;
545 for (int c
= 0; c
< 4; c
++) {
546 if (!(readmask
& (1 << c
)))
549 chans_used
[reg
] = MAX2(chans_used
[reg
],
550 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
555 int new_uniform_count
= 0;
557 /* Now, figure out a packing of the live uniform vectors into our
560 for (int src
= 0; src
< uniforms
; src
++) {
561 assert(src
< uniform_array_size
);
562 int size
= chans_used
[src
];
568 /* Find the lowest place we can slot this uniform in. */
569 for (dst
= 0; dst
< src
; dst
++) {
570 if (chans_used
[dst
] + size
<= 4)
579 new_chan
[src
] = chans_used
[dst
];
581 /* Move the references to the data */
582 for (int j
= 0; j
< size
; j
++) {
583 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
584 stage_prog_data
->param
[src
* 4 + j
];
587 chans_used
[dst
] += size
;
591 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
594 this->uniforms
= new_uniform_count
;
596 /* Now, update the instructions for our repacked uniforms. */
597 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
598 for (int i
= 0 ; i
< 3; i
++) {
599 int src
= inst
->src
[i
].nr
;
601 if (inst
->src
[i
].file
!= UNIFORM
)
604 inst
->src
[i
].nr
= new_loc
[src
];
605 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
606 new_chan
[src
], new_chan
[src
]);
612 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
614 * While GLSL IR also performs this optimization, we end up with it in
615 * our instruction stream for a couple of reasons. One is that we
616 * sometimes generate silly instructions, for example in array access
617 * where we'll generate "ADD offset, index, base" even if base is 0.
618 * The other is that GLSL IR's constant propagation doesn't track the
619 * components of aggregates, so some VS patterns (initialize matrix to
620 * 0, accumulate in vertex blending factors) end up breaking down to
621 * instructions involving 0.
624 vec4_visitor::opt_algebraic()
626 bool progress
= false;
628 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
629 switch (inst
->opcode
) {
631 if (inst
->src
[0].file
!= IMM
)
634 if (inst
->saturate
) {
635 if (inst
->dst
.type
!= inst
->src
[0].type
)
636 assert(!"unimplemented: saturate mixed types");
638 if (brw_saturate_immediate(inst
->dst
.type
,
639 &inst
->src
[0].as_brw_reg())) {
640 inst
->saturate
= false;
646 case VEC4_OPCODE_UNPACK_UNIFORM
:
647 if (inst
->src
[0].file
!= UNIFORM
) {
648 inst
->opcode
= BRW_OPCODE_MOV
;
654 if (inst
->src
[1].is_zero()) {
655 inst
->opcode
= BRW_OPCODE_MOV
;
656 inst
->src
[1] = src_reg();
662 if (inst
->src
[1].is_zero()) {
663 inst
->opcode
= BRW_OPCODE_MOV
;
664 switch (inst
->src
[0].type
) {
665 case BRW_REGISTER_TYPE_F
:
666 inst
->src
[0] = brw_imm_f(0.0f
);
668 case BRW_REGISTER_TYPE_D
:
669 inst
->src
[0] = brw_imm_d(0);
671 case BRW_REGISTER_TYPE_UD
:
672 inst
->src
[0] = brw_imm_ud(0u);
675 unreachable("not reached");
677 inst
->src
[1] = src_reg();
679 } else if (inst
->src
[1].is_one()) {
680 inst
->opcode
= BRW_OPCODE_MOV
;
681 inst
->src
[1] = src_reg();
683 } else if (inst
->src
[1].is_negative_one()) {
684 inst
->opcode
= BRW_OPCODE_MOV
;
685 inst
->src
[0].negate
= !inst
->src
[0].negate
;
686 inst
->src
[1] = src_reg();
691 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
693 inst
->src
[0].negate
&&
694 inst
->src
[1].is_zero()) {
695 inst
->src
[0].abs
= false;
696 inst
->src
[0].negate
= false;
697 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
702 case SHADER_OPCODE_RCP
: {
703 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
704 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
705 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
706 inst
->opcode
= SHADER_OPCODE_RSQ
;
707 inst
->src
[0] = prev
->src
[0];
713 case SHADER_OPCODE_BROADCAST
:
714 if (is_uniform(inst
->src
[0]) ||
715 inst
->src
[1].is_zero()) {
716 inst
->opcode
= BRW_OPCODE_MOV
;
717 inst
->src
[1] = src_reg();
718 inst
->force_writemask_all
= true;
729 invalidate_live_intervals();
735 * Only a limited number of hardware registers may be used for push
736 * constants, so this turns access to the overflowed constants into
740 vec4_visitor::move_push_constants_to_pull_constants()
742 int pull_constant_loc
[this->uniforms
];
744 /* Only allow 32 registers (256 uniform components) as push constants,
745 * which is the limit on gen6.
747 * If changing this value, note the limitation about total_regs in
750 int max_uniform_components
= 32 * 8;
751 if (this->uniforms
* 4 <= max_uniform_components
)
754 /* Make some sort of choice as to which uniforms get sent to pull
755 * constants. We could potentially do something clever here like
756 * look for the most infrequently used uniform vec4s, but leave
759 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
760 pull_constant_loc
[i
/ 4] = -1;
762 if (i
>= max_uniform_components
) {
763 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
765 /* Try to find an existing copy of this uniform in the pull
766 * constants if it was part of an array access already.
768 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
771 for (matches
= 0; matches
< 4; matches
++) {
772 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
777 pull_constant_loc
[i
/ 4] = j
/ 4;
782 if (pull_constant_loc
[i
/ 4] == -1) {
783 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
784 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
786 for (int j
= 0; j
< 4; j
++) {
787 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
794 /* Now actually rewrite usage of the things we've moved to pull
797 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
798 for (int i
= 0 ; i
< 3; i
++) {
799 if (inst
->src
[i
].file
!= UNIFORM
||
800 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
803 int uniform
= inst
->src
[i
].nr
;
805 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
807 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
808 pull_constant_loc
[uniform
]);
810 inst
->src
[i
].file
= temp
.file
;
811 inst
->src
[i
].nr
= temp
.nr
;
812 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
813 inst
->src
[i
].reladdr
= NULL
;
817 /* Repack push constants to remove the now-unused ones. */
818 pack_uniform_registers();
821 /* Conditions for which we want to avoid setting the dependency control bits */
823 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
825 #define IS_DWORD(reg) \
826 (reg.type == BRW_REGISTER_TYPE_UD || \
827 reg.type == BRW_REGISTER_TYPE_D)
829 /* "When source or destination datatype is 64b or operation is integer DWord
830 * multiply, DepCtrl must not be used."
831 * May apply to future SoCs as well.
833 if (devinfo
->is_cherryview
) {
834 if (inst
->opcode
== BRW_OPCODE_MUL
&&
835 IS_DWORD(inst
->src
[0]) &&
836 IS_DWORD(inst
->src
[1]))
841 if (devinfo
->gen
>= 8) {
842 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
848 * In the presence of send messages, totally interrupt dependency
849 * control. They're long enough that the chance of dependency
850 * control around them just doesn't matter.
853 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
854 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
855 * completes the scoreboard clear must have a non-zero execution mask. This
856 * means, if any kind of predication can change the execution mask or channel
857 * enable of the last instruction, the optimization must be avoided. This is
858 * to avoid instructions being shot down the pipeline when no writes are
862 * Dependency control does not work well over math instructions.
863 * NB: Discovered empirically
865 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
869 * Sets the dependency control fields on instructions after register
870 * allocation and before the generator is run.
872 * When you have a sequence of instructions like:
874 * DP4 temp.x vertex uniform[0]
875 * DP4 temp.y vertex uniform[0]
876 * DP4 temp.z vertex uniform[0]
877 * DP4 temp.w vertex uniform[0]
879 * The hardware doesn't know that it can actually run the later instructions
880 * while the previous ones are in flight, producing stalls. However, we have
881 * manual fields we can set in the instructions that let it do so.
884 vec4_visitor::opt_set_dependency_control()
886 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
887 uint8_t grf_channels_written
[BRW_MAX_GRF
];
888 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
889 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
891 assert(prog_data
->total_grf
||
892 !"Must be called after register allocation");
894 foreach_block (block
, cfg
) {
895 memset(last_grf_write
, 0, sizeof(last_grf_write
));
896 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
898 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
899 /* If we read from a register that we were doing dependency control
900 * on, don't do dependency control across the read.
902 for (int i
= 0; i
< 3; i
++) {
903 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
904 if (inst
->src
[i
].file
== VGRF
) {
905 last_grf_write
[reg
] = NULL
;
906 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
907 memset(last_grf_write
, 0, sizeof(last_grf_write
));
910 assert(inst
->src
[i
].file
!= MRF
);
913 if (is_dep_ctrl_unsafe(inst
)) {
914 memset(last_grf_write
, 0, sizeof(last_grf_write
));
915 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
919 /* Now, see if we can do dependency control for this instruction
920 * against a previous one writing to its destination.
922 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
923 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
924 if (last_grf_write
[reg
] &&
925 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
926 last_grf_write
[reg
]->no_dd_clear
= true;
927 inst
->no_dd_check
= true;
929 grf_channels_written
[reg
] = 0;
932 last_grf_write
[reg
] = inst
;
933 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
934 } else if (inst
->dst
.file
== MRF
) {
935 if (last_mrf_write
[reg
] &&
936 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
937 last_mrf_write
[reg
]->no_dd_clear
= true;
938 inst
->no_dd_check
= true;
940 mrf_channels_written
[reg
] = 0;
943 last_mrf_write
[reg
] = inst
;
944 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
951 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
956 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
957 * or writemasking are not allowed.
959 if (devinfo
->gen
== 6 && is_math() &&
960 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
963 /* If this instruction sets anything not referenced by swizzle, then we'd
964 * totally break it when we reswizzle.
966 if (dst
.writemask
& ~swizzle_mask
)
972 for (int i
= 0; i
< 3; i
++) {
973 if (src
[i
].is_accumulator())
981 * For any channels in the swizzle's source that were populated by this
982 * instruction, rewrite the instruction to put the appropriate result directly
985 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
988 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
990 /* Destination write mask doesn't correspond to source swizzle for the dot
991 * product and pack_bytes instructions.
993 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
994 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
995 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
996 for (int i
= 0; i
< 3; i
++) {
997 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1000 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1004 /* Apply the specified swizzle and writemask to the original mask of
1005 * written components.
1007 dst
.writemask
= dst_writemask
&
1008 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1012 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1013 * just written and then MOVed into another reg and making the original write
1014 * of the GRF write directly to the final destination instead.
1017 vec4_visitor::opt_register_coalesce()
1019 bool progress
= false;
1022 calculate_live_intervals();
1024 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1028 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1029 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1031 inst
->src
[0].file
!= VGRF
||
1032 inst
->dst
.type
!= inst
->src
[0].type
||
1033 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1036 /* Remove no-op MOVs */
1037 if (inst
->dst
.file
== inst
->src
[0].file
&&
1038 inst
->dst
.nr
== inst
->src
[0].nr
&&
1039 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1040 bool is_nop_mov
= true;
1042 for (unsigned c
= 0; c
< 4; c
++) {
1043 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1046 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1053 inst
->remove(block
);
1059 bool to_mrf
= (inst
->dst
.file
== MRF
);
1061 /* Can't coalesce this GRF if someone else was going to
1064 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1067 /* We need to check interference with the final destination between this
1068 * instruction and the earliest instruction involved in writing the GRF
1069 * we're eliminating. To do that, keep track of which of our source
1070 * channels we've seen initialized.
1072 const unsigned chans_needed
=
1073 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1074 inst
->dst
.writemask
);
1075 unsigned chans_remaining
= chans_needed
;
1077 /* Now walk up the instruction stream trying to see if we can rewrite
1078 * everything writing to the temporary to write into the destination
1081 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1082 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1084 _scan_inst
= scan_inst
;
1086 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1087 /* Found something writing to the reg we want to coalesce away. */
1089 /* SEND instructions can't have MRF as a destination. */
1090 if (scan_inst
->mlen
)
1093 if (devinfo
->gen
== 6) {
1094 /* gen6 math instructions must have the destination be
1095 * VGRF, so no compute-to-MRF for them.
1097 if (scan_inst
->is_math()) {
1103 /* This doesn't handle saturation on the instruction we
1104 * want to coalesce away if the register types do not match.
1105 * But if scan_inst is a non type-converting 'mov', we can fix
1108 if (inst
->saturate
&&
1109 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1110 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1111 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1114 /* If we can't handle the swizzle, bail. */
1115 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1116 inst
->src
[0].swizzle
,
1121 /* This doesn't handle coalescing of multiple registers. */
1122 if (scan_inst
->regs_written
> 1)
1125 /* Mark which channels we found unconditional writes for. */
1126 if (!scan_inst
->predicate
)
1127 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1129 if (chans_remaining
== 0)
1133 /* You can't read from an MRF, so if someone else reads our MRF's
1134 * source GRF that we wanted to rewrite, that stops us. If it's a
1135 * GRF we're trying to coalesce to, we don't actually handle
1136 * rewriting sources so bail in that case as well.
1138 bool interfered
= false;
1139 for (int i
= 0; i
< 3; i
++) {
1140 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1141 scan_inst
->regs_read(i
)))
1147 /* If somebody else writes the same channels of our destination here,
1148 * we can't coalesce before that.
1150 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1151 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1155 /* Check for reads of the register we're trying to coalesce into. We
1156 * can't go rewriting instructions above that to put some other value
1157 * in the register instead.
1159 if (to_mrf
&& scan_inst
->mlen
> 0) {
1160 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1161 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1165 for (int i
= 0; i
< 3; i
++) {
1166 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1167 scan_inst
->regs_read(i
)))
1175 if (chans_remaining
== 0) {
1176 /* If we've made it here, we have an MOV we want to coalesce out, and
1177 * a scan_inst pointing to the earliest instruction involved in
1178 * computing the value. Now go rewrite the instruction stream
1181 vec4_instruction
*scan_inst
= _scan_inst
;
1182 while (scan_inst
!= inst
) {
1183 if (scan_inst
->dst
.file
== VGRF
&&
1184 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1185 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1186 scan_inst
->reswizzle(inst
->dst
.writemask
,
1187 inst
->src
[0].swizzle
);
1188 scan_inst
->dst
.file
= inst
->dst
.file
;
1189 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1190 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1191 if (inst
->saturate
&&
1192 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1193 /* If we have reached this point, scan_inst is a non
1194 * type-converting 'mov' and we can modify its register types
1195 * to match the ones in inst. Otherwise, we could have an
1196 * incorrect saturation result.
1198 scan_inst
->dst
.type
= inst
->dst
.type
;
1199 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1201 scan_inst
->saturate
|= inst
->saturate
;
1203 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1205 inst
->remove(block
);
1211 invalidate_live_intervals();
1217 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1218 * flow. We could probably do better here with some form of divergence
1222 vec4_visitor::eliminate_find_live_channel()
1224 bool progress
= false;
1227 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1228 switch (inst
->opcode
) {
1234 case BRW_OPCODE_ENDIF
:
1235 case BRW_OPCODE_WHILE
:
1239 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1241 inst
->opcode
= BRW_OPCODE_MOV
;
1242 inst
->src
[0] = brw_imm_d(0);
1243 inst
->force_writemask_all
= true;
1257 * Splits virtual GRFs requesting more than one contiguous physical register.
1259 * We initially create large virtual GRFs for temporary structures, arrays,
1260 * and matrices, so that the dereference visitor functions can add reg_offsets
1261 * to work their way down to the actual member being accessed. But when it
1262 * comes to optimization, we'd like to treat each register as individual
1263 * storage if possible.
1265 * So far, the only thing that might prevent splitting is a send message from
1269 vec4_visitor::split_virtual_grfs()
1271 int num_vars
= this->alloc
.count
;
1272 int new_virtual_grf
[num_vars
];
1273 bool split_grf
[num_vars
];
1275 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1277 /* Try to split anything > 0 sized. */
1278 for (int i
= 0; i
< num_vars
; i
++) {
1279 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1282 /* Check that the instructions are compatible with the registers we're trying
1285 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1286 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1287 split_grf
[inst
->dst
.nr
] = false;
1289 for (int i
= 0; i
< 3; i
++) {
1290 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1291 split_grf
[inst
->src
[i
].nr
] = false;
1295 /* Allocate new space for split regs. Note that the virtual
1296 * numbers will be contiguous.
1298 for (int i
= 0; i
< num_vars
; i
++) {
1302 new_virtual_grf
[i
] = alloc
.allocate(1);
1303 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1304 unsigned reg
= alloc
.allocate(1);
1305 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1308 this->alloc
.sizes
[i
] = 1;
1311 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1312 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1313 inst
->dst
.reg_offset
!= 0) {
1314 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1315 inst
->dst
.reg_offset
- 1);
1316 inst
->dst
.reg_offset
= 0;
1318 for (int i
= 0; i
< 3; i
++) {
1319 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1320 inst
->src
[i
].reg_offset
!= 0) {
1321 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1322 inst
->src
[i
].reg_offset
- 1);
1323 inst
->src
[i
].reg_offset
= 0;
1327 invalidate_live_intervals();
1331 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1333 dump_instruction(be_inst
, stderr
);
1337 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1339 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1341 if (inst
->predicate
) {
1342 fprintf(file
, "(%cf0.%d%s) ",
1343 inst
->predicate_inverse
? '-' : '+',
1345 pred_ctrl_align16
[inst
->predicate
]);
1348 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1350 fprintf(file
, ".sat");
1351 if (inst
->conditional_mod
) {
1352 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1353 if (!inst
->predicate
&&
1354 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1355 inst
->opcode
!= BRW_OPCODE_IF
&&
1356 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1357 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1362 switch (inst
->dst
.file
) {
1364 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1367 fprintf(file
, "g%d", inst
->dst
.nr
);
1370 fprintf(file
, "m%d", inst
->dst
.nr
);
1373 switch (inst
->dst
.nr
) {
1375 fprintf(file
, "null");
1377 case BRW_ARF_ADDRESS
:
1378 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1380 case BRW_ARF_ACCUMULATOR
:
1381 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1384 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1387 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1390 if (inst
->dst
.subnr
)
1391 fprintf(file
, "+%d", inst
->dst
.subnr
);
1394 fprintf(file
, "(null)");
1399 unreachable("not reached");
1401 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1403 if (inst
->dst
.writemask
& 1)
1405 if (inst
->dst
.writemask
& 2)
1407 if (inst
->dst
.writemask
& 4)
1409 if (inst
->dst
.writemask
& 8)
1412 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1414 if (inst
->src
[0].file
!= BAD_FILE
)
1415 fprintf(file
, ", ");
1417 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1418 if (inst
->src
[i
].negate
)
1420 if (inst
->src
[i
].abs
)
1422 switch (inst
->src
[i
].file
) {
1424 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1427 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1430 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1433 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1436 switch (inst
->src
[i
].type
) {
1437 case BRW_REGISTER_TYPE_F
:
1438 fprintf(file
, "%fF", inst
->src
[i
].f
);
1440 case BRW_REGISTER_TYPE_D
:
1441 fprintf(file
, "%dD", inst
->src
[i
].d
);
1443 case BRW_REGISTER_TYPE_UD
:
1444 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1446 case BRW_REGISTER_TYPE_VF
:
1447 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1448 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1449 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1450 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1451 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1454 fprintf(file
, "???");
1459 switch (inst
->src
[i
].nr
) {
1461 fprintf(file
, "null");
1463 case BRW_ARF_ADDRESS
:
1464 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1466 case BRW_ARF_ACCUMULATOR
:
1467 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1470 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1473 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1476 if (inst
->src
[i
].subnr
)
1477 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1480 fprintf(file
, "(null)");
1483 unreachable("not reached");
1486 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1487 if (inst
->src
[i
].reg_offset
!= 0 &&
1488 inst
->src
[i
].file
== VGRF
&&
1489 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1490 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1492 if (inst
->src
[i
].file
!= IMM
) {
1493 static const char *chans
[4] = {"x", "y", "z", "w"};
1495 for (int c
= 0; c
< 4; c
++) {
1496 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1500 if (inst
->src
[i
].abs
)
1503 if (inst
->src
[i
].file
!= IMM
) {
1504 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1507 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1508 fprintf(file
, ", ");
1511 if (inst
->force_writemask_all
)
1512 fprintf(file
, " NoMask");
1514 fprintf(file
, "\n");
1518 static inline struct brw_reg
1519 attribute_to_hw_reg(int attr
, bool interleaved
)
1522 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1524 return brw_vec8_grf(attr
, 0);
1529 * Replace each register of type ATTR in this->instructions with a reference
1530 * to a fixed HW register.
1532 * If interleaved is true, then each attribute takes up half a register, with
1533 * register N containing attribute 2*N in its first half and attribute 2*N+1
1534 * in its second half (this corresponds to the payload setup used by geometry
1535 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1536 * false, then each attribute takes up a whole register, with register N
1537 * containing attribute N (this corresponds to the payload setup used by
1538 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1541 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1544 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1545 for (int i
= 0; i
< 3; i
++) {
1546 if (inst
->src
[i
].file
!= ATTR
)
1549 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1551 /* All attributes used in the shader need to have been assigned a
1552 * hardware register by the caller
1556 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1557 reg
.swizzle
= inst
->src
[i
].swizzle
;
1558 reg
.type
= inst
->src
[i
].type
;
1559 if (inst
->src
[i
].abs
)
1561 if (inst
->src
[i
].negate
)
1570 vec4_vs_visitor::setup_attributes(int payload_reg
)
1573 int attribute_map
[VERT_ATTRIB_MAX
+ 2];
1574 memset(attribute_map
, 0, sizeof(attribute_map
));
1577 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1578 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1579 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1584 /* VertexID is stored by the VF as the last vertex element, but we
1585 * don't represent it with a flag in inputs_read, so we call it
1588 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1589 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) {
1590 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1594 if (vs_prog_data
->uses_drawid
) {
1595 attribute_map
[VERT_ATTRIB_MAX
+ 1] = payload_reg
+ nr_attributes
;
1599 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1601 return payload_reg
+ vs_prog_data
->nr_attributes
;
1605 vec4_visitor::setup_uniforms(int reg
)
1607 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1609 /* The pre-gen6 VS requires that some push constants get loaded no
1610 * matter what, or the GPU would hang.
1612 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1613 assert(this->uniforms
< this->uniform_array_size
);
1615 stage_prog_data
->param
=
1616 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1617 for (unsigned int i
= 0; i
< 4; i
++) {
1618 unsigned int slot
= this->uniforms
* 4 + i
;
1619 static gl_constant_value zero
= { 0.0 };
1620 stage_prog_data
->param
[slot
] = &zero
;
1626 reg
+= ALIGN(uniforms
, 2) / 2;
1629 stage_prog_data
->nr_params
= this->uniforms
* 4;
1631 prog_data
->base
.curb_read_length
=
1632 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1638 vec4_vs_visitor::setup_payload(void)
1642 /* The payload always contains important data in g0, which contains
1643 * the URB handles that are passed on to the URB write at the end
1644 * of the thread. So, we always start push constants at g1.
1648 reg
= setup_uniforms(reg
);
1650 reg
= setup_attributes(reg
);
1652 this->first_non_payload_grf
= reg
;
1656 vec4_visitor::lower_minmax()
1658 assert(devinfo
->gen
< 6);
1660 bool progress
= false;
1662 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1663 const vec4_builder
ibld(this, block
, inst
);
1665 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1666 inst
->predicate
== BRW_PREDICATE_NONE
) {
1667 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1668 * the original SEL.L/GE instruction
1670 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1671 inst
->conditional_mod
);
1672 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1673 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1680 invalidate_live_intervals();
1686 vec4_visitor::get_timestamp()
1688 assert(devinfo
->gen
>= 7);
1690 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1695 BRW_REGISTER_TYPE_UD
,
1696 BRW_VERTICAL_STRIDE_0
,
1698 BRW_HORIZONTAL_STRIDE_4
,
1702 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1704 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1705 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1706 * even if it's not enabled in the dispatch.
1708 mov
->force_writemask_all
= true;
1710 return src_reg(dst
);
1714 vec4_visitor::emit_shader_time_begin()
1716 current_annotation
= "shader time start";
1717 shader_start_time
= get_timestamp();
1721 vec4_visitor::emit_shader_time_end()
1723 current_annotation
= "shader time end";
1724 src_reg shader_end_time
= get_timestamp();
1727 /* Check that there weren't any timestamp reset events (assuming these
1728 * were the only two timestamp reads that happened).
1730 src_reg reset_end
= shader_end_time
;
1731 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1732 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1733 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1735 emit(IF(BRW_PREDICATE_NORMAL
));
1737 /* Take the current timestamp and get the delta. */
1738 shader_start_time
.negate
= true;
1739 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1740 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1742 /* If there were no instructions between the two timestamp gets, the diff
1743 * is 2 cycles. Remove that overhead, so I can forget about that when
1744 * trying to determine the time taken for single instructions.
1746 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1748 emit_shader_time_write(0, src_reg(diff
));
1749 emit_shader_time_write(1, brw_imm_ud(1u));
1750 emit(BRW_OPCODE_ELSE
);
1751 emit_shader_time_write(2, brw_imm_ud(1u));
1752 emit(BRW_OPCODE_ENDIF
);
1756 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1759 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1761 dst_reg offset
= dst
;
1765 offset
.type
= BRW_REGISTER_TYPE_UD
;
1766 int index
= shader_time_index
* 3 + shader_time_subindex
;
1767 emit(MOV(offset
, brw_imm_d(index
* SHADER_TIME_STRIDE
)));
1769 time
.type
= BRW_REGISTER_TYPE_UD
;
1770 emit(MOV(time
, value
));
1772 vec4_instruction
*inst
=
1773 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1778 vec4_visitor::convert_to_hw_regs()
1780 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1781 for (int i
= 0; i
< 3; i
++) {
1782 struct src_reg
&src
= inst
->src
[i
];
1786 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1787 reg
.type
= src
.type
;
1788 reg
.swizzle
= src
.swizzle
;
1790 reg
.negate
= src
.negate
;
1794 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1795 (src
.nr
+ src
.reg_offset
) / 2,
1796 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1798 reg
.type
= src
.type
;
1799 reg
.swizzle
= src
.swizzle
;
1801 reg
.negate
= src
.negate
;
1803 /* This should have been moved to pull constants. */
1804 assert(!src
.reladdr
);
1813 /* Probably unused. */
1814 reg
= brw_null_reg();
1819 unreachable("not reached");
1825 if (inst
->is_3src()) {
1826 /* 3-src instructions with scalar sources support arbitrary subnr,
1827 * but don't actually use swizzles. Convert swizzle into subnr.
1829 for (int i
= 0; i
< 3; i
++) {
1830 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
) {
1831 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
1832 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
1837 dst_reg
&dst
= inst
->dst
;
1840 switch (inst
->dst
.file
) {
1842 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1843 reg
.type
= dst
.type
;
1844 reg
.writemask
= dst
.writemask
;
1848 assert(((dst
.nr
+ dst
.reg_offset
) & ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
1849 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1850 reg
.type
= dst
.type
;
1851 reg
.writemask
= dst
.writemask
;
1856 reg
= dst
.as_brw_reg();
1860 reg
= brw_null_reg();
1866 unreachable("not reached");
1876 if (shader_time_index
>= 0)
1877 emit_shader_time_begin();
1890 /* Before any optimization, push array accesses out to scratch
1891 * space where we need them to be. This pass may allocate new
1892 * virtual GRFs, so we want to do it early. It also makes sure
1893 * that we have reladdr computations available for CSE, since we'll
1894 * often do repeated subexpressions for those.
1896 move_grf_array_access_to_scratch();
1897 move_uniform_array_access_to_pull_constants();
1899 pack_uniform_registers();
1900 move_push_constants_to_pull_constants();
1901 split_virtual_grfs();
1903 #define OPT(pass, args...) ({ \
1905 bool this_progress = pass(args); \
1907 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1908 char filename[64]; \
1909 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1910 stage_abbrev, nir->info.name, iteration, pass_num); \
1912 backend_shader::dump_instructions(filename); \
1915 progress = progress || this_progress; \
1920 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1922 snprintf(filename
, 64, "%s-%s-00-00-start",
1923 stage_abbrev
, nir
->info
.name
);
1925 backend_shader::dump_instructions(filename
);
1936 OPT(opt_predicated_break
, this);
1937 OPT(opt_reduce_swizzle
);
1938 OPT(dead_code_eliminate
);
1939 OPT(dead_control_flow_eliminate
, this);
1940 OPT(opt_copy_propagation
);
1941 OPT(opt_cmod_propagation
);
1944 OPT(opt_register_coalesce
);
1945 OPT(eliminate_find_live_channel
);
1950 if (OPT(opt_vector_float
)) {
1952 OPT(opt_copy_propagation
, false);
1953 OPT(opt_copy_propagation
, true);
1954 OPT(dead_code_eliminate
);
1957 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
1958 OPT(opt_cmod_propagation
);
1960 OPT(opt_copy_propagation
);
1961 OPT(dead_code_eliminate
);
1969 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1970 /* Debug of register spilling: Go spill everything. */
1971 const int grf_count
= alloc
.count
;
1972 float spill_costs
[alloc
.count
];
1973 bool no_spill
[alloc
.count
];
1974 evaluate_spill_costs(spill_costs
, no_spill
);
1975 for (int i
= 0; i
< grf_count
; i
++) {
1982 bool allocated_without_spills
= reg_allocate();
1984 if (!allocated_without_spills
) {
1985 compiler
->shader_perf_log(log_data
,
1986 "%s shader triggered register spilling. "
1987 "Try reducing the number of live vec4 values "
1988 "to improve performance.\n",
1991 while (!reg_allocate()) {
1997 opt_schedule_instructions();
1999 opt_set_dependency_control();
2001 convert_to_hw_regs();
2003 if (last_scratch
> 0) {
2004 prog_data
->base
.total_scratch
=
2005 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2011 } /* namespace brw */
2016 * Compile a vertex shader.
2018 * Returns the final assembly and the program's size.
2021 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2023 const struct brw_vs_prog_key
*key
,
2024 struct brw_vs_prog_data
*prog_data
,
2025 const nir_shader
*src_shader
,
2026 gl_clip_plane
*clip_planes
,
2027 bool use_legacy_snorm_formula
,
2028 int shader_time_index
,
2029 unsigned *final_assembly_size
,
2032 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2033 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2034 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
2036 brw_nir_lower_vs_inputs(shader
, compiler
->devinfo
, is_scalar
,
2037 use_legacy_snorm_formula
, key
->gl_attrib_wa_flags
);
2038 brw_nir_lower_vue_outputs(shader
, is_scalar
);
2039 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, is_scalar
);
2041 const unsigned *assembly
= NULL
;
2043 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
2045 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2046 * incoming vertex attribute. So, add an extra slot.
2048 if (shader
->info
.system_values_read
&
2049 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
2050 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2051 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2052 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2056 /* gl_DrawID has its very own vec4 */
2057 if (shader
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2061 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2062 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2063 * vec4 mode, the hardware appears to wedge unless we read something.
2066 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
2068 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
2070 prog_data
->nr_attributes
= nr_attributes
;
2072 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2073 * (overwriting the original contents), we need to make sure the size is
2074 * the larger of the two.
2076 const unsigned vue_entries
=
2077 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2079 if (compiler
->devinfo
->gen
== 6)
2080 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2082 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2085 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2087 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2088 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2089 shader
, 8, shader_time_index
);
2090 if (!v
.run_vs(clip_planes
)) {
2092 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2097 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2098 &prog_data
->base
.base
, v
.promoted_constants
,
2099 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2100 if (INTEL_DEBUG
& DEBUG_VS
) {
2101 const char *debug_name
=
2102 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2103 shader
->info
.label
? shader
->info
.label
: "unnamed",
2106 g
.enable_debug(debug_name
);
2108 g
.generate_code(v
.cfg
, 8);
2109 assembly
= g
.get_assembly(final_assembly_size
);
2113 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2115 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2116 shader
, clip_planes
, mem_ctx
,
2117 shader_time_index
, use_legacy_snorm_formula
);
2120 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2125 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2126 shader
, &prog_data
->base
, v
.cfg
,
2127 final_assembly_size
);