2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
115 src_reg::src_reg(struct brw_reg reg
)
120 this->fixed_hw_reg
= reg
;
121 this->type
= reg
.type
;
124 src_reg::src_reg(dst_reg reg
)
128 this->file
= reg
.file
;
130 this->reg_offset
= reg
.reg_offset
;
131 this->type
= reg
.type
;
132 this->reladdr
= reg
.reladdr
;
133 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 for (int i
= 0; i
< 4; i
++) {
140 if (!(reg
.writemask
& (1 << i
)))
143 swizzles
[next_chan
++] = last
= i
;
146 for (; next_chan
< 4; next_chan
++) {
147 swizzles
[next_chan
] = last
;
150 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
151 swizzles
[2], swizzles
[3]);
157 memset(this, 0, sizeof(*this));
158 this->file
= BAD_FILE
;
159 this->writemask
= WRITEMASK_XYZW
;
167 dst_reg::dst_reg(register_file file
, int reg
)
175 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
182 this->type
= brw_type_for_base_type(type
);
183 this->writemask
= writemask
;
186 dst_reg::dst_reg(struct brw_reg reg
)
191 this->fixed_hw_reg
= reg
;
192 this->type
= reg
.type
;
195 dst_reg::dst_reg(src_reg reg
)
199 this->file
= reg
.file
;
201 this->reg_offset
= reg
.reg_offset
;
202 this->type
= reg
.type
;
203 /* How should we do writemasking when converting from a src_reg? It seems
204 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
205 * what about for src.wx? Just special-case src.xxxx for now.
207 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
208 this->writemask
= WRITEMASK_X
;
210 this->writemask
= WRITEMASK_XYZW
;
211 this->reladdr
= reg
.reladdr
;
212 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
216 vec4_instruction::is_send_from_grf()
219 case SHADER_OPCODE_SHADER_TIME_ADD
:
220 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
228 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
230 if (brw
->gen
== 6 && inst
->is_math())
233 if (inst
->is_send_from_grf())
236 if (!inst
->can_do_source_mods())
243 * Returns how many MRFs an opcode will write over.
245 * Note that this is not the 0 or 1 implied writes in an actual gen
246 * instruction -- the generate_* functions generate additional MOVs
250 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
255 switch (inst
->opcode
) {
256 case SHADER_OPCODE_RCP
:
257 case SHADER_OPCODE_RSQ
:
258 case SHADER_OPCODE_SQRT
:
259 case SHADER_OPCODE_EXP2
:
260 case SHADER_OPCODE_LOG2
:
261 case SHADER_OPCODE_SIN
:
262 case SHADER_OPCODE_COS
:
264 case SHADER_OPCODE_INT_QUOTIENT
:
265 case SHADER_OPCODE_INT_REMAINDER
:
266 case SHADER_OPCODE_POW
:
268 case VS_OPCODE_URB_WRITE
:
270 case VS_OPCODE_PULL_CONSTANT_LOAD
:
272 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
274 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
276 case GS_OPCODE_URB_WRITE
:
277 case GS_OPCODE_THREAD_END
:
279 case SHADER_OPCODE_SHADER_TIME_ADD
:
281 case SHADER_OPCODE_TEX
:
282 case SHADER_OPCODE_TXL
:
283 case SHADER_OPCODE_TXD
:
284 case SHADER_OPCODE_TXF
:
285 case SHADER_OPCODE_TXF_CMS
:
286 case SHADER_OPCODE_TXF_MCS
:
287 case SHADER_OPCODE_TXS
:
288 case SHADER_OPCODE_TG4
:
289 case SHADER_OPCODE_TG4_OFFSET
:
290 return inst
->header_present
? 1 : 0;
291 case SHADER_OPCODE_UNTYPED_ATOMIC
:
292 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
295 assert(!"not reached");
301 src_reg::equals(src_reg
*r
)
303 return (file
== r
->file
&&
305 reg_offset
== r
->reg_offset
&&
307 negate
== r
->negate
&&
309 swizzle
== r
->swizzle
&&
310 !reladdr
&& !r
->reladdr
&&
311 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
312 sizeof(fixed_hw_reg
)) == 0 &&
317 * Must be called after calculate_live_intervales() to remove unused
318 * writes to registers -- register allocation will fail otherwise
319 * because something deffed but not used won't be considered to
320 * interfere with other regs.
323 vec4_visitor::dead_code_eliminate()
325 bool progress
= false;
328 calculate_live_intervals();
330 foreach_list_safe(node
, &this->instructions
) {
331 vec4_instruction
*inst
= (vec4_instruction
*)node
;
333 if (inst
->dst
.file
== GRF
&& !inst
->has_side_effects()) {
334 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
335 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
336 /* Don't dead code eliminate instructions that write to the
337 * accumulator as a side-effect. Instead just set the destination
338 * to the null register to free it.
340 switch (inst
->opcode
) {
341 case BRW_OPCODE_ADDC
:
342 case BRW_OPCODE_SUBB
:
343 case BRW_OPCODE_MACH
:
344 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
358 invalidate_live_intervals();
364 vec4_visitor::split_uniform_registers()
366 /* Prior to this, uniforms have been in an array sized according to
367 * the number of vector uniforms present, sparsely filled (so an
368 * aggregate results in reg indices being skipped over). Now we're
369 * going to cut those aggregates up so each .reg index is one
370 * vector. The goal is to make elimination of unused uniform
371 * components easier later.
373 foreach_list(node
, &this->instructions
) {
374 vec4_instruction
*inst
= (vec4_instruction
*)node
;
376 for (int i
= 0 ; i
< 3; i
++) {
377 if (inst
->src
[i
].file
!= UNIFORM
)
380 assert(!inst
->src
[i
].reladdr
);
382 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
383 inst
->src
[i
].reg_offset
= 0;
387 /* Update that everything is now vector-sized. */
388 for (int i
= 0; i
< this->uniforms
; i
++) {
389 this->uniform_size
[i
] = 1;
394 vec4_visitor::pack_uniform_registers()
396 bool uniform_used
[this->uniforms
];
397 int new_loc
[this->uniforms
];
398 int new_chan
[this->uniforms
];
400 memset(uniform_used
, 0, sizeof(uniform_used
));
401 memset(new_loc
, 0, sizeof(new_loc
));
402 memset(new_chan
, 0, sizeof(new_chan
));
404 /* Find which uniform vectors are actually used by the program. We
405 * expect unused vector elements when we've moved array access out
406 * to pull constants, and from some GLSL code generators like wine.
408 foreach_list(node
, &this->instructions
) {
409 vec4_instruction
*inst
= (vec4_instruction
*)node
;
411 for (int i
= 0 ; i
< 3; i
++) {
412 if (inst
->src
[i
].file
!= UNIFORM
)
415 uniform_used
[inst
->src
[i
].reg
] = true;
419 int new_uniform_count
= 0;
421 /* Now, figure out a packing of the live uniform vectors into our
424 for (int src
= 0; src
< uniforms
; src
++) {
425 assert(src
< uniform_array_size
);
426 int size
= this->uniform_vector_size
[src
];
428 if (!uniform_used
[src
]) {
429 this->uniform_vector_size
[src
] = 0;
434 /* Find the lowest place we can slot this uniform in. */
435 for (dst
= 0; dst
< src
; dst
++) {
436 if (this->uniform_vector_size
[dst
] + size
<= 4)
445 new_chan
[src
] = this->uniform_vector_size
[dst
];
447 /* Move the references to the data */
448 for (int j
= 0; j
< size
; j
++) {
449 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
450 stage_prog_data
->param
[src
* 4 + j
];
453 this->uniform_vector_size
[dst
] += size
;
454 this->uniform_vector_size
[src
] = 0;
457 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
460 this->uniforms
= new_uniform_count
;
462 /* Now, update the instructions for our repacked uniforms. */
463 foreach_list(node
, &this->instructions
) {
464 vec4_instruction
*inst
= (vec4_instruction
*)node
;
466 for (int i
= 0 ; i
< 3; i
++) {
467 int src
= inst
->src
[i
].reg
;
469 if (inst
->src
[i
].file
!= UNIFORM
)
472 inst
->src
[i
].reg
= new_loc
[src
];
474 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
475 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
476 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
477 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
478 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
484 src_reg::is_zero() const
489 if (type
== BRW_REGISTER_TYPE_F
) {
497 src_reg::is_one() const
502 if (type
== BRW_REGISTER_TYPE_F
) {
510 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
512 * While GLSL IR also performs this optimization, we end up with it in
513 * our instruction stream for a couple of reasons. One is that we
514 * sometimes generate silly instructions, for example in array access
515 * where we'll generate "ADD offset, index, base" even if base is 0.
516 * The other is that GLSL IR's constant propagation doesn't track the
517 * components of aggregates, so some VS patterns (initialize matrix to
518 * 0, accumulate in vertex blending factors) end up breaking down to
519 * instructions involving 0.
522 vec4_visitor::opt_algebraic()
524 bool progress
= false;
526 foreach_list(node
, &this->instructions
) {
527 vec4_instruction
*inst
= (vec4_instruction
*)node
;
529 switch (inst
->opcode
) {
531 if (inst
->src
[1].is_zero()) {
532 inst
->opcode
= BRW_OPCODE_MOV
;
533 inst
->src
[1] = src_reg();
539 if (inst
->src
[1].is_zero()) {
540 inst
->opcode
= BRW_OPCODE_MOV
;
541 switch (inst
->src
[0].type
) {
542 case BRW_REGISTER_TYPE_F
:
543 inst
->src
[0] = src_reg(0.0f
);
545 case BRW_REGISTER_TYPE_D
:
546 inst
->src
[0] = src_reg(0);
548 case BRW_REGISTER_TYPE_UD
:
549 inst
->src
[0] = src_reg(0u);
552 assert(!"not reached");
553 inst
->src
[0] = src_reg(0.0f
);
556 inst
->src
[1] = src_reg();
558 } else if (inst
->src
[1].is_one()) {
559 inst
->opcode
= BRW_OPCODE_MOV
;
560 inst
->src
[1] = src_reg();
570 invalidate_live_intervals();
576 * Only a limited number of hardware registers may be used for push
577 * constants, so this turns access to the overflowed constants into
581 vec4_visitor::move_push_constants_to_pull_constants()
583 int pull_constant_loc
[this->uniforms
];
585 /* Only allow 32 registers (256 uniform components) as push constants,
586 * which is the limit on gen6.
588 int max_uniform_components
= 32 * 8;
589 if (this->uniforms
* 4 <= max_uniform_components
)
592 /* Make some sort of choice as to which uniforms get sent to pull
593 * constants. We could potentially do something clever here like
594 * look for the most infrequently used uniform vec4s, but leave
597 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
598 pull_constant_loc
[i
/ 4] = -1;
600 if (i
>= max_uniform_components
) {
601 const float **values
= &stage_prog_data
->param
[i
];
603 /* Try to find an existing copy of this uniform in the pull
604 * constants if it was part of an array access already.
606 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
609 for (matches
= 0; matches
< 4; matches
++) {
610 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
615 pull_constant_loc
[i
/ 4] = j
/ 4;
620 if (pull_constant_loc
[i
/ 4] == -1) {
621 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
622 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
624 for (int j
= 0; j
< 4; j
++) {
625 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
632 /* Now actually rewrite usage of the things we've moved to pull
635 foreach_list_safe(node
, &this->instructions
) {
636 vec4_instruction
*inst
= (vec4_instruction
*)node
;
638 for (int i
= 0 ; i
< 3; i
++) {
639 if (inst
->src
[i
].file
!= UNIFORM
||
640 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
643 int uniform
= inst
->src
[i
].reg
;
645 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
647 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
648 pull_constant_loc
[uniform
]);
650 inst
->src
[i
].file
= temp
.file
;
651 inst
->src
[i
].reg
= temp
.reg
;
652 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
653 inst
->src
[i
].reladdr
= NULL
;
657 /* Repack push constants to remove the now-unused ones. */
658 pack_uniform_registers();
662 * Sets the dependency control fields on instructions after register
663 * allocation and before the generator is run.
665 * When you have a sequence of instructions like:
667 * DP4 temp.x vertex uniform[0]
668 * DP4 temp.y vertex uniform[0]
669 * DP4 temp.z vertex uniform[0]
670 * DP4 temp.w vertex uniform[0]
672 * The hardware doesn't know that it can actually run the later instructions
673 * while the previous ones are in flight, producing stalls. However, we have
674 * manual fields we can set in the instructions that let it do so.
677 vec4_visitor::opt_set_dependency_control()
679 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
680 uint8_t grf_channels_written
[BRW_MAX_GRF
];
681 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
682 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
684 cfg_t
cfg(&instructions
);
686 assert(prog_data
->total_grf
||
687 !"Must be called after register allocation");
689 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
690 bblock_t
*bblock
= cfg
.blocks
[i
];
691 vec4_instruction
*inst
;
693 memset(last_grf_write
, 0, sizeof(last_grf_write
));
694 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
696 for (inst
= (vec4_instruction
*)bblock
->start
;
697 inst
!= (vec4_instruction
*)bblock
->end
->next
;
698 inst
= (vec4_instruction
*)inst
->next
) {
699 /* If we read from a register that we were doing dependency control
700 * on, don't do dependency control across the read.
702 for (int i
= 0; i
< 3; i
++) {
703 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
704 if (inst
->src
[i
].file
== GRF
) {
705 last_grf_write
[reg
] = NULL
;
706 } else if (inst
->src
[i
].file
== HW_REG
) {
707 memset(last_grf_write
, 0, sizeof(last_grf_write
));
710 assert(inst
->src
[i
].file
!= MRF
);
713 /* In the presence of send messages, totally interrupt dependency
714 * control. They're long enough that the chance of dependency
715 * control around them just doesn't matter.
718 memset(last_grf_write
, 0, sizeof(last_grf_write
));
719 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
723 /* It looks like setting dependency control on a predicated
724 * instruction hangs the GPU.
726 if (inst
->predicate
) {
727 memset(last_grf_write
, 0, sizeof(last_grf_write
));
728 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
732 /* Now, see if we can do dependency control for this instruction
733 * against a previous one writing to its destination.
735 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
736 if (inst
->dst
.file
== GRF
) {
737 if (last_grf_write
[reg
] &&
738 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
739 last_grf_write
[reg
]->no_dd_clear
= true;
740 inst
->no_dd_check
= true;
742 grf_channels_written
[reg
] = 0;
745 last_grf_write
[reg
] = inst
;
746 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
747 } else if (inst
->dst
.file
== MRF
) {
748 if (last_mrf_write
[reg
] &&
749 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
750 last_mrf_write
[reg
]->no_dd_clear
= true;
751 inst
->no_dd_check
= true;
753 mrf_channels_written
[reg
] = 0;
756 last_mrf_write
[reg
] = inst
;
757 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
758 } else if (inst
->dst
.reg
== HW_REG
) {
759 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
760 memset(last_grf_write
, 0, sizeof(last_grf_write
));
761 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
762 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
769 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
773 /* If this instruction sets anything not referenced by swizzle, then we'd
774 * totally break it when we reswizzle.
776 if (dst
.writemask
& ~swizzle_mask
)
785 /* Check if there happens to be no reswizzling required. */
786 for (int c
= 0; c
< 4; c
++) {
787 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
788 /* Skip components of the swizzle not used by the dst. */
789 if (!(dst_writemask
& (1 << c
)))
792 /* We don't do the reswizzling yet, so just sanity check that we
803 * For any channels in the swizzle's source that were populated by this
804 * instruction, rewrite the instruction to put the appropriate result directly
807 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
810 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
812 int new_writemask
= 0;
818 for (int c
= 0; c
< 4; c
++) {
819 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
820 /* Skip components of the swizzle not used by the dst. */
821 if (!(dst_writemask
& (1 << c
)))
823 /* If we were populating this component, then populate the
824 * corresponding channel of the new dst.
826 if (dst
.writemask
& bit
)
827 new_writemask
|= (1 << c
);
829 dst
.writemask
= new_writemask
;
832 for (int c
= 0; c
< 4; c
++) {
833 /* Skip components of the swizzle not used by the dst. */
834 if (!(dst_writemask
& (1 << c
)))
837 /* We don't do the reswizzling yet, so just sanity check that we
840 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
847 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
848 * just written and then MOVed into another reg and making the original write
849 * of the GRF write directly to the final destination instead.
852 vec4_visitor::opt_register_coalesce()
854 bool progress
= false;
857 calculate_live_intervals();
859 foreach_list_safe(node
, &this->instructions
) {
860 vec4_instruction
*inst
= (vec4_instruction
*)node
;
865 if (inst
->opcode
!= BRW_OPCODE_MOV
||
866 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
868 inst
->src
[0].file
!= GRF
||
869 inst
->dst
.type
!= inst
->src
[0].type
||
870 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
873 bool to_mrf
= (inst
->dst
.file
== MRF
);
875 /* Can't coalesce this GRF if someone else was going to
878 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
881 /* We need to check interference with the final destination between this
882 * instruction and the earliest instruction involved in writing the GRF
883 * we're eliminating. To do that, keep track of which of our source
884 * channels we've seen initialized.
886 bool chans_needed
[4] = {false, false, false, false};
887 int chans_remaining
= 0;
888 int swizzle_mask
= 0;
889 for (int i
= 0; i
< 4; i
++) {
890 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
892 if (!(inst
->dst
.writemask
& (1 << i
)))
895 swizzle_mask
|= (1 << chan
);
897 if (!chans_needed
[chan
]) {
898 chans_needed
[chan
] = true;
903 /* Now walk up the instruction stream trying to see if we can rewrite
904 * everything writing to the temporary to write into the destination
907 vec4_instruction
*scan_inst
;
908 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
909 scan_inst
->prev
!= NULL
;
910 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
911 if (scan_inst
->dst
.file
== GRF
&&
912 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
913 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
914 /* Found something writing to the reg we want to coalesce away. */
916 /* SEND instructions can't have MRF as a destination. */
921 /* gen6 math instructions must have the destination be
922 * GRF, so no compute-to-MRF for them.
924 if (scan_inst
->is_math()) {
930 /* If we can't handle the swizzle, bail. */
931 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
932 inst
->src
[0].swizzle
,
937 /* Mark which channels we found unconditional writes for. */
938 if (!scan_inst
->predicate
) {
939 for (int i
= 0; i
< 4; i
++) {
940 if (scan_inst
->dst
.writemask
& (1 << i
) &&
942 chans_needed
[i
] = false;
948 if (chans_remaining
== 0)
952 /* We don't handle flow control here. Most computation of values
953 * that could be coalesced happens just before their use.
955 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
956 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
957 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
958 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
962 /* You can't read from an MRF, so if someone else reads our MRF's
963 * source GRF that we wanted to rewrite, that stops us. If it's a
964 * GRF we're trying to coalesce to, we don't actually handle
965 * rewriting sources so bail in that case as well.
967 bool interfered
= false;
968 for (int i
= 0; i
< 3; i
++) {
969 if (scan_inst
->src
[i
].file
== GRF
&&
970 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
971 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
978 /* If somebody else writes our destination here, we can't coalesce
981 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
982 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
986 /* Check for reads of the register we're trying to coalesce into. We
987 * can't go rewriting instructions above that to put some other value
988 * in the register instead.
990 if (to_mrf
&& scan_inst
->mlen
> 0) {
991 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
992 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
996 for (int i
= 0; i
< 3; i
++) {
997 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
998 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
999 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1008 if (chans_remaining
== 0) {
1009 /* If we've made it here, we have an MOV we want to coalesce out, and
1010 * a scan_inst pointing to the earliest instruction involved in
1011 * computing the value. Now go rewrite the instruction stream
1015 while (scan_inst
!= inst
) {
1016 if (scan_inst
->dst
.file
== GRF
&&
1017 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1018 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1019 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1020 inst
->src
[0].swizzle
);
1021 scan_inst
->dst
.file
= inst
->dst
.file
;
1022 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1023 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1024 scan_inst
->saturate
|= inst
->saturate
;
1026 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1034 invalidate_live_intervals();
1040 * Splits virtual GRFs requesting more than one contiguous physical register.
1042 * We initially create large virtual GRFs for temporary structures, arrays,
1043 * and matrices, so that the dereference visitor functions can add reg_offsets
1044 * to work their way down to the actual member being accessed. But when it
1045 * comes to optimization, we'd like to treat each register as individual
1046 * storage if possible.
1048 * So far, the only thing that might prevent splitting is a send message from
1052 vec4_visitor::split_virtual_grfs()
1054 int num_vars
= this->virtual_grf_count
;
1055 int new_virtual_grf
[num_vars
];
1056 bool split_grf
[num_vars
];
1058 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1060 /* Try to split anything > 0 sized. */
1061 for (int i
= 0; i
< num_vars
; i
++) {
1062 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1065 /* Check that the instructions are compatible with the registers we're trying
1068 foreach_list(node
, &this->instructions
) {
1069 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1071 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1074 if (inst
->is_send_from_grf()) {
1075 for (int i
= 0; i
< 3; i
++) {
1076 if (inst
->src
[i
].file
== GRF
) {
1077 split_grf
[inst
->src
[i
].reg
] = false;
1083 /* Allocate new space for split regs. Note that the virtual
1084 * numbers will be contiguous.
1086 for (int i
= 0; i
< num_vars
; i
++) {
1090 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1091 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1092 int reg
= virtual_grf_alloc(1);
1093 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1096 this->virtual_grf_sizes
[i
] = 1;
1099 foreach_list(node
, &this->instructions
) {
1100 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1102 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1103 inst
->dst
.reg_offset
!= 0) {
1104 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1105 inst
->dst
.reg_offset
- 1);
1106 inst
->dst
.reg_offset
= 0;
1108 for (int i
= 0; i
< 3; i
++) {
1109 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1110 inst
->src
[i
].reg_offset
!= 0) {
1111 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1112 inst
->src
[i
].reg_offset
- 1);
1113 inst
->src
[i
].reg_offset
= 0;
1117 invalidate_live_intervals();
1121 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1123 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1125 fprintf(stderr
, "%s", brw_instruction_name(inst
->opcode
));
1126 if (inst
->conditional_mod
) {
1127 fprintf(stderr
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1129 fprintf(stderr
, " ");
1131 switch (inst
->dst
.file
) {
1133 fprintf(stderr
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1136 fprintf(stderr
, "m%d", inst
->dst
.reg
);
1139 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1140 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1142 fprintf(stderr
, "null");
1144 case BRW_ARF_ADDRESS
:
1145 fprintf(stderr
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1147 case BRW_ARF_ACCUMULATOR
:
1148 fprintf(stderr
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1151 fprintf(stderr
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1152 inst
->dst
.fixed_hw_reg
.subnr
);
1155 fprintf(stderr
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1156 inst
->dst
.fixed_hw_reg
.subnr
);
1160 fprintf(stderr
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1162 if (inst
->dst
.fixed_hw_reg
.subnr
)
1163 fprintf(stderr
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1166 fprintf(stderr
, "(null)");
1169 fprintf(stderr
, "???");
1172 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1173 fprintf(stderr
, ".");
1174 if (inst
->dst
.writemask
& 1)
1175 fprintf(stderr
, "x");
1176 if (inst
->dst
.writemask
& 2)
1177 fprintf(stderr
, "y");
1178 if (inst
->dst
.writemask
& 4)
1179 fprintf(stderr
, "z");
1180 if (inst
->dst
.writemask
& 8)
1181 fprintf(stderr
, "w");
1183 fprintf(stderr
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
1185 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1186 if (inst
->src
[i
].negate
)
1187 fprintf(stderr
, "-");
1188 if (inst
->src
[i
].abs
)
1189 fprintf(stderr
, "|");
1190 switch (inst
->src
[i
].file
) {
1192 fprintf(stderr
, "vgrf%d", inst
->src
[i
].reg
);
1195 fprintf(stderr
, "attr%d", inst
->src
[i
].reg
);
1198 fprintf(stderr
, "u%d", inst
->src
[i
].reg
);
1201 switch (inst
->src
[i
].type
) {
1202 case BRW_REGISTER_TYPE_F
:
1203 fprintf(stderr
, "%fF", inst
->src
[i
].imm
.f
);
1205 case BRW_REGISTER_TYPE_D
:
1206 fprintf(stderr
, "%dD", inst
->src
[i
].imm
.i
);
1208 case BRW_REGISTER_TYPE_UD
:
1209 fprintf(stderr
, "%uU", inst
->src
[i
].imm
.u
);
1212 fprintf(stderr
, "???");
1217 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1218 fprintf(stderr
, "-");
1219 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1220 fprintf(stderr
, "|");
1221 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1222 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1224 fprintf(stderr
, "null");
1226 case BRW_ARF_ADDRESS
:
1227 fprintf(stderr
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1229 case BRW_ARF_ACCUMULATOR
:
1230 fprintf(stderr
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1233 fprintf(stderr
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1234 inst
->src
[i
].fixed_hw_reg
.subnr
);
1237 fprintf(stderr
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1238 inst
->src
[i
].fixed_hw_reg
.subnr
);
1242 fprintf(stderr
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1244 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1245 fprintf(stderr
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1246 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1247 fprintf(stderr
, "|");
1250 fprintf(stderr
, "(null)");
1253 fprintf(stderr
, "???");
1257 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1258 fprintf(stderr
, ".%d", inst
->src
[i
].reg_offset
);
1260 if (inst
->src
[i
].file
!= IMM
) {
1261 static const char *chans
[4] = {"x", "y", "z", "w"};
1262 fprintf(stderr
, ".");
1263 for (int c
= 0; c
< 4; c
++) {
1264 fprintf(stderr
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1268 if (inst
->src
[i
].abs
)
1269 fprintf(stderr
, "|");
1271 if (inst
->src
[i
].file
!= IMM
) {
1272 fprintf(stderr
, ":%s", reg_encoding
[inst
->src
[i
].type
]);
1275 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1276 fprintf(stderr
, ", ");
1279 fprintf(stderr
, "\n");
1283 static inline struct brw_reg
1284 attribute_to_hw_reg(int attr
, bool interleaved
)
1287 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1289 return brw_vec8_grf(attr
, 0);
1294 * Replace each register of type ATTR in this->instructions with a reference
1295 * to a fixed HW register.
1297 * If interleaved is true, then each attribute takes up half a register, with
1298 * register N containing attribute 2*N in its first half and attribute 2*N+1
1299 * in its second half (this corresponds to the payload setup used by geometry
1300 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1301 * false, then each attribute takes up a whole register, with register N
1302 * containing attribute N (this corresponds to the payload setup used by
1303 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1306 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1309 foreach_list(node
, &this->instructions
) {
1310 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1312 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1313 if (inst
->dst
.file
== ATTR
) {
1314 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1316 /* All attributes used in the shader need to have been assigned a
1317 * hardware register by the caller
1321 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1322 reg
.type
= inst
->dst
.type
;
1323 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1325 inst
->dst
.file
= HW_REG
;
1326 inst
->dst
.fixed_hw_reg
= reg
;
1329 for (int i
= 0; i
< 3; i
++) {
1330 if (inst
->src
[i
].file
!= ATTR
)
1333 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1335 /* All attributes used in the shader need to have been assigned a
1336 * hardware register by the caller
1340 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1341 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1342 reg
.type
= inst
->src
[i
].type
;
1343 if (inst
->src
[i
].abs
)
1345 if (inst
->src
[i
].negate
)
1348 inst
->src
[i
].file
= HW_REG
;
1349 inst
->src
[i
].fixed_hw_reg
= reg
;
1355 vec4_vs_visitor::setup_attributes(int payload_reg
)
1358 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1359 memset(attribute_map
, 0, sizeof(attribute_map
));
1362 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1363 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1364 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1369 /* VertexID is stored by the VF as the last vertex element, but we
1370 * don't represent it with a flag in inputs_read, so we call it
1373 if (vs_prog_data
->uses_vertexid
) {
1374 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1378 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1380 /* The BSpec says we always have to read at least one thing from
1381 * the VF, and it appears that the hardware wedges otherwise.
1383 if (nr_attributes
== 0)
1386 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1388 unsigned vue_entries
=
1389 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1392 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1394 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1396 return payload_reg
+ nr_attributes
;
1400 vec4_visitor::setup_uniforms(int reg
)
1402 prog_data
->dispatch_grf_start_reg
= reg
;
1404 /* The pre-gen6 VS requires that some push constants get loaded no
1405 * matter what, or the GPU would hang.
1407 if (brw
->gen
< 6 && this->uniforms
== 0) {
1408 assert(this->uniforms
< this->uniform_array_size
);
1409 this->uniform_vector_size
[this->uniforms
] = 1;
1411 stage_prog_data
->param
=
1412 reralloc(NULL
, stage_prog_data
->param
, const float *, 4);
1413 for (unsigned int i
= 0; i
< 4; i
++) {
1414 unsigned int slot
= this->uniforms
* 4 + i
;
1415 static float zero
= 0.0;
1416 stage_prog_data
->param
[slot
] = &zero
;
1422 reg
+= ALIGN(uniforms
, 2) / 2;
1425 stage_prog_data
->nr_params
= this->uniforms
* 4;
1427 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1433 vec4_vs_visitor::setup_payload(void)
1437 /* The payload always contains important data in g0, which contains
1438 * the URB handles that are passed on to the URB write at the end
1439 * of the thread. So, we always start push constants at g1.
1443 reg
= setup_uniforms(reg
);
1445 reg
= setup_attributes(reg
);
1447 this->first_non_payload_grf
= reg
;
1451 vec4_visitor::get_timestamp()
1453 assert(brw
->gen
>= 7);
1455 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1458 BRW_REGISTER_TYPE_UD
,
1459 BRW_VERTICAL_STRIDE_0
,
1461 BRW_HORIZONTAL_STRIDE_4
,
1465 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1467 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1468 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1469 * even if it's not enabled in the dispatch.
1471 mov
->force_writemask_all
= true;
1473 return src_reg(dst
);
1477 vec4_visitor::emit_shader_time_begin()
1479 current_annotation
= "shader time start";
1480 shader_start_time
= get_timestamp();
1484 vec4_visitor::emit_shader_time_end()
1486 current_annotation
= "shader time end";
1487 src_reg shader_end_time
= get_timestamp();
1490 /* Check that there weren't any timestamp reset events (assuming these
1491 * were the only two timestamp reads that happened).
1493 src_reg reset_end
= shader_end_time
;
1494 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1495 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1496 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1498 emit(IF(BRW_PREDICATE_NORMAL
));
1500 /* Take the current timestamp and get the delta. */
1501 shader_start_time
.negate
= true;
1502 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1503 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1505 /* If there were no instructions between the two timestamp gets, the diff
1506 * is 2 cycles. Remove that overhead, so I can forget about that when
1507 * trying to determine the time taken for single instructions.
1509 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1511 emit_shader_time_write(st_base
, src_reg(diff
));
1512 emit_shader_time_write(st_written
, src_reg(1u));
1513 emit(BRW_OPCODE_ELSE
);
1514 emit_shader_time_write(st_reset
, src_reg(1u));
1515 emit(BRW_OPCODE_ENDIF
);
1519 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1522 int shader_time_index
=
1523 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1526 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1528 dst_reg offset
= dst
;
1532 offset
.type
= BRW_REGISTER_TYPE_UD
;
1533 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1535 time
.type
= BRW_REGISTER_TYPE_UD
;
1536 emit(MOV(time
, src_reg(value
)));
1538 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1544 sanity_param_count
= prog
->Parameters
->NumParameters
;
1546 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1547 emit_shader_time_begin();
1549 assign_common_binding_table_offsets(0);
1553 /* Generate VS IR for main(). (the visitor only descends into
1554 * functions called "main").
1557 visit_instructions(shader
->base
.ir
);
1559 emit_program_code();
1563 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1564 setup_uniform_clipplane_values();
1568 /* Before any optimization, push array accesses out to scratch
1569 * space where we need them to be. This pass may allocate new
1570 * virtual GRFs, so we want to do it early. It also makes sure
1571 * that we have reladdr computations available for CSE, since we'll
1572 * often do repeated subexpressions for those.
1575 move_grf_array_access_to_scratch();
1576 move_uniform_array_access_to_pull_constants();
1578 /* The ARB_vertex_program frontend emits pull constant loads directly
1579 * rather than using reladdr, so we don't need to walk through all the
1580 * instructions looking for things to move. There isn't anything.
1582 * We do still need to split things to vec4 size.
1584 split_uniform_registers();
1586 pack_uniform_registers();
1587 move_push_constants_to_pull_constants();
1588 split_virtual_grfs();
1593 progress
= dead_code_eliminate() || progress
;
1594 progress
= dead_control_flow_eliminate(this) || progress
;
1595 progress
= opt_copy_propagation() || progress
;
1596 progress
= opt_algebraic() || progress
;
1597 progress
= opt_register_coalesce() || progress
;
1607 /* Debug of register spilling: Go spill everything. */
1608 const int grf_count
= virtual_grf_count
;
1609 float spill_costs
[virtual_grf_count
];
1610 bool no_spill
[virtual_grf_count
];
1611 evaluate_spill_costs(spill_costs
, no_spill
);
1612 for (int i
= 0; i
< grf_count
; i
++) {
1619 while (!reg_allocate()) {
1624 opt_schedule_instructions();
1626 opt_set_dependency_control();
1628 /* If any state parameters were appended, then ParameterValues could have
1629 * been realloced, in which case the driver uniform storage set up by
1630 * _mesa_associate_uniform_storage() would point to freed memory. Make
1631 * sure that didn't happen.
1633 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1638 } /* namespace brw */
1643 * Compile a vertex shader.
1645 * Returns the final assembly and the program's size.
1648 brw_vs_emit(struct brw_context
*brw
,
1649 struct gl_shader_program
*prog
,
1650 struct brw_vs_compile
*c
,
1651 struct brw_vs_prog_data
*prog_data
,
1653 unsigned *final_assembly_size
)
1655 bool start_busy
= false;
1656 double start_time
= 0;
1658 if (unlikely(brw
->perf_debug
)) {
1659 start_busy
= (brw
->batch
.last_bo
&&
1660 drm_intel_bo_busy(brw
->batch
.last_bo
));
1661 start_time
= get_time();
1664 struct brw_shader
*shader
= NULL
;
1666 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1668 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1669 brw_dump_ir(brw
, "vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1671 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1674 prog
->LinkStatus
= false;
1675 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1678 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1684 const unsigned *assembly
= NULL
;
1685 if (brw
->gen
>= 8) {
1686 gen8_vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1687 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1688 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1690 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1691 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1692 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1695 if (unlikely(brw
->perf_debug
) && shader
) {
1696 if (shader
->compiled_once
) {
1697 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1699 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1700 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1701 (get_time() - start_time
) * 1000);
1703 shader
->compiled_once
= true;
1711 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1712 struct brw_vec4_prog_key
*key
,
1713 GLuint id
, struct gl_program
*prog
)
1715 key
->program_string_id
= id
;
1716 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1718 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1719 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1720 if (prog
->ShadowSamplers
& (1 << i
)) {
1721 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1722 key
->tex
.swizzles
[i
] =
1723 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1725 /* Color sampler: assume no swizzling. */
1726 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;