2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
115 src_reg::src_reg(struct brw_reg reg
)
120 this->fixed_hw_reg
= reg
;
121 this->type
= reg
.type
;
124 src_reg::src_reg(dst_reg reg
)
128 this->file
= reg
.file
;
130 this->reg_offset
= reg
.reg_offset
;
131 this->type
= reg
.type
;
132 this->reladdr
= reg
.reladdr
;
133 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 for (int i
= 0; i
< 4; i
++) {
140 if (!(reg
.writemask
& (1 << i
)))
143 swizzles
[next_chan
++] = last
= i
;
146 for (; next_chan
< 4; next_chan
++) {
147 swizzles
[next_chan
] = last
;
150 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
151 swizzles
[2], swizzles
[3]);
155 src_reg::is_accumulator() const
157 return file
== HW_REG
&&
158 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
159 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
166 memset(this, 0, sizeof(*this));
167 this->file
= BAD_FILE
;
168 this->writemask
= WRITEMASK_XYZW
;
176 dst_reg::dst_reg(register_file file
, int reg
)
184 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
191 this->type
= brw_type_for_base_type(type
);
192 this->writemask
= writemask
;
195 dst_reg::dst_reg(struct brw_reg reg
)
200 this->fixed_hw_reg
= reg
;
201 this->type
= reg
.type
;
204 dst_reg::dst_reg(src_reg reg
)
208 this->file
= reg
.file
;
210 this->reg_offset
= reg
.reg_offset
;
211 this->type
= reg
.type
;
212 /* How should we do writemasking when converting from a src_reg? It seems
213 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
214 * what about for src.wx? Just special-case src.xxxx for now.
216 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
217 this->writemask
= WRITEMASK_X
;
219 this->writemask
= WRITEMASK_XYZW
;
220 this->reladdr
= reg
.reladdr
;
221 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
225 dst_reg::is_null() const
227 return file
== HW_REG
&&
228 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
229 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
233 dst_reg::is_accumulator() const
235 return file
== HW_REG
&&
236 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
237 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
241 vec4_instruction::is_send_from_grf()
244 case SHADER_OPCODE_SHADER_TIME_ADD
:
245 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
253 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
255 if (brw
->gen
== 6 && inst
->is_math())
258 if (inst
->is_send_from_grf())
261 if (!inst
->can_do_source_mods())
268 * Returns how many MRFs an opcode will write over.
270 * Note that this is not the 0 or 1 implied writes in an actual gen
271 * instruction -- the generate_* functions generate additional MOVs
275 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
280 switch (inst
->opcode
) {
281 case SHADER_OPCODE_RCP
:
282 case SHADER_OPCODE_RSQ
:
283 case SHADER_OPCODE_SQRT
:
284 case SHADER_OPCODE_EXP2
:
285 case SHADER_OPCODE_LOG2
:
286 case SHADER_OPCODE_SIN
:
287 case SHADER_OPCODE_COS
:
289 case SHADER_OPCODE_INT_QUOTIENT
:
290 case SHADER_OPCODE_INT_REMAINDER
:
291 case SHADER_OPCODE_POW
:
293 case VS_OPCODE_URB_WRITE
:
295 case VS_OPCODE_PULL_CONSTANT_LOAD
:
297 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
299 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
301 case GS_OPCODE_URB_WRITE
:
302 case GS_OPCODE_THREAD_END
:
304 case SHADER_OPCODE_SHADER_TIME_ADD
:
306 case SHADER_OPCODE_TEX
:
307 case SHADER_OPCODE_TXL
:
308 case SHADER_OPCODE_TXD
:
309 case SHADER_OPCODE_TXF
:
310 case SHADER_OPCODE_TXF_CMS
:
311 case SHADER_OPCODE_TXF_MCS
:
312 case SHADER_OPCODE_TXS
:
313 case SHADER_OPCODE_TG4
:
314 case SHADER_OPCODE_TG4_OFFSET
:
315 return inst
->header_present
? 1 : 0;
316 case SHADER_OPCODE_UNTYPED_ATOMIC
:
317 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
320 assert(!"not reached");
326 src_reg::equals(src_reg
*r
)
328 return (file
== r
->file
&&
330 reg_offset
== r
->reg_offset
&&
332 negate
== r
->negate
&&
334 swizzle
== r
->swizzle
&&
335 !reladdr
&& !r
->reladdr
&&
336 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
337 sizeof(fixed_hw_reg
)) == 0 &&
342 try_eliminate_instruction(vec4_instruction
*inst
, int new_writemask
,
343 const struct brw_context
*brw
)
345 if (inst
->has_side_effects())
348 if (new_writemask
== 0) {
349 /* Don't dead code eliminate instructions that write to the
350 * accumulator as a side-effect. Instead just set the destination
351 * to the null register to free it.
353 if (inst
->writes_accumulator
|| inst
->writes_flag()) {
354 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
360 } else if (inst
->dst
.writemask
!= new_writemask
) {
361 switch (inst
->opcode
) {
362 case SHADER_OPCODE_TXF_CMS
:
363 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
364 case VS_OPCODE_PULL_CONSTANT_LOAD
:
365 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
368 /* Do not set a writemask on Gen6 for math instructions, those are
369 * executed using align1 mode that does not support a destination mask.
371 if (!(brw
->gen
== 6 && inst
->is_math()) && !inst
->is_tex()) {
372 inst
->dst
.writemask
= new_writemask
;
382 * Must be called after calculate_live_intervals() to remove unused
383 * writes to registers -- register allocation will fail otherwise
384 * because something deffed but not used won't be considered to
385 * interfere with other regs.
388 vec4_visitor::dead_code_eliminate()
390 bool progress
= false;
393 calculate_live_intervals();
395 foreach_list_safe(node
, &this->instructions
) {
396 vec4_instruction
*inst
= (vec4_instruction
*)node
;
400 bool inst_writes_flag
= false;
401 if (inst
->dst
.file
!= GRF
) {
402 if (inst
->dst
.is_null() && inst
->writes_flag()) {
403 inst_writes_flag
= true;
409 if (inst
->dst
.file
== GRF
) {
410 int write_mask
= inst
->dst
.writemask
;
412 for (int c
= 0; c
< 4; c
++) {
413 if (write_mask
& (1 << c
)) {
414 assert(this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] >= pc
);
415 if (this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] == pc
) {
416 write_mask
&= ~(1 << c
);
421 progress
= try_eliminate_instruction(inst
, write_mask
, brw
) ||
425 if (inst
->predicate
|| inst
->prev
== NULL
)
429 if (inst_writes_flag
) {
430 /* Arbitrarily chosen, other than not being an xyzw writemask. */
431 #define FLAG_WRITEMASK (1 << 5)
432 dead_channels
= inst
->reads_flag() ? 0 : FLAG_WRITEMASK
;
434 dead_channels
= inst
->dst
.writemask
;
436 for (int i
= 0; i
< 3; i
++) {
437 if (inst
->src
[i
].file
!= GRF
||
438 inst
->src
[i
].reg
!= inst
->dst
.reg
)
441 for (int j
= 0; j
< 4; j
++) {
442 int swiz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
443 dead_channels
&= ~(1 << swiz
);
448 for (exec_node
*node
= inst
->prev
, *prev
= node
->prev
;
449 prev
!= NULL
&& dead_channels
!= 0;
450 node
= prev
, prev
= prev
->prev
) {
451 vec4_instruction
*scan_inst
= (vec4_instruction
*)node
;
453 if (scan_inst
->is_control_flow())
456 if (inst_writes_flag
) {
457 if (scan_inst
->dst
.is_null() && scan_inst
->writes_flag()) {
461 } else if (scan_inst
->reads_flag()) {
466 if (inst
->dst
.file
== scan_inst
->dst
.file
&&
467 inst
->dst
.reg
== scan_inst
->dst
.reg
) {
468 int new_writemask
= scan_inst
->dst
.writemask
& ~dead_channels
;
470 progress
= try_eliminate_instruction(scan_inst
, new_writemask
, brw
) ||
474 for (int i
= 0; i
< 3; i
++) {
475 if (scan_inst
->src
[i
].file
!= inst
->dst
.file
||
476 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
)
479 for (int j
= 0; j
< 4; j
++) {
480 int swiz
= BRW_GET_SWZ(scan_inst
->src
[i
].swizzle
, j
);
481 dead_channels
&= ~(1 << swiz
);
488 invalidate_live_intervals();
494 vec4_visitor::split_uniform_registers()
496 /* Prior to this, uniforms have been in an array sized according to
497 * the number of vector uniforms present, sparsely filled (so an
498 * aggregate results in reg indices being skipped over). Now we're
499 * going to cut those aggregates up so each .reg index is one
500 * vector. The goal is to make elimination of unused uniform
501 * components easier later.
503 foreach_list(node
, &this->instructions
) {
504 vec4_instruction
*inst
= (vec4_instruction
*)node
;
506 for (int i
= 0 ; i
< 3; i
++) {
507 if (inst
->src
[i
].file
!= UNIFORM
)
510 assert(!inst
->src
[i
].reladdr
);
512 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
513 inst
->src
[i
].reg_offset
= 0;
517 /* Update that everything is now vector-sized. */
518 for (int i
= 0; i
< this->uniforms
; i
++) {
519 this->uniform_size
[i
] = 1;
524 vec4_visitor::pack_uniform_registers()
526 bool uniform_used
[this->uniforms
];
527 int new_loc
[this->uniforms
];
528 int new_chan
[this->uniforms
];
530 memset(uniform_used
, 0, sizeof(uniform_used
));
531 memset(new_loc
, 0, sizeof(new_loc
));
532 memset(new_chan
, 0, sizeof(new_chan
));
534 /* Find which uniform vectors are actually used by the program. We
535 * expect unused vector elements when we've moved array access out
536 * to pull constants, and from some GLSL code generators like wine.
538 foreach_list(node
, &this->instructions
) {
539 vec4_instruction
*inst
= (vec4_instruction
*)node
;
541 for (int i
= 0 ; i
< 3; i
++) {
542 if (inst
->src
[i
].file
!= UNIFORM
)
545 uniform_used
[inst
->src
[i
].reg
] = true;
549 int new_uniform_count
= 0;
551 /* Now, figure out a packing of the live uniform vectors into our
554 for (int src
= 0; src
< uniforms
; src
++) {
555 assert(src
< uniform_array_size
);
556 int size
= this->uniform_vector_size
[src
];
558 if (!uniform_used
[src
]) {
559 this->uniform_vector_size
[src
] = 0;
564 /* Find the lowest place we can slot this uniform in. */
565 for (dst
= 0; dst
< src
; dst
++) {
566 if (this->uniform_vector_size
[dst
] + size
<= 4)
575 new_chan
[src
] = this->uniform_vector_size
[dst
];
577 /* Move the references to the data */
578 for (int j
= 0; j
< size
; j
++) {
579 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
580 stage_prog_data
->param
[src
* 4 + j
];
583 this->uniform_vector_size
[dst
] += size
;
584 this->uniform_vector_size
[src
] = 0;
587 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
590 this->uniforms
= new_uniform_count
;
592 /* Now, update the instructions for our repacked uniforms. */
593 foreach_list(node
, &this->instructions
) {
594 vec4_instruction
*inst
= (vec4_instruction
*)node
;
596 for (int i
= 0 ; i
< 3; i
++) {
597 int src
= inst
->src
[i
].reg
;
599 if (inst
->src
[i
].file
!= UNIFORM
)
602 inst
->src
[i
].reg
= new_loc
[src
];
604 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
605 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
606 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
607 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
608 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
614 src_reg::is_zero() const
619 if (type
== BRW_REGISTER_TYPE_F
) {
627 src_reg::is_one() const
632 if (type
== BRW_REGISTER_TYPE_F
) {
640 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
642 * While GLSL IR also performs this optimization, we end up with it in
643 * our instruction stream for a couple of reasons. One is that we
644 * sometimes generate silly instructions, for example in array access
645 * where we'll generate "ADD offset, index, base" even if base is 0.
646 * The other is that GLSL IR's constant propagation doesn't track the
647 * components of aggregates, so some VS patterns (initialize matrix to
648 * 0, accumulate in vertex blending factors) end up breaking down to
649 * instructions involving 0.
652 vec4_visitor::opt_algebraic()
654 bool progress
= false;
656 foreach_list(node
, &this->instructions
) {
657 vec4_instruction
*inst
= (vec4_instruction
*)node
;
659 switch (inst
->opcode
) {
661 if (inst
->src
[1].is_zero()) {
662 inst
->opcode
= BRW_OPCODE_MOV
;
663 inst
->src
[1] = src_reg();
669 if (inst
->src
[1].is_zero()) {
670 inst
->opcode
= BRW_OPCODE_MOV
;
671 switch (inst
->src
[0].type
) {
672 case BRW_REGISTER_TYPE_F
:
673 inst
->src
[0] = src_reg(0.0f
);
675 case BRW_REGISTER_TYPE_D
:
676 inst
->src
[0] = src_reg(0);
678 case BRW_REGISTER_TYPE_UD
:
679 inst
->src
[0] = src_reg(0u);
682 assert(!"not reached");
683 inst
->src
[0] = src_reg(0.0f
);
686 inst
->src
[1] = src_reg();
688 } else if (inst
->src
[1].is_one()) {
689 inst
->opcode
= BRW_OPCODE_MOV
;
690 inst
->src
[1] = src_reg();
700 invalidate_live_intervals();
706 * Only a limited number of hardware registers may be used for push
707 * constants, so this turns access to the overflowed constants into
711 vec4_visitor::move_push_constants_to_pull_constants()
713 int pull_constant_loc
[this->uniforms
];
715 /* Only allow 32 registers (256 uniform components) as push constants,
716 * which is the limit on gen6.
718 int max_uniform_components
= 32 * 8;
719 if (this->uniforms
* 4 <= max_uniform_components
)
722 /* Make some sort of choice as to which uniforms get sent to pull
723 * constants. We could potentially do something clever here like
724 * look for the most infrequently used uniform vec4s, but leave
727 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
728 pull_constant_loc
[i
/ 4] = -1;
730 if (i
>= max_uniform_components
) {
731 const float **values
= &stage_prog_data
->param
[i
];
733 /* Try to find an existing copy of this uniform in the pull
734 * constants if it was part of an array access already.
736 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
739 for (matches
= 0; matches
< 4; matches
++) {
740 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
745 pull_constant_loc
[i
/ 4] = j
/ 4;
750 if (pull_constant_loc
[i
/ 4] == -1) {
751 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
752 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
754 for (int j
= 0; j
< 4; j
++) {
755 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
762 /* Now actually rewrite usage of the things we've moved to pull
765 foreach_list_safe(node
, &this->instructions
) {
766 vec4_instruction
*inst
= (vec4_instruction
*)node
;
768 for (int i
= 0 ; i
< 3; i
++) {
769 if (inst
->src
[i
].file
!= UNIFORM
||
770 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
773 int uniform
= inst
->src
[i
].reg
;
775 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
777 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
778 pull_constant_loc
[uniform
]);
780 inst
->src
[i
].file
= temp
.file
;
781 inst
->src
[i
].reg
= temp
.reg
;
782 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
783 inst
->src
[i
].reladdr
= NULL
;
787 /* Repack push constants to remove the now-unused ones. */
788 pack_uniform_registers();
792 * Sets the dependency control fields on instructions after register
793 * allocation and before the generator is run.
795 * When you have a sequence of instructions like:
797 * DP4 temp.x vertex uniform[0]
798 * DP4 temp.y vertex uniform[0]
799 * DP4 temp.z vertex uniform[0]
800 * DP4 temp.w vertex uniform[0]
802 * The hardware doesn't know that it can actually run the later instructions
803 * while the previous ones are in flight, producing stalls. However, we have
804 * manual fields we can set in the instructions that let it do so.
807 vec4_visitor::opt_set_dependency_control()
809 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
810 uint8_t grf_channels_written
[BRW_MAX_GRF
];
811 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
812 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
814 cfg_t
cfg(&instructions
);
816 assert(prog_data
->total_grf
||
817 !"Must be called after register allocation");
819 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
820 bblock_t
*bblock
= cfg
.blocks
[i
];
821 vec4_instruction
*inst
;
823 memset(last_grf_write
, 0, sizeof(last_grf_write
));
824 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
826 for (inst
= (vec4_instruction
*)bblock
->start
;
827 inst
!= (vec4_instruction
*)bblock
->end
->next
;
828 inst
= (vec4_instruction
*)inst
->next
) {
829 /* If we read from a register that we were doing dependency control
830 * on, don't do dependency control across the read.
832 for (int i
= 0; i
< 3; i
++) {
833 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
834 if (inst
->src
[i
].file
== GRF
) {
835 last_grf_write
[reg
] = NULL
;
836 } else if (inst
->src
[i
].file
== HW_REG
) {
837 memset(last_grf_write
, 0, sizeof(last_grf_write
));
840 assert(inst
->src
[i
].file
!= MRF
);
843 /* In the presence of send messages, totally interrupt dependency
844 * control. They're long enough that the chance of dependency
845 * control around them just doesn't matter.
848 memset(last_grf_write
, 0, sizeof(last_grf_write
));
849 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
853 /* It looks like setting dependency control on a predicated
854 * instruction hangs the GPU.
856 if (inst
->predicate
) {
857 memset(last_grf_write
, 0, sizeof(last_grf_write
));
858 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
862 /* Dependency control does not work well over math instructions.
864 if (inst
->is_math()) {
865 memset(last_grf_write
, 0, sizeof(last_grf_write
));
866 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
870 /* Now, see if we can do dependency control for this instruction
871 * against a previous one writing to its destination.
873 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
874 if (inst
->dst
.file
== GRF
) {
875 if (last_grf_write
[reg
] &&
876 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
877 last_grf_write
[reg
]->no_dd_clear
= true;
878 inst
->no_dd_check
= true;
880 grf_channels_written
[reg
] = 0;
883 last_grf_write
[reg
] = inst
;
884 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
885 } else if (inst
->dst
.file
== MRF
) {
886 if (last_mrf_write
[reg
] &&
887 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
888 last_mrf_write
[reg
]->no_dd_clear
= true;
889 inst
->no_dd_check
= true;
891 mrf_channels_written
[reg
] = 0;
894 last_mrf_write
[reg
] = inst
;
895 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
896 } else if (inst
->dst
.reg
== HW_REG
) {
897 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
898 memset(last_grf_write
, 0, sizeof(last_grf_write
));
899 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
900 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
907 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
911 /* If this instruction sets anything not referenced by swizzle, then we'd
912 * totally break it when we reswizzle.
914 if (dst
.writemask
& ~swizzle_mask
)
923 /* Check if there happens to be no reswizzling required. */
924 for (int c
= 0; c
< 4; c
++) {
925 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
926 /* Skip components of the swizzle not used by the dst. */
927 if (!(dst_writemask
& (1 << c
)))
930 /* We don't do the reswizzling yet, so just sanity check that we
941 * For any channels in the swizzle's source that were populated by this
942 * instruction, rewrite the instruction to put the appropriate result directly
945 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
948 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
950 int new_writemask
= 0;
956 for (int c
= 0; c
< 4; c
++) {
957 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
958 /* Skip components of the swizzle not used by the dst. */
959 if (!(dst_writemask
& (1 << c
)))
961 /* If we were populating this component, then populate the
962 * corresponding channel of the new dst.
964 if (dst
.writemask
& bit
)
965 new_writemask
|= (1 << c
);
967 dst
.writemask
= new_writemask
;
970 for (int c
= 0; c
< 4; c
++) {
971 /* Skip components of the swizzle not used by the dst. */
972 if (!(dst_writemask
& (1 << c
)))
975 /* We don't do the reswizzling yet, so just sanity check that we
978 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
985 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
986 * just written and then MOVed into another reg and making the original write
987 * of the GRF write directly to the final destination instead.
990 vec4_visitor::opt_register_coalesce()
992 bool progress
= false;
995 calculate_live_intervals();
997 foreach_list_safe(node
, &this->instructions
) {
998 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1003 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1004 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1006 inst
->src
[0].file
!= GRF
||
1007 inst
->dst
.type
!= inst
->src
[0].type
||
1008 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1011 bool to_mrf
= (inst
->dst
.file
== MRF
);
1013 /* Can't coalesce this GRF if someone else was going to
1016 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1017 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1018 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1019 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1022 /* We need to check interference with the final destination between this
1023 * instruction and the earliest instruction involved in writing the GRF
1024 * we're eliminating. To do that, keep track of which of our source
1025 * channels we've seen initialized.
1027 bool chans_needed
[4] = {false, false, false, false};
1028 int chans_remaining
= 0;
1029 int swizzle_mask
= 0;
1030 for (int i
= 0; i
< 4; i
++) {
1031 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1033 if (!(inst
->dst
.writemask
& (1 << i
)))
1036 swizzle_mask
|= (1 << chan
);
1038 if (!chans_needed
[chan
]) {
1039 chans_needed
[chan
] = true;
1044 /* Now walk up the instruction stream trying to see if we can rewrite
1045 * everything writing to the temporary to write into the destination
1048 vec4_instruction
*scan_inst
;
1049 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
1050 scan_inst
->prev
!= NULL
;
1051 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
1052 if (scan_inst
->dst
.file
== GRF
&&
1053 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1054 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1055 /* Found something writing to the reg we want to coalesce away. */
1057 /* SEND instructions can't have MRF as a destination. */
1058 if (scan_inst
->mlen
)
1061 if (brw
->gen
== 6) {
1062 /* gen6 math instructions must have the destination be
1063 * GRF, so no compute-to-MRF for them.
1065 if (scan_inst
->is_math()) {
1071 /* If we can't handle the swizzle, bail. */
1072 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
1073 inst
->src
[0].swizzle
,
1078 /* Mark which channels we found unconditional writes for. */
1079 if (!scan_inst
->predicate
) {
1080 for (int i
= 0; i
< 4; i
++) {
1081 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1083 chans_needed
[i
] = false;
1089 if (chans_remaining
== 0)
1093 /* We don't handle flow control here. Most computation of values
1094 * that could be coalesced happens just before their use.
1096 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1097 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1098 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1099 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1103 /* You can't read from an MRF, so if someone else reads our MRF's
1104 * source GRF that we wanted to rewrite, that stops us. If it's a
1105 * GRF we're trying to coalesce to, we don't actually handle
1106 * rewriting sources so bail in that case as well.
1108 bool interfered
= false;
1109 for (int i
= 0; i
< 3; i
++) {
1110 if (scan_inst
->src
[i
].file
== GRF
&&
1111 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1112 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1119 /* If somebody else writes our destination here, we can't coalesce
1122 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1123 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1127 /* Check for reads of the register we're trying to coalesce into. We
1128 * can't go rewriting instructions above that to put some other value
1129 * in the register instead.
1131 if (to_mrf
&& scan_inst
->mlen
> 0) {
1132 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1133 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1137 for (int i
= 0; i
< 3; i
++) {
1138 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1139 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1140 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1149 if (chans_remaining
== 0) {
1150 /* If we've made it here, we have an MOV we want to coalesce out, and
1151 * a scan_inst pointing to the earliest instruction involved in
1152 * computing the value. Now go rewrite the instruction stream
1156 while (scan_inst
!= inst
) {
1157 if (scan_inst
->dst
.file
== GRF
&&
1158 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1159 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1160 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1161 inst
->src
[0].swizzle
);
1162 scan_inst
->dst
.file
= inst
->dst
.file
;
1163 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1164 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1165 scan_inst
->saturate
|= inst
->saturate
;
1167 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1175 invalidate_live_intervals();
1181 * Splits virtual GRFs requesting more than one contiguous physical register.
1183 * We initially create large virtual GRFs for temporary structures, arrays,
1184 * and matrices, so that the dereference visitor functions can add reg_offsets
1185 * to work their way down to the actual member being accessed. But when it
1186 * comes to optimization, we'd like to treat each register as individual
1187 * storage if possible.
1189 * So far, the only thing that might prevent splitting is a send message from
1193 vec4_visitor::split_virtual_grfs()
1195 int num_vars
= this->virtual_grf_count
;
1196 int new_virtual_grf
[num_vars
];
1197 bool split_grf
[num_vars
];
1199 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1201 /* Try to split anything > 0 sized. */
1202 for (int i
= 0; i
< num_vars
; i
++) {
1203 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1206 /* Check that the instructions are compatible with the registers we're trying
1209 foreach_list(node
, &this->instructions
) {
1210 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1212 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1215 if (inst
->is_send_from_grf()) {
1216 for (int i
= 0; i
< 3; i
++) {
1217 if (inst
->src
[i
].file
== GRF
) {
1218 split_grf
[inst
->src
[i
].reg
] = false;
1224 /* Allocate new space for split regs. Note that the virtual
1225 * numbers will be contiguous.
1227 for (int i
= 0; i
< num_vars
; i
++) {
1231 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1232 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1233 int reg
= virtual_grf_alloc(1);
1234 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1237 this->virtual_grf_sizes
[i
] = 1;
1240 foreach_list(node
, &this->instructions
) {
1241 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1243 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1244 inst
->dst
.reg_offset
!= 0) {
1245 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1246 inst
->dst
.reg_offset
- 1);
1247 inst
->dst
.reg_offset
= 0;
1249 for (int i
= 0; i
< 3; i
++) {
1250 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1251 inst
->src
[i
].reg_offset
!= 0) {
1252 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1253 inst
->src
[i
].reg_offset
- 1);
1254 inst
->src
[i
].reg_offset
= 0;
1258 invalidate_live_intervals();
1262 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1264 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1266 if (inst
->predicate
) {
1267 fprintf(stderr
, "(%cf0) ",
1268 inst
->predicate_inverse
? '-' : '+');
1271 fprintf(stderr
, "%s", brw_instruction_name(inst
->opcode
));
1272 if (inst
->conditional_mod
) {
1273 fprintf(stderr
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1275 fprintf(stderr
, " ");
1277 switch (inst
->dst
.file
) {
1279 fprintf(stderr
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1282 fprintf(stderr
, "m%d", inst
->dst
.reg
);
1285 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1286 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1288 fprintf(stderr
, "null");
1290 case BRW_ARF_ADDRESS
:
1291 fprintf(stderr
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1293 case BRW_ARF_ACCUMULATOR
:
1294 fprintf(stderr
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1297 fprintf(stderr
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1298 inst
->dst
.fixed_hw_reg
.subnr
);
1301 fprintf(stderr
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1302 inst
->dst
.fixed_hw_reg
.subnr
);
1306 fprintf(stderr
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1308 if (inst
->dst
.fixed_hw_reg
.subnr
)
1309 fprintf(stderr
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1312 fprintf(stderr
, "(null)");
1315 fprintf(stderr
, "???");
1318 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1319 fprintf(stderr
, ".");
1320 if (inst
->dst
.writemask
& 1)
1321 fprintf(stderr
, "x");
1322 if (inst
->dst
.writemask
& 2)
1323 fprintf(stderr
, "y");
1324 if (inst
->dst
.writemask
& 4)
1325 fprintf(stderr
, "z");
1326 if (inst
->dst
.writemask
& 8)
1327 fprintf(stderr
, "w");
1329 fprintf(stderr
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
1331 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1332 if (inst
->src
[i
].negate
)
1333 fprintf(stderr
, "-");
1334 if (inst
->src
[i
].abs
)
1335 fprintf(stderr
, "|");
1336 switch (inst
->src
[i
].file
) {
1338 fprintf(stderr
, "vgrf%d", inst
->src
[i
].reg
);
1341 fprintf(stderr
, "attr%d", inst
->src
[i
].reg
);
1344 fprintf(stderr
, "u%d", inst
->src
[i
].reg
);
1347 switch (inst
->src
[i
].type
) {
1348 case BRW_REGISTER_TYPE_F
:
1349 fprintf(stderr
, "%fF", inst
->src
[i
].imm
.f
);
1351 case BRW_REGISTER_TYPE_D
:
1352 fprintf(stderr
, "%dD", inst
->src
[i
].imm
.i
);
1354 case BRW_REGISTER_TYPE_UD
:
1355 fprintf(stderr
, "%uU", inst
->src
[i
].imm
.u
);
1358 fprintf(stderr
, "???");
1363 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1364 fprintf(stderr
, "-");
1365 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1366 fprintf(stderr
, "|");
1367 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1368 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1370 fprintf(stderr
, "null");
1372 case BRW_ARF_ADDRESS
:
1373 fprintf(stderr
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1375 case BRW_ARF_ACCUMULATOR
:
1376 fprintf(stderr
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1379 fprintf(stderr
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1380 inst
->src
[i
].fixed_hw_reg
.subnr
);
1383 fprintf(stderr
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1384 inst
->src
[i
].fixed_hw_reg
.subnr
);
1388 fprintf(stderr
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1390 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1391 fprintf(stderr
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1392 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1393 fprintf(stderr
, "|");
1396 fprintf(stderr
, "(null)");
1399 fprintf(stderr
, "???");
1403 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1404 fprintf(stderr
, ".%d", inst
->src
[i
].reg_offset
);
1406 if (inst
->src
[i
].file
!= IMM
) {
1407 static const char *chans
[4] = {"x", "y", "z", "w"};
1408 fprintf(stderr
, ".");
1409 for (int c
= 0; c
< 4; c
++) {
1410 fprintf(stderr
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1414 if (inst
->src
[i
].abs
)
1415 fprintf(stderr
, "|");
1417 if (inst
->src
[i
].file
!= IMM
) {
1418 fprintf(stderr
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1421 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1422 fprintf(stderr
, ", ");
1425 fprintf(stderr
, "\n");
1429 static inline struct brw_reg
1430 attribute_to_hw_reg(int attr
, bool interleaved
)
1433 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1435 return brw_vec8_grf(attr
, 0);
1440 * Replace each register of type ATTR in this->instructions with a reference
1441 * to a fixed HW register.
1443 * If interleaved is true, then each attribute takes up half a register, with
1444 * register N containing attribute 2*N in its first half and attribute 2*N+1
1445 * in its second half (this corresponds to the payload setup used by geometry
1446 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1447 * false, then each attribute takes up a whole register, with register N
1448 * containing attribute N (this corresponds to the payload setup used by
1449 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1452 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1455 foreach_list(node
, &this->instructions
) {
1456 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1458 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1459 if (inst
->dst
.file
== ATTR
) {
1460 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1462 /* All attributes used in the shader need to have been assigned a
1463 * hardware register by the caller
1467 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1468 reg
.type
= inst
->dst
.type
;
1469 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1471 inst
->dst
.file
= HW_REG
;
1472 inst
->dst
.fixed_hw_reg
= reg
;
1475 for (int i
= 0; i
< 3; i
++) {
1476 if (inst
->src
[i
].file
!= ATTR
)
1479 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1481 /* All attributes used in the shader need to have been assigned a
1482 * hardware register by the caller
1486 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1487 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1488 reg
.type
= inst
->src
[i
].type
;
1489 if (inst
->src
[i
].abs
)
1491 if (inst
->src
[i
].negate
)
1494 inst
->src
[i
].file
= HW_REG
;
1495 inst
->src
[i
].fixed_hw_reg
= reg
;
1501 vec4_vs_visitor::setup_attributes(int payload_reg
)
1504 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1505 memset(attribute_map
, 0, sizeof(attribute_map
));
1508 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1509 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1510 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1515 /* VertexID is stored by the VF as the last vertex element, but we
1516 * don't represent it with a flag in inputs_read, so we call it
1519 if (vs_prog_data
->uses_vertexid
) {
1520 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1524 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1526 /* The BSpec says we always have to read at least one thing from
1527 * the VF, and it appears that the hardware wedges otherwise.
1529 if (nr_attributes
== 0)
1532 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1534 unsigned vue_entries
=
1535 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1538 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1540 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1542 return payload_reg
+ nr_attributes
;
1546 vec4_visitor::setup_uniforms(int reg
)
1548 prog_data
->dispatch_grf_start_reg
= reg
;
1550 /* The pre-gen6 VS requires that some push constants get loaded no
1551 * matter what, or the GPU would hang.
1553 if (brw
->gen
< 6 && this->uniforms
== 0) {
1554 assert(this->uniforms
< this->uniform_array_size
);
1555 this->uniform_vector_size
[this->uniforms
] = 1;
1557 stage_prog_data
->param
=
1558 reralloc(NULL
, stage_prog_data
->param
, const float *, 4);
1559 for (unsigned int i
= 0; i
< 4; i
++) {
1560 unsigned int slot
= this->uniforms
* 4 + i
;
1561 static float zero
= 0.0;
1562 stage_prog_data
->param
[slot
] = &zero
;
1568 reg
+= ALIGN(uniforms
, 2) / 2;
1571 stage_prog_data
->nr_params
= this->uniforms
* 4;
1573 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1579 vec4_vs_visitor::setup_payload(void)
1583 /* The payload always contains important data in g0, which contains
1584 * the URB handles that are passed on to the URB write at the end
1585 * of the thread. So, we always start push constants at g1.
1589 reg
= setup_uniforms(reg
);
1591 reg
= setup_attributes(reg
);
1593 this->first_non_payload_grf
= reg
;
1597 vec4_visitor::get_timestamp()
1599 assert(brw
->gen
>= 7);
1601 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1604 BRW_REGISTER_TYPE_UD
,
1605 BRW_VERTICAL_STRIDE_0
,
1607 BRW_HORIZONTAL_STRIDE_4
,
1611 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1613 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1614 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1615 * even if it's not enabled in the dispatch.
1617 mov
->force_writemask_all
= true;
1619 return src_reg(dst
);
1623 vec4_visitor::emit_shader_time_begin()
1625 current_annotation
= "shader time start";
1626 shader_start_time
= get_timestamp();
1630 vec4_visitor::emit_shader_time_end()
1632 current_annotation
= "shader time end";
1633 src_reg shader_end_time
= get_timestamp();
1636 /* Check that there weren't any timestamp reset events (assuming these
1637 * were the only two timestamp reads that happened).
1639 src_reg reset_end
= shader_end_time
;
1640 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1641 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1642 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1644 emit(IF(BRW_PREDICATE_NORMAL
));
1646 /* Take the current timestamp and get the delta. */
1647 shader_start_time
.negate
= true;
1648 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1649 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1651 /* If there were no instructions between the two timestamp gets, the diff
1652 * is 2 cycles. Remove that overhead, so I can forget about that when
1653 * trying to determine the time taken for single instructions.
1655 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1657 emit_shader_time_write(st_base
, src_reg(diff
));
1658 emit_shader_time_write(st_written
, src_reg(1u));
1659 emit(BRW_OPCODE_ELSE
);
1660 emit_shader_time_write(st_reset
, src_reg(1u));
1661 emit(BRW_OPCODE_ENDIF
);
1665 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1668 int shader_time_index
=
1669 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1672 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1674 dst_reg offset
= dst
;
1678 offset
.type
= BRW_REGISTER_TYPE_UD
;
1679 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1681 time
.type
= BRW_REGISTER_TYPE_UD
;
1682 emit(MOV(time
, src_reg(value
)));
1684 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1690 sanity_param_count
= prog
->Parameters
->NumParameters
;
1692 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1693 emit_shader_time_begin();
1695 assign_common_binding_table_offsets(0);
1699 /* Generate VS IR for main(). (the visitor only descends into
1700 * functions called "main").
1703 visit_instructions(shader
->base
.ir
);
1705 emit_program_code();
1709 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1710 setup_uniform_clipplane_values();
1714 /* Before any optimization, push array accesses out to scratch
1715 * space where we need them to be. This pass may allocate new
1716 * virtual GRFs, so we want to do it early. It also makes sure
1717 * that we have reladdr computations available for CSE, since we'll
1718 * often do repeated subexpressions for those.
1721 move_grf_array_access_to_scratch();
1722 move_uniform_array_access_to_pull_constants();
1724 /* The ARB_vertex_program frontend emits pull constant loads directly
1725 * rather than using reladdr, so we don't need to walk through all the
1726 * instructions looking for things to move. There isn't anything.
1728 * We do still need to split things to vec4 size.
1730 split_uniform_registers();
1732 pack_uniform_registers();
1733 move_push_constants_to_pull_constants();
1734 split_virtual_grfs();
1739 progress
= dead_code_eliminate() || progress
;
1740 progress
= dead_control_flow_eliminate(this) || progress
;
1741 progress
= opt_copy_propagation() || progress
;
1742 progress
= opt_algebraic() || progress
;
1743 progress
= opt_register_coalesce() || progress
;
1753 /* Debug of register spilling: Go spill everything. */
1754 const int grf_count
= virtual_grf_count
;
1755 float spill_costs
[virtual_grf_count
];
1756 bool no_spill
[virtual_grf_count
];
1757 evaluate_spill_costs(spill_costs
, no_spill
);
1758 for (int i
= 0; i
< grf_count
; i
++) {
1765 while (!reg_allocate()) {
1770 opt_schedule_instructions();
1772 opt_set_dependency_control();
1774 /* If any state parameters were appended, then ParameterValues could have
1775 * been realloced, in which case the driver uniform storage set up by
1776 * _mesa_associate_uniform_storage() would point to freed memory. Make
1777 * sure that didn't happen.
1779 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1784 } /* namespace brw */
1789 * Compile a vertex shader.
1791 * Returns the final assembly and the program's size.
1794 brw_vs_emit(struct brw_context
*brw
,
1795 struct gl_shader_program
*prog
,
1796 struct brw_vs_compile
*c
,
1797 struct brw_vs_prog_data
*prog_data
,
1799 unsigned *final_assembly_size
)
1801 bool start_busy
= false;
1802 double start_time
= 0;
1804 if (unlikely(brw
->perf_debug
)) {
1805 start_busy
= (brw
->batch
.last_bo
&&
1806 drm_intel_bo_busy(brw
->batch
.last_bo
));
1807 start_time
= get_time();
1810 struct brw_shader
*shader
= NULL
;
1812 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1814 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1815 brw_dump_ir(brw
, "vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1817 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1820 prog
->LinkStatus
= false;
1821 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1824 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1830 const unsigned *assembly
= NULL
;
1831 if (brw
->gen
>= 8) {
1832 gen8_vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1833 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1834 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1836 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1837 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1838 assembly
= g
.generate_assembly(&v
.instructions
, final_assembly_size
);
1841 if (unlikely(brw
->perf_debug
) && shader
) {
1842 if (shader
->compiled_once
) {
1843 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1845 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1846 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1847 (get_time() - start_time
) * 1000);
1849 shader
->compiled_once
= true;
1857 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1858 struct brw_vec4_prog_key
*key
,
1859 GLuint id
, struct gl_program
*prog
)
1861 key
->program_string_id
= id
;
1862 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1864 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1865 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1866 if (prog
->ShadowSamplers
& (1 << i
)) {
1867 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1868 key
->tex
.swizzles
[i
] =
1869 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1871 /* Color sampler: assume no swizzling. */
1872 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;