2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_dead_control_flow.h"
31 #include "main/macros.h"
32 #include "main/shaderobj.h"
33 #include "program/prog_print.h"
34 #include "program/prog_parameter.h"
37 #define MAX_INSTRUCTION (1 << 30)
44 * Common helper for constructing swizzles. When only a subset of
45 * channels of a vec4 are used, we don't want to reference the other
46 * channels, as that will tell optimization passes that those other
50 swizzle_for_size(int size
)
52 static const unsigned size_swizzles
[4] = {
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
56 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
59 assert((size
>= 1) && (size
<= 4));
60 return size_swizzles
[size
- 1];
66 memset(this, 0, sizeof(*this));
68 this->file
= BAD_FILE
;
71 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= BRW_SWIZZLE_XYZW
;
83 /** Generic unset register constructor. */
89 src_reg::src_reg(float f
)
94 this->type
= BRW_REGISTER_TYPE_F
;
95 this->fixed_hw_reg
.dw1
.f
= f
;
98 src_reg::src_reg(uint32_t u
)
103 this->type
= BRW_REGISTER_TYPE_UD
;
104 this->fixed_hw_reg
.dw1
.ud
= u
;
107 src_reg::src_reg(int32_t i
)
112 this->type
= BRW_REGISTER_TYPE_D
;
113 this->fixed_hw_reg
.dw1
.d
= i
;
116 src_reg::src_reg(uint8_t vf
[4])
121 this->type
= BRW_REGISTER_TYPE_VF
;
122 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
125 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
130 this->type
= BRW_REGISTER_TYPE_VF
;
131 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
137 src_reg::src_reg(struct brw_reg reg
)
142 this->fixed_hw_reg
= reg
;
143 this->type
= reg
.type
;
146 src_reg::src_reg(dst_reg reg
)
150 this->file
= reg
.file
;
152 this->reg_offset
= reg
.reg_offset
;
153 this->type
= reg
.type
;
154 this->reladdr
= reg
.reladdr
;
155 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
161 for (int i
= 0; i
< 4; i
++) {
162 if (!(reg
.writemask
& (1 << i
)))
165 swizzles
[next_chan
++] = last
= i
;
168 for (; next_chan
< 4; next_chan
++) {
169 swizzles
[next_chan
] = last
;
172 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
173 swizzles
[2], swizzles
[3]);
179 memset(this, 0, sizeof(*this));
180 this->file
= BAD_FILE
;
181 this->writemask
= WRITEMASK_XYZW
;
189 dst_reg::dst_reg(register_file file
, int reg
)
197 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
204 this->type
= brw_type_for_base_type(type
);
205 this->writemask
= writemask
;
208 dst_reg::dst_reg(struct brw_reg reg
)
213 this->fixed_hw_reg
= reg
;
214 this->type
= reg
.type
;
217 dst_reg::dst_reg(src_reg reg
)
221 this->file
= reg
.file
;
223 this->reg_offset
= reg
.reg_offset
;
224 this->type
= reg
.type
;
225 /* How should we do writemasking when converting from a src_reg? It seems
226 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
227 * what about for src.wx? Just special-case src.xxxx for now.
229 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
230 this->writemask
= WRITEMASK_X
;
232 this->writemask
= WRITEMASK_XYZW
;
233 this->reladdr
= reg
.reladdr
;
234 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
238 vec4_instruction::is_send_from_grf()
241 case SHADER_OPCODE_SHADER_TIME_ADD
:
242 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
250 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
252 if (brw
->gen
== 6 && is_math())
255 if (is_send_from_grf())
258 if (!backend_instruction::can_do_source_mods())
265 * Returns how many MRFs an opcode will write over.
267 * Note that this is not the 0 or 1 implied writes in an actual gen
268 * instruction -- the generate_* functions generate additional MOVs
272 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
277 switch (inst
->opcode
) {
278 case SHADER_OPCODE_RCP
:
279 case SHADER_OPCODE_RSQ
:
280 case SHADER_OPCODE_SQRT
:
281 case SHADER_OPCODE_EXP2
:
282 case SHADER_OPCODE_LOG2
:
283 case SHADER_OPCODE_SIN
:
284 case SHADER_OPCODE_COS
:
286 case SHADER_OPCODE_INT_QUOTIENT
:
287 case SHADER_OPCODE_INT_REMAINDER
:
288 case SHADER_OPCODE_POW
:
290 case VS_OPCODE_URB_WRITE
:
292 case VS_OPCODE_PULL_CONSTANT_LOAD
:
294 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
296 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
298 case GS_OPCODE_URB_WRITE
:
299 case GS_OPCODE_URB_WRITE_ALLOCATE
:
300 case GS_OPCODE_THREAD_END
:
302 case GS_OPCODE_FF_SYNC
:
304 case SHADER_OPCODE_SHADER_TIME_ADD
:
306 case SHADER_OPCODE_TEX
:
307 case SHADER_OPCODE_TXL
:
308 case SHADER_OPCODE_TXD
:
309 case SHADER_OPCODE_TXF
:
310 case SHADER_OPCODE_TXF_CMS
:
311 case SHADER_OPCODE_TXF_MCS
:
312 case SHADER_OPCODE_TXS
:
313 case SHADER_OPCODE_TG4
:
314 case SHADER_OPCODE_TG4_OFFSET
:
315 return inst
->header_present
? 1 : 0;
316 case SHADER_OPCODE_UNTYPED_ATOMIC
:
317 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
320 unreachable("not reached");
325 src_reg::equals(const src_reg
&r
) const
327 return (file
== r
.file
&&
329 reg_offset
== r
.reg_offset
&&
331 negate
== r
.negate
&&
333 swizzle
== r
.swizzle
&&
334 !reladdr
&& !r
.reladdr
&&
335 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
336 sizeof(fixed_hw_reg
)) == 0);
340 vec4_visitor::opt_vector_float()
342 bool progress
= false;
344 int last_reg
= -1, last_reg_offset
= -1;
345 enum register_file last_reg_file
= BAD_FILE
;
347 int remaining_channels
;
350 vec4_instruction
*imm_inst
[4];
352 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
353 if (last_reg
!= inst
->dst
.reg
||
354 last_reg_offset
!= inst
->dst
.reg_offset
||
355 last_reg_file
!= inst
->dst
.file
) {
356 last_reg
= inst
->dst
.reg
;
357 last_reg_offset
= inst
->dst
.reg_offset
;
358 last_reg_file
= inst
->dst
.file
;
359 remaining_channels
= WRITEMASK_XYZW
;
364 if (inst
->opcode
!= BRW_OPCODE_MOV
||
365 inst
->dst
.writemask
== WRITEMASK_XYZW
||
366 inst
->src
[0].file
!= IMM
)
369 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
373 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
375 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
377 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
379 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
382 imm_inst
[inst_count
++] = inst
;
384 remaining_channels
&= ~inst
->dst
.writemask
;
385 if (remaining_channels
== 0) {
386 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
387 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
388 mov
->dst
.writemask
= WRITEMASK_XYZW
;
389 inst
->insert_after(block
, mov
);
392 for (int i
= 0; i
< inst_count
; i
++) {
393 imm_inst
[i
]->remove(block
);
400 invalidate_live_intervals();
405 /* Replaces unused channels of a swizzle with channels that are used.
407 * For instance, this pass transforms
409 * mov vgrf4.yz, vgrf5.wxzy
413 * mov vgrf4.yz, vgrf5.xxzx
415 * This eliminates false uses of some channels, letting dead code elimination
416 * remove the instructions that wrote them.
419 vec4_visitor::opt_reduce_swizzle()
421 bool progress
= false;
423 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
424 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
)
429 /* Determine which channels of the sources are read. */
430 switch (inst
->opcode
) {
431 case VEC4_OPCODE_PACK_BYTES
:
438 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
439 * but all four of src1.
459 swizzle
[0] = inst
->dst
.writemask
& WRITEMASK_X
? 0 : -1;
460 swizzle
[1] = inst
->dst
.writemask
& WRITEMASK_Y
? 1 : -1;
461 swizzle
[2] = inst
->dst
.writemask
& WRITEMASK_Z
? 2 : -1;
462 swizzle
[3] = inst
->dst
.writemask
& WRITEMASK_W
? 3 : -1;
466 /* Resolve unread channels (-1) by assigning them the swizzle of the
467 * first channel that is used.
469 int first_used_channel
= 0;
470 for (int i
= 0; i
< 4; i
++) {
471 if (swizzle
[i
] != -1) {
472 first_used_channel
= swizzle
[i
];
476 for (int i
= 0; i
< 4; i
++) {
477 if (swizzle
[i
] == -1) {
478 swizzle
[i
] = first_used_channel
;
482 /* Update sources' swizzles. */
483 for (int i
= 0; i
< 3; i
++) {
484 if (inst
->src
[i
].file
!= GRF
&&
485 inst
->src
[i
].file
!= ATTR
&&
486 inst
->src
[i
].file
!= UNIFORM
)
490 for (int j
= 0; j
< 4; j
++) {
491 swiz
[j
] = BRW_GET_SWZ(inst
->src
[i
].swizzle
, swizzle
[j
]);
494 unsigned new_swizzle
= BRW_SWIZZLE4(swiz
[0], swiz
[1], swiz
[2], swiz
[3]);
495 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
496 inst
->src
[i
].swizzle
= new_swizzle
;
503 invalidate_live_intervals();
509 vec4_visitor::split_uniform_registers()
511 /* Prior to this, uniforms have been in an array sized according to
512 * the number of vector uniforms present, sparsely filled (so an
513 * aggregate results in reg indices being skipped over). Now we're
514 * going to cut those aggregates up so each .reg index is one
515 * vector. The goal is to make elimination of unused uniform
516 * components easier later.
518 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
519 for (int i
= 0 ; i
< 3; i
++) {
520 if (inst
->src
[i
].file
!= UNIFORM
)
523 assert(!inst
->src
[i
].reladdr
);
525 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
526 inst
->src
[i
].reg_offset
= 0;
530 /* Update that everything is now vector-sized. */
531 for (int i
= 0; i
< this->uniforms
; i
++) {
532 this->uniform_size
[i
] = 1;
537 vec4_visitor::pack_uniform_registers()
539 bool uniform_used
[this->uniforms
];
540 int new_loc
[this->uniforms
];
541 int new_chan
[this->uniforms
];
543 memset(uniform_used
, 0, sizeof(uniform_used
));
544 memset(new_loc
, 0, sizeof(new_loc
));
545 memset(new_chan
, 0, sizeof(new_chan
));
547 /* Find which uniform vectors are actually used by the program. We
548 * expect unused vector elements when we've moved array access out
549 * to pull constants, and from some GLSL code generators like wine.
551 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
552 for (int i
= 0 ; i
< 3; i
++) {
553 if (inst
->src
[i
].file
!= UNIFORM
)
556 uniform_used
[inst
->src
[i
].reg
] = true;
560 int new_uniform_count
= 0;
562 /* Now, figure out a packing of the live uniform vectors into our
565 for (int src
= 0; src
< uniforms
; src
++) {
566 assert(src
< uniform_array_size
);
567 int size
= this->uniform_vector_size
[src
];
569 if (!uniform_used
[src
]) {
570 this->uniform_vector_size
[src
] = 0;
575 /* Find the lowest place we can slot this uniform in. */
576 for (dst
= 0; dst
< src
; dst
++) {
577 if (this->uniform_vector_size
[dst
] + size
<= 4)
586 new_chan
[src
] = this->uniform_vector_size
[dst
];
588 /* Move the references to the data */
589 for (int j
= 0; j
< size
; j
++) {
590 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
591 stage_prog_data
->param
[src
* 4 + j
];
594 this->uniform_vector_size
[dst
] += size
;
595 this->uniform_vector_size
[src
] = 0;
598 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
601 this->uniforms
= new_uniform_count
;
603 /* Now, update the instructions for our repacked uniforms. */
604 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
605 for (int i
= 0 ; i
< 3; i
++) {
606 int src
= inst
->src
[i
].reg
;
608 if (inst
->src
[i
].file
!= UNIFORM
)
611 inst
->src
[i
].reg
= new_loc
[src
];
613 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
614 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
615 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
616 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
617 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
623 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
625 * While GLSL IR also performs this optimization, we end up with it in
626 * our instruction stream for a couple of reasons. One is that we
627 * sometimes generate silly instructions, for example in array access
628 * where we'll generate "ADD offset, index, base" even if base is 0.
629 * The other is that GLSL IR's constant propagation doesn't track the
630 * components of aggregates, so some VS patterns (initialize matrix to
631 * 0, accumulate in vertex blending factors) end up breaking down to
632 * instructions involving 0.
635 vec4_visitor::opt_algebraic()
637 bool progress
= false;
639 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
640 switch (inst
->opcode
) {
642 if (inst
->src
[0].file
!= IMM
)
645 if (inst
->saturate
) {
646 if (inst
->dst
.type
!= inst
->src
[0].type
)
647 assert(!"unimplemented: saturate mixed types");
649 if (brw_saturate_immediate(inst
->dst
.type
,
650 &inst
->src
[0].fixed_hw_reg
)) {
651 inst
->saturate
= false;
657 case VEC4_OPCODE_UNPACK_UNIFORM
:
658 if (inst
->src
[0].file
!= UNIFORM
) {
659 inst
->opcode
= BRW_OPCODE_MOV
;
665 if (inst
->src
[1].is_zero()) {
666 inst
->opcode
= BRW_OPCODE_MOV
;
667 inst
->src
[1] = src_reg();
673 if (inst
->src
[1].is_zero()) {
674 inst
->opcode
= BRW_OPCODE_MOV
;
675 switch (inst
->src
[0].type
) {
676 case BRW_REGISTER_TYPE_F
:
677 inst
->src
[0] = src_reg(0.0f
);
679 case BRW_REGISTER_TYPE_D
:
680 inst
->src
[0] = src_reg(0);
682 case BRW_REGISTER_TYPE_UD
:
683 inst
->src
[0] = src_reg(0u);
686 unreachable("not reached");
688 inst
->src
[1] = src_reg();
690 } else if (inst
->src
[1].is_one()) {
691 inst
->opcode
= BRW_OPCODE_MOV
;
692 inst
->src
[1] = src_reg();
697 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
699 inst
->src
[0].negate
&&
700 inst
->src
[1].is_zero()) {
701 inst
->src
[0].abs
= false;
702 inst
->src
[0].negate
= false;
703 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
708 case SHADER_OPCODE_RCP
: {
709 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
710 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
711 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
712 inst
->opcode
= SHADER_OPCODE_RSQ
;
713 inst
->src
[0] = prev
->src
[0];
725 invalidate_live_intervals();
731 * Only a limited number of hardware registers may be used for push
732 * constants, so this turns access to the overflowed constants into
736 vec4_visitor::move_push_constants_to_pull_constants()
738 int pull_constant_loc
[this->uniforms
];
740 /* Only allow 32 registers (256 uniform components) as push constants,
741 * which is the limit on gen6.
743 * If changing this value, note the limitation about total_regs in
746 int max_uniform_components
= 32 * 8;
747 if (this->uniforms
* 4 <= max_uniform_components
)
750 /* Make some sort of choice as to which uniforms get sent to pull
751 * constants. We could potentially do something clever here like
752 * look for the most infrequently used uniform vec4s, but leave
755 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
756 pull_constant_loc
[i
/ 4] = -1;
758 if (i
>= max_uniform_components
) {
759 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
761 /* Try to find an existing copy of this uniform in the pull
762 * constants if it was part of an array access already.
764 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
767 for (matches
= 0; matches
< 4; matches
++) {
768 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
773 pull_constant_loc
[i
/ 4] = j
/ 4;
778 if (pull_constant_loc
[i
/ 4] == -1) {
779 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
780 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
782 for (int j
= 0; j
< 4; j
++) {
783 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
790 /* Now actually rewrite usage of the things we've moved to pull
793 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
794 for (int i
= 0 ; i
< 3; i
++) {
795 if (inst
->src
[i
].file
!= UNIFORM
||
796 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
799 int uniform
= inst
->src
[i
].reg
;
801 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
803 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
804 pull_constant_loc
[uniform
]);
806 inst
->src
[i
].file
= temp
.file
;
807 inst
->src
[i
].reg
= temp
.reg
;
808 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
809 inst
->src
[i
].reladdr
= NULL
;
813 /* Repack push constants to remove the now-unused ones. */
814 pack_uniform_registers();
817 /* Conditions for which we want to avoid setting the dependency control bits */
819 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
821 #define IS_DWORD(reg) \
822 (reg.type == BRW_REGISTER_TYPE_UD || \
823 reg.type == BRW_REGISTER_TYPE_D)
825 /* "When source or destination datatype is 64b or operation is integer DWord
826 * multiply, DepCtrl must not be used."
827 * May apply to future SoCs as well.
829 if (brw
->is_cherryview
) {
830 if (inst
->opcode
== BRW_OPCODE_MUL
&&
831 IS_DWORD(inst
->src
[0]) &&
832 IS_DWORD(inst
->src
[1]))
839 * In the presence of send messages, totally interrupt dependency
840 * control. They're long enough that the chance of dependency
841 * control around them just doesn't matter.
844 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
845 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
846 * completes the scoreboard clear must have a non-zero execution mask. This
847 * means, if any kind of predication can change the execution mask or channel
848 * enable of the last instruction, the optimization must be avoided. This is
849 * to avoid instructions being shot down the pipeline when no writes are
853 * Dependency control does not work well over math instructions.
854 * NB: Discovered empirically
856 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
860 * Sets the dependency control fields on instructions after register
861 * allocation and before the generator is run.
863 * When you have a sequence of instructions like:
865 * DP4 temp.x vertex uniform[0]
866 * DP4 temp.y vertex uniform[0]
867 * DP4 temp.z vertex uniform[0]
868 * DP4 temp.w vertex uniform[0]
870 * The hardware doesn't know that it can actually run the later instructions
871 * while the previous ones are in flight, producing stalls. However, we have
872 * manual fields we can set in the instructions that let it do so.
875 vec4_visitor::opt_set_dependency_control()
877 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
878 uint8_t grf_channels_written
[BRW_MAX_GRF
];
879 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
880 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
882 assert(prog_data
->total_grf
||
883 !"Must be called after register allocation");
885 foreach_block (block
, cfg
) {
886 memset(last_grf_write
, 0, sizeof(last_grf_write
));
887 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
889 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
890 /* If we read from a register that we were doing dependency control
891 * on, don't do dependency control across the read.
893 for (int i
= 0; i
< 3; i
++) {
894 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
895 if (inst
->src
[i
].file
== GRF
) {
896 last_grf_write
[reg
] = NULL
;
897 } else if (inst
->src
[i
].file
== HW_REG
) {
898 memset(last_grf_write
, 0, sizeof(last_grf_write
));
901 assert(inst
->src
[i
].file
!= MRF
);
904 if (is_dep_ctrl_unsafe(inst
)) {
905 memset(last_grf_write
, 0, sizeof(last_grf_write
));
906 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
910 /* Now, see if we can do dependency control for this instruction
911 * against a previous one writing to its destination.
913 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
914 if (inst
->dst
.file
== GRF
) {
915 if (last_grf_write
[reg
] &&
916 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
917 last_grf_write
[reg
]->no_dd_clear
= true;
918 inst
->no_dd_check
= true;
920 grf_channels_written
[reg
] = 0;
923 last_grf_write
[reg
] = inst
;
924 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
925 } else if (inst
->dst
.file
== MRF
) {
926 if (last_mrf_write
[reg
] &&
927 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
928 last_mrf_write
[reg
]->no_dd_clear
= true;
929 inst
->no_dd_check
= true;
931 mrf_channels_written
[reg
] = 0;
934 last_mrf_write
[reg
] = inst
;
935 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
936 } else if (inst
->dst
.reg
== HW_REG
) {
937 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
938 memset(last_grf_write
, 0, sizeof(last_grf_write
));
939 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
940 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
947 vec4_instruction::can_reswizzle(int dst_writemask
,
951 /* If this instruction sets anything not referenced by swizzle, then we'd
952 * totally break it when we reswizzle.
954 if (dst
.writemask
& ~swizzle_mask
)
964 * For any channels in the swizzle's source that were populated by this
965 * instruction, rewrite the instruction to put the appropriate result directly
968 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
971 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
973 int new_writemask
= 0;
974 int new_swizzle
[4] = { 0 };
976 /* Dot product instructions write a single result into all channels. */
977 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
978 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
) {
979 for (int i
= 0; i
< 3; i
++) {
980 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
983 /* Destination write mask doesn't correspond to source swizzle for the
984 * pack_bytes instruction.
986 if (opcode
== VEC4_OPCODE_PACK_BYTES
)
989 for (int c
= 0; c
< 4; c
++) {
990 new_swizzle
[c
] = BRW_GET_SWZ(src
[i
].swizzle
, BRW_GET_SWZ(swizzle
, c
));
993 src
[i
].swizzle
= BRW_SWIZZLE4(new_swizzle
[0], new_swizzle
[1],
994 new_swizzle
[2], new_swizzle
[3]);
998 for (int c
= 0; c
< 4; c
++) {
999 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
1000 /* Skip components of the swizzle not used by the dst. */
1001 if (!(dst_writemask
& (1 << c
)))
1003 /* If we were populating this component, then populate the
1004 * corresponding channel of the new dst.
1006 if (dst
.writemask
& bit
)
1007 new_writemask
|= (1 << c
);
1009 dst
.writemask
= new_writemask
;
1013 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1014 * just written and then MOVed into another reg and making the original write
1015 * of the GRF write directly to the final destination instead.
1018 vec4_visitor::opt_register_coalesce()
1020 bool progress
= false;
1023 calculate_live_intervals();
1025 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1029 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1030 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1032 inst
->src
[0].file
!= GRF
||
1033 inst
->dst
.type
!= inst
->src
[0].type
||
1034 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1037 bool to_mrf
= (inst
->dst
.file
== MRF
);
1039 /* Can't coalesce this GRF if someone else was going to
1042 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1043 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1044 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1045 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1048 /* We need to check interference with the final destination between this
1049 * instruction and the earliest instruction involved in writing the GRF
1050 * we're eliminating. To do that, keep track of which of our source
1051 * channels we've seen initialized.
1053 bool chans_needed
[4] = {false, false, false, false};
1054 int chans_remaining
= 0;
1055 int swizzle_mask
= 0;
1056 for (int i
= 0; i
< 4; i
++) {
1057 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1059 if (!(inst
->dst
.writemask
& (1 << i
)))
1062 swizzle_mask
|= (1 << chan
);
1064 if (!chans_needed
[chan
]) {
1065 chans_needed
[chan
] = true;
1070 /* Now walk up the instruction stream trying to see if we can rewrite
1071 * everything writing to the temporary to write into the destination
1074 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1075 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1077 _scan_inst
= scan_inst
;
1079 if (scan_inst
->dst
.file
== GRF
&&
1080 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1081 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1082 /* Found something writing to the reg we want to coalesce away. */
1084 /* SEND instructions can't have MRF as a destination. */
1085 if (scan_inst
->mlen
)
1088 if (brw
->gen
== 6) {
1089 /* gen6 math instructions must have the destination be
1090 * GRF, so no compute-to-MRF for them.
1092 if (scan_inst
->is_math()) {
1098 /* If we can't handle the swizzle, bail. */
1099 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1100 inst
->src
[0].swizzle
,
1105 /* Mark which channels we found unconditional writes for. */
1106 if (!scan_inst
->predicate
) {
1107 for (int i
= 0; i
< 4; i
++) {
1108 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1110 chans_needed
[i
] = false;
1116 if (chans_remaining
== 0)
1120 /* You can't read from an MRF, so if someone else reads our MRF's
1121 * source GRF that we wanted to rewrite, that stops us. If it's a
1122 * GRF we're trying to coalesce to, we don't actually handle
1123 * rewriting sources so bail in that case as well.
1125 bool interfered
= false;
1126 for (int i
= 0; i
< 3; i
++) {
1127 if (scan_inst
->src
[i
].file
== GRF
&&
1128 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1129 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1136 /* If somebody else writes our destination here, we can't coalesce
1139 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1140 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1144 /* Check for reads of the register we're trying to coalesce into. We
1145 * can't go rewriting instructions above that to put some other value
1146 * in the register instead.
1148 if (to_mrf
&& scan_inst
->mlen
> 0) {
1149 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1150 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1154 for (int i
= 0; i
< 3; i
++) {
1155 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1156 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1157 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1166 if (chans_remaining
== 0) {
1167 /* If we've made it here, we have an MOV we want to coalesce out, and
1168 * a scan_inst pointing to the earliest instruction involved in
1169 * computing the value. Now go rewrite the instruction stream
1172 vec4_instruction
*scan_inst
= _scan_inst
;
1173 while (scan_inst
!= inst
) {
1174 if (scan_inst
->dst
.file
== GRF
&&
1175 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1176 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1177 scan_inst
->reswizzle(inst
->dst
.writemask
,
1178 inst
->src
[0].swizzle
);
1179 scan_inst
->dst
.file
= inst
->dst
.file
;
1180 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1181 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1182 scan_inst
->saturate
|= inst
->saturate
;
1184 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1186 inst
->remove(block
);
1192 invalidate_live_intervals();
1198 * Splits virtual GRFs requesting more than one contiguous physical register.
1200 * We initially create large virtual GRFs for temporary structures, arrays,
1201 * and matrices, so that the dereference visitor functions can add reg_offsets
1202 * to work their way down to the actual member being accessed. But when it
1203 * comes to optimization, we'd like to treat each register as individual
1204 * storage if possible.
1206 * So far, the only thing that might prevent splitting is a send message from
1210 vec4_visitor::split_virtual_grfs()
1212 int num_vars
= this->alloc
.count
;
1213 int new_virtual_grf
[num_vars
];
1214 bool split_grf
[num_vars
];
1216 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1218 /* Try to split anything > 0 sized. */
1219 for (int i
= 0; i
< num_vars
; i
++) {
1220 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1223 /* Check that the instructions are compatible with the registers we're trying
1226 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1227 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1230 if (inst
->is_send_from_grf()) {
1231 for (int i
= 0; i
< 3; i
++) {
1232 if (inst
->src
[i
].file
== GRF
) {
1233 split_grf
[inst
->src
[i
].reg
] = false;
1239 /* Allocate new space for split regs. Note that the virtual
1240 * numbers will be contiguous.
1242 for (int i
= 0; i
< num_vars
; i
++) {
1246 new_virtual_grf
[i
] = alloc
.allocate(1);
1247 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1248 unsigned reg
= alloc
.allocate(1);
1249 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1252 this->alloc
.sizes
[i
] = 1;
1255 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1256 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1257 inst
->dst
.reg_offset
!= 0) {
1258 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1259 inst
->dst
.reg_offset
- 1);
1260 inst
->dst
.reg_offset
= 0;
1262 for (int i
= 0; i
< 3; i
++) {
1263 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1264 inst
->src
[i
].reg_offset
!= 0) {
1265 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1266 inst
->src
[i
].reg_offset
- 1);
1267 inst
->src
[i
].reg_offset
= 0;
1271 invalidate_live_intervals();
1275 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1277 dump_instruction(be_inst
, stderr
);
1281 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1283 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1285 if (inst
->predicate
) {
1286 fprintf(file
, "(%cf0) ",
1287 inst
->predicate_inverse
? '-' : '+');
1290 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1291 if (inst
->conditional_mod
) {
1292 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1296 switch (inst
->dst
.file
) {
1298 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1301 fprintf(file
, "m%d", inst
->dst
.reg
);
1304 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1305 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1307 fprintf(file
, "null");
1309 case BRW_ARF_ADDRESS
:
1310 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1312 case BRW_ARF_ACCUMULATOR
:
1313 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1316 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1317 inst
->dst
.fixed_hw_reg
.subnr
);
1320 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1321 inst
->dst
.fixed_hw_reg
.subnr
);
1325 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1327 if (inst
->dst
.fixed_hw_reg
.subnr
)
1328 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1331 fprintf(file
, "(null)");
1334 fprintf(file
, "???");
1337 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1339 if (inst
->dst
.writemask
& 1)
1341 if (inst
->dst
.writemask
& 2)
1343 if (inst
->dst
.writemask
& 4)
1345 if (inst
->dst
.writemask
& 8)
1348 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1350 if (inst
->src
[0].file
!= BAD_FILE
)
1351 fprintf(file
, ", ");
1353 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1354 if (inst
->src
[i
].negate
)
1356 if (inst
->src
[i
].abs
)
1358 switch (inst
->src
[i
].file
) {
1360 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1363 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1366 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1369 switch (inst
->src
[i
].type
) {
1370 case BRW_REGISTER_TYPE_F
:
1371 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1373 case BRW_REGISTER_TYPE_D
:
1374 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1376 case BRW_REGISTER_TYPE_UD
:
1377 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1379 case BRW_REGISTER_TYPE_VF
:
1380 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1381 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1382 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1383 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1384 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1387 fprintf(file
, "???");
1392 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1394 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1396 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1397 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1399 fprintf(file
, "null");
1401 case BRW_ARF_ADDRESS
:
1402 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1404 case BRW_ARF_ACCUMULATOR
:
1405 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1408 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1409 inst
->src
[i
].fixed_hw_reg
.subnr
);
1412 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1413 inst
->src
[i
].fixed_hw_reg
.subnr
);
1417 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1419 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1420 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1421 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1425 fprintf(file
, "(null)");
1428 fprintf(file
, "???");
1432 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1433 if (inst
->src
[i
].reg_offset
!= 0 &&
1434 inst
->src
[i
].file
== GRF
&&
1435 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1436 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1438 if (inst
->src
[i
].file
!= IMM
) {
1439 static const char *chans
[4] = {"x", "y", "z", "w"};
1441 for (int c
= 0; c
< 4; c
++) {
1442 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1446 if (inst
->src
[i
].abs
)
1449 if (inst
->src
[i
].file
!= IMM
) {
1450 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1453 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1454 fprintf(file
, ", ");
1457 fprintf(file
, "\n");
1461 static inline struct brw_reg
1462 attribute_to_hw_reg(int attr
, bool interleaved
)
1465 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1467 return brw_vec8_grf(attr
, 0);
1472 * Replace each register of type ATTR in this->instructions with a reference
1473 * to a fixed HW register.
1475 * If interleaved is true, then each attribute takes up half a register, with
1476 * register N containing attribute 2*N in its first half and attribute 2*N+1
1477 * in its second half (this corresponds to the payload setup used by geometry
1478 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1479 * false, then each attribute takes up a whole register, with register N
1480 * containing attribute N (this corresponds to the payload setup used by
1481 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1484 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1487 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1488 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1489 if (inst
->dst
.file
== ATTR
) {
1490 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1492 /* All attributes used in the shader need to have been assigned a
1493 * hardware register by the caller
1497 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1498 reg
.type
= inst
->dst
.type
;
1499 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1501 inst
->dst
.file
= HW_REG
;
1502 inst
->dst
.fixed_hw_reg
= reg
;
1505 for (int i
= 0; i
< 3; i
++) {
1506 if (inst
->src
[i
].file
!= ATTR
)
1509 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1511 /* All attributes used in the shader need to have been assigned a
1512 * hardware register by the caller
1516 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1517 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1518 reg
.type
= inst
->src
[i
].type
;
1519 if (inst
->src
[i
].abs
)
1521 if (inst
->src
[i
].negate
)
1524 inst
->src
[i
].file
= HW_REG
;
1525 inst
->src
[i
].fixed_hw_reg
= reg
;
1531 vec4_vs_visitor::setup_attributes(int payload_reg
)
1534 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1535 memset(attribute_map
, 0, sizeof(attribute_map
));
1538 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1539 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1540 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1545 /* VertexID is stored by the VF as the last vertex element, but we
1546 * don't represent it with a flag in inputs_read, so we call it
1549 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1550 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1554 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1556 /* The BSpec says we always have to read at least one thing from
1557 * the VF, and it appears that the hardware wedges otherwise.
1559 if (nr_attributes
== 0)
1562 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1564 unsigned vue_entries
=
1565 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1568 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1570 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1572 return payload_reg
+ nr_attributes
;
1576 vec4_visitor::setup_uniforms(int reg
)
1578 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1580 /* The pre-gen6 VS requires that some push constants get loaded no
1581 * matter what, or the GPU would hang.
1583 if (brw
->gen
< 6 && this->uniforms
== 0) {
1584 assert(this->uniforms
< this->uniform_array_size
);
1585 this->uniform_vector_size
[this->uniforms
] = 1;
1587 stage_prog_data
->param
=
1588 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1589 for (unsigned int i
= 0; i
< 4; i
++) {
1590 unsigned int slot
= this->uniforms
* 4 + i
;
1591 static gl_constant_value zero
= { 0.0 };
1592 stage_prog_data
->param
[slot
] = &zero
;
1598 reg
+= ALIGN(uniforms
, 2) / 2;
1601 stage_prog_data
->nr_params
= this->uniforms
* 4;
1603 prog_data
->base
.curb_read_length
=
1604 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1610 vec4_vs_visitor::setup_payload(void)
1614 /* The payload always contains important data in g0, which contains
1615 * the URB handles that are passed on to the URB write at the end
1616 * of the thread. So, we always start push constants at g1.
1620 reg
= setup_uniforms(reg
);
1622 reg
= setup_attributes(reg
);
1624 this->first_non_payload_grf
= reg
;
1628 vec4_visitor::assign_binding_table_offsets()
1630 assign_common_binding_table_offsets(0);
1634 vec4_visitor::get_timestamp()
1636 assert(brw
->gen
>= 7);
1638 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1643 BRW_REGISTER_TYPE_UD
,
1644 BRW_VERTICAL_STRIDE_0
,
1646 BRW_HORIZONTAL_STRIDE_4
,
1650 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1652 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1653 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1654 * even if it's not enabled in the dispatch.
1656 mov
->force_writemask_all
= true;
1658 return src_reg(dst
);
1662 vec4_visitor::emit_shader_time_begin()
1664 current_annotation
= "shader time start";
1665 shader_start_time
= get_timestamp();
1669 vec4_visitor::emit_shader_time_end()
1671 current_annotation
= "shader time end";
1672 src_reg shader_end_time
= get_timestamp();
1675 /* Check that there weren't any timestamp reset events (assuming these
1676 * were the only two timestamp reads that happened).
1678 src_reg reset_end
= shader_end_time
;
1679 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1680 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1681 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1683 emit(IF(BRW_PREDICATE_NORMAL
));
1685 /* Take the current timestamp and get the delta. */
1686 shader_start_time
.negate
= true;
1687 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1688 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1690 /* If there were no instructions between the two timestamp gets, the diff
1691 * is 2 cycles. Remove that overhead, so I can forget about that when
1692 * trying to determine the time taken for single instructions.
1694 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1696 emit_shader_time_write(st_base
, src_reg(diff
));
1697 emit_shader_time_write(st_written
, src_reg(1u));
1698 emit(BRW_OPCODE_ELSE
);
1699 emit_shader_time_write(st_reset
, src_reg(1u));
1700 emit(BRW_OPCODE_ENDIF
);
1704 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1707 int shader_time_index
=
1708 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1711 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1713 dst_reg offset
= dst
;
1717 offset
.type
= BRW_REGISTER_TYPE_UD
;
1718 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1720 time
.type
= BRW_REGISTER_TYPE_UD
;
1721 emit(MOV(time
, src_reg(value
)));
1723 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1729 sanity_param_count
= prog
->Parameters
->NumParameters
;
1731 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1732 emit_shader_time_begin();
1734 assign_binding_table_offsets();
1738 /* Generate VS IR for main(). (the visitor only descends into
1739 * functions called "main").
1742 visit_instructions(shader
->base
.ir
);
1744 emit_program_code();
1748 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1749 setup_uniform_clipplane_values();
1755 /* Before any optimization, push array accesses out to scratch
1756 * space where we need them to be. This pass may allocate new
1757 * virtual GRFs, so we want to do it early. It also makes sure
1758 * that we have reladdr computations available for CSE, since we'll
1759 * often do repeated subexpressions for those.
1762 move_grf_array_access_to_scratch();
1763 move_uniform_array_access_to_pull_constants();
1765 /* The ARB_vertex_program frontend emits pull constant loads directly
1766 * rather than using reladdr, so we don't need to walk through all the
1767 * instructions looking for things to move. There isn't anything.
1769 * We do still need to split things to vec4 size.
1771 split_uniform_registers();
1773 pack_uniform_registers();
1774 move_push_constants_to_pull_constants();
1775 split_virtual_grfs();
1777 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1779 #define OPT(pass, args...) ({ \
1781 bool this_progress = pass(args); \
1783 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1784 char filename[64]; \
1785 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1786 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1788 backend_visitor::dump_instructions(filename); \
1791 progress = progress || this_progress; \
1796 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1798 snprintf(filename
, 64, "%s-%04d-00-start",
1799 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1801 backend_visitor::dump_instructions(filename
);
1812 OPT(opt_reduce_swizzle
);
1813 OPT(dead_code_eliminate
);
1814 OPT(dead_control_flow_eliminate
, this);
1815 OPT(opt_copy_propagation
);
1818 OPT(opt_register_coalesce
);
1823 if (OPT(opt_vector_float
)) {
1825 OPT(opt_copy_propagation
, false);
1826 OPT(opt_copy_propagation
, true);
1827 OPT(dead_code_eliminate
);
1836 /* Debug of register spilling: Go spill everything. */
1837 const int grf_count
= alloc
.count
;
1838 float spill_costs
[alloc
.count
];
1839 bool no_spill
[alloc
.count
];
1840 evaluate_spill_costs(spill_costs
, no_spill
);
1841 for (int i
= 0; i
< grf_count
; i
++) {
1848 while (!reg_allocate()) {
1853 opt_schedule_instructions();
1855 opt_set_dependency_control();
1857 /* If any state parameters were appended, then ParameterValues could have
1858 * been realloced, in which case the driver uniform storage set up by
1859 * _mesa_associate_uniform_storage() would point to freed memory. Make
1860 * sure that didn't happen.
1862 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1867 } /* namespace brw */
1872 * Compile a vertex shader.
1874 * Returns the final assembly and the program's size.
1877 brw_vs_emit(struct brw_context
*brw
,
1878 struct gl_shader_program
*prog
,
1879 struct brw_vs_compile
*c
,
1880 struct brw_vs_prog_data
*prog_data
,
1882 unsigned *final_assembly_size
)
1884 bool start_busy
= false;
1885 double start_time
= 0;
1886 const unsigned *assembly
= NULL
;
1888 if (unlikely(brw
->perf_debug
)) {
1889 start_busy
= (brw
->batch
.last_bo
&&
1890 drm_intel_bo_busy(brw
->batch
.last_bo
));
1891 start_time
= get_time();
1894 struct brw_shader
*shader
= NULL
;
1896 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1898 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1899 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1901 if (prog
&& brw
->gen
>= 8 && brw
->scalar_vs
) {
1902 fs_visitor
v(brw
, mem_ctx
, &c
->key
, prog_data
, prog
, &c
->vp
->program
, 8);
1905 prog
->LinkStatus
= false;
1906 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1909 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1915 fs_generator
g(brw
, mem_ctx
, (void *) &c
->key
, &prog_data
->base
.base
,
1916 &c
->vp
->program
.Base
, v
.runtime_check_aads_emit
, "VS");
1917 if (INTEL_DEBUG
& DEBUG_VS
) {
1918 char *name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1919 prog
->Label
? prog
->Label
: "unnamed",
1921 g
.enable_debug(name
);
1923 g
.generate_code(v
.cfg
, 8);
1924 assembly
= g
.get_assembly(final_assembly_size
);
1927 prog_data
->base
.simd8
= true;
1928 c
->base
.last_scratch
= v
.last_scratch
;
1932 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1935 prog
->LinkStatus
= false;
1936 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1939 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1945 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1946 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
1947 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1950 if (unlikely(brw
->perf_debug
) && shader
) {
1951 if (shader
->compiled_once
) {
1952 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1954 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1955 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1956 (get_time() - start_time
) * 1000);
1958 shader
->compiled_once
= true;
1966 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1967 struct brw_vue_prog_key
*key
,
1968 GLuint id
, struct gl_program
*prog
)
1970 struct brw_context
*brw
= brw_context(ctx
);
1971 key
->program_string_id
= id
;
1973 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
1974 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1975 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1976 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
1977 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1978 key
->tex
.swizzles
[i
] =
1979 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1981 /* Color sampler: assume no swizzling. */
1982 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;