2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
94 this->fixed_hw_reg
.dw1
.f
= f
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
103 this->fixed_hw_reg
.dw1
.ud
= u
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
112 this->fixed_hw_reg
.dw1
.d
= i
;
115 src_reg::src_reg(struct brw_reg reg
)
120 this->fixed_hw_reg
= reg
;
121 this->type
= reg
.type
;
124 src_reg::src_reg(dst_reg reg
)
128 this->file
= reg
.file
;
130 this->reg_offset
= reg
.reg_offset
;
131 this->type
= reg
.type
;
132 this->reladdr
= reg
.reladdr
;
133 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 for (int i
= 0; i
< 4; i
++) {
140 if (!(reg
.writemask
& (1 << i
)))
143 swizzles
[next_chan
++] = last
= i
;
146 for (; next_chan
< 4; next_chan
++) {
147 swizzles
[next_chan
] = last
;
150 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
151 swizzles
[2], swizzles
[3]);
157 memset(this, 0, sizeof(*this));
158 this->file
= BAD_FILE
;
159 this->writemask
= WRITEMASK_XYZW
;
167 dst_reg::dst_reg(register_file file
, int reg
)
175 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
182 this->type
= brw_type_for_base_type(type
);
183 this->writemask
= writemask
;
186 dst_reg::dst_reg(struct brw_reg reg
)
191 this->fixed_hw_reg
= reg
;
192 this->type
= reg
.type
;
195 dst_reg::dst_reg(src_reg reg
)
199 this->file
= reg
.file
;
201 this->reg_offset
= reg
.reg_offset
;
202 this->type
= reg
.type
;
203 /* How should we do writemasking when converting from a src_reg? It seems
204 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
205 * what about for src.wx? Just special-case src.xxxx for now.
207 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
208 this->writemask
= WRITEMASK_X
;
210 this->writemask
= WRITEMASK_XYZW
;
211 this->reladdr
= reg
.reladdr
;
212 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
216 vec4_instruction::is_send_from_grf()
219 case SHADER_OPCODE_SHADER_TIME_ADD
:
220 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
228 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
230 if (brw
->gen
== 6 && is_math())
233 if (is_send_from_grf())
236 if (!backend_instruction::can_do_source_mods())
243 * Returns how many MRFs an opcode will write over.
245 * Note that this is not the 0 or 1 implied writes in an actual gen
246 * instruction -- the generate_* functions generate additional MOVs
250 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
255 switch (inst
->opcode
) {
256 case SHADER_OPCODE_RCP
:
257 case SHADER_OPCODE_RSQ
:
258 case SHADER_OPCODE_SQRT
:
259 case SHADER_OPCODE_EXP2
:
260 case SHADER_OPCODE_LOG2
:
261 case SHADER_OPCODE_SIN
:
262 case SHADER_OPCODE_COS
:
264 case SHADER_OPCODE_INT_QUOTIENT
:
265 case SHADER_OPCODE_INT_REMAINDER
:
266 case SHADER_OPCODE_POW
:
268 case VS_OPCODE_URB_WRITE
:
270 case VS_OPCODE_PULL_CONSTANT_LOAD
:
272 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
274 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
276 case GS_OPCODE_URB_WRITE
:
277 case GS_OPCODE_THREAD_END
:
279 case GS_OPCODE_FF_SYNC
:
281 case SHADER_OPCODE_SHADER_TIME_ADD
:
283 case SHADER_OPCODE_TEX
:
284 case SHADER_OPCODE_TXL
:
285 case SHADER_OPCODE_TXD
:
286 case SHADER_OPCODE_TXF
:
287 case SHADER_OPCODE_TXF_CMS
:
288 case SHADER_OPCODE_TXF_MCS
:
289 case SHADER_OPCODE_TXS
:
290 case SHADER_OPCODE_TG4
:
291 case SHADER_OPCODE_TG4_OFFSET
:
292 return inst
->header_present
? 1 : 0;
293 case SHADER_OPCODE_UNTYPED_ATOMIC
:
294 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
297 unreachable("not reached");
302 src_reg::equals(const src_reg
&r
) const
304 return (file
== r
.file
&&
306 reg_offset
== r
.reg_offset
&&
308 negate
== r
.negate
&&
310 swizzle
== r
.swizzle
&&
311 !reladdr
&& !r
.reladdr
&&
312 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
313 sizeof(fixed_hw_reg
)) == 0);
316 /* Replaces unused channels of a swizzle with channels that are used.
318 * For instance, this pass transforms
320 * mov vgrf4.yz, vgrf5.wxzy
324 * mov vgrf4.yz, vgrf5.xxzx
326 * This eliminates false uses of some channels, letting dead code elimination
327 * remove the instructions that wrote them.
330 vec4_visitor::opt_reduce_swizzle()
332 bool progress
= false;
334 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
335 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
)
340 /* Determine which channels of the sources are read. */
341 switch (inst
->opcode
) {
343 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
344 * but all four of src1.
364 swizzle
[0] = inst
->dst
.writemask
& WRITEMASK_X
? 0 : -1;
365 swizzle
[1] = inst
->dst
.writemask
& WRITEMASK_Y
? 1 : -1;
366 swizzle
[2] = inst
->dst
.writemask
& WRITEMASK_Z
? 2 : -1;
367 swizzle
[3] = inst
->dst
.writemask
& WRITEMASK_W
? 3 : -1;
371 /* Resolve unread channels (-1) by assigning them the swizzle of the
372 * first channel that is used.
374 int first_used_channel
= 0;
375 for (int i
= 0; i
< 4; i
++) {
376 if (swizzle
[i
] != -1) {
377 first_used_channel
= swizzle
[i
];
381 for (int i
= 0; i
< 4; i
++) {
382 if (swizzle
[i
] == -1) {
383 swizzle
[i
] = first_used_channel
;
387 /* Update sources' swizzles. */
388 for (int i
= 0; i
< 3; i
++) {
389 if (inst
->src
[i
].file
!= GRF
&&
390 inst
->src
[i
].file
!= ATTR
&&
391 inst
->src
[i
].file
!= UNIFORM
)
395 for (int j
= 0; j
< 4; j
++) {
396 swiz
[j
] = BRW_GET_SWZ(inst
->src
[i
].swizzle
, swizzle
[j
]);
399 unsigned new_swizzle
= BRW_SWIZZLE4(swiz
[0], swiz
[1], swiz
[2], swiz
[3]);
400 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
401 inst
->src
[i
].swizzle
= new_swizzle
;
408 invalidate_live_intervals(false);
414 try_eliminate_instruction(vec4_instruction
*inst
, int new_writemask
,
415 const struct brw_context
*brw
)
417 if (inst
->has_side_effects())
420 if (new_writemask
== 0) {
421 /* Don't dead code eliminate instructions that write to the
422 * accumulator as a side-effect. Instead just set the destination
423 * to the null register to free it.
425 if (inst
->writes_accumulator
|| inst
->writes_flag()) {
426 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
432 } else if (inst
->dst
.writemask
!= new_writemask
) {
433 switch (inst
->opcode
) {
434 case SHADER_OPCODE_TXF_CMS
:
435 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
436 case VS_OPCODE_PULL_CONSTANT_LOAD
:
437 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
440 /* Do not set a writemask on Gen6 for math instructions, those are
441 * executed using align1 mode that does not support a destination mask.
443 if (!(brw
->gen
== 6 && inst
->is_math()) && !inst
->is_tex()) {
444 inst
->dst
.writemask
= new_writemask
;
454 * Must be called after calculate_live_intervals() to remove unused
455 * writes to registers -- register allocation will fail otherwise
456 * because something deffed but not used won't be considered to
457 * interfere with other regs.
460 vec4_visitor::dead_code_eliminate()
462 bool progress
= false;
465 calculate_live_intervals();
467 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
470 bool inst_writes_flag
= false;
471 if (inst
->dst
.file
!= GRF
) {
472 if (inst
->dst
.is_null() && inst
->writes_flag()) {
473 inst_writes_flag
= true;
479 if (inst
->dst
.file
== GRF
) {
480 int write_mask
= inst
->dst
.writemask
;
482 for (int c
= 0; c
< 4; c
++) {
483 if (write_mask
& (1 << c
)) {
484 assert(this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] >= pc
);
485 if (this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] == pc
) {
486 write_mask
&= ~(1 << c
);
491 progress
= try_eliminate_instruction(inst
, write_mask
, brw
) ||
495 if (inst
->predicate
|| inst
->prev
== NULL
)
499 if (inst_writes_flag
) {
500 /* Arbitrarily chosen, other than not being an xyzw writemask. */
501 #define FLAG_WRITEMASK (1 << 5)
502 dead_channels
= inst
->reads_flag() ? 0 : FLAG_WRITEMASK
;
504 dead_channels
= inst
->dst
.writemask
;
506 for (int i
= 0; i
< 3; i
++) {
507 if (inst
->src
[i
].file
!= GRF
||
508 inst
->src
[i
].reg
!= inst
->dst
.reg
)
511 for (int j
= 0; j
< 4; j
++) {
512 int swiz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
513 dead_channels
&= ~(1 << swiz
);
518 for (exec_node
*node
= inst
->prev
, *prev
= node
->prev
;
519 prev
!= NULL
&& dead_channels
!= 0;
520 node
= prev
, prev
= prev
->prev
) {
521 vec4_instruction
*scan_inst
= (vec4_instruction
*)node
;
523 if (scan_inst
->is_control_flow())
526 if (inst_writes_flag
) {
527 if (scan_inst
->dst
.is_null() && scan_inst
->writes_flag()) {
531 } else if (scan_inst
->reads_flag()) {
536 if (inst
->dst
.file
== scan_inst
->dst
.file
&&
537 inst
->dst
.reg
== scan_inst
->dst
.reg
&&
538 inst
->dst
.reg_offset
== scan_inst
->dst
.reg_offset
) {
539 int new_writemask
= scan_inst
->dst
.writemask
& ~dead_channels
;
541 progress
= try_eliminate_instruction(scan_inst
, new_writemask
, brw
) ||
545 for (int i
= 0; i
< 3; i
++) {
546 if (scan_inst
->src
[i
].file
!= inst
->dst
.file
||
547 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
)
550 for (int j
= 0; j
< 4; j
++) {
551 int swiz
= BRW_GET_SWZ(scan_inst
->src
[i
].swizzle
, j
);
552 dead_channels
&= ~(1 << swiz
);
559 invalidate_live_intervals();
565 vec4_visitor::split_uniform_registers()
567 /* Prior to this, uniforms have been in an array sized according to
568 * the number of vector uniforms present, sparsely filled (so an
569 * aggregate results in reg indices being skipped over). Now we're
570 * going to cut those aggregates up so each .reg index is one
571 * vector. The goal is to make elimination of unused uniform
572 * components easier later.
574 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
575 for (int i
= 0 ; i
< 3; i
++) {
576 if (inst
->src
[i
].file
!= UNIFORM
)
579 assert(!inst
->src
[i
].reladdr
);
581 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
582 inst
->src
[i
].reg_offset
= 0;
586 /* Update that everything is now vector-sized. */
587 for (int i
= 0; i
< this->uniforms
; i
++) {
588 this->uniform_size
[i
] = 1;
593 vec4_visitor::pack_uniform_registers()
595 bool uniform_used
[this->uniforms
];
596 int new_loc
[this->uniforms
];
597 int new_chan
[this->uniforms
];
599 memset(uniform_used
, 0, sizeof(uniform_used
));
600 memset(new_loc
, 0, sizeof(new_loc
));
601 memset(new_chan
, 0, sizeof(new_chan
));
603 /* Find which uniform vectors are actually used by the program. We
604 * expect unused vector elements when we've moved array access out
605 * to pull constants, and from some GLSL code generators like wine.
607 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
608 for (int i
= 0 ; i
< 3; i
++) {
609 if (inst
->src
[i
].file
!= UNIFORM
)
612 uniform_used
[inst
->src
[i
].reg
] = true;
616 int new_uniform_count
= 0;
618 /* Now, figure out a packing of the live uniform vectors into our
621 for (int src
= 0; src
< uniforms
; src
++) {
622 assert(src
< uniform_array_size
);
623 int size
= this->uniform_vector_size
[src
];
625 if (!uniform_used
[src
]) {
626 this->uniform_vector_size
[src
] = 0;
631 /* Find the lowest place we can slot this uniform in. */
632 for (dst
= 0; dst
< src
; dst
++) {
633 if (this->uniform_vector_size
[dst
] + size
<= 4)
642 new_chan
[src
] = this->uniform_vector_size
[dst
];
644 /* Move the references to the data */
645 for (int j
= 0; j
< size
; j
++) {
646 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
647 stage_prog_data
->param
[src
* 4 + j
];
650 this->uniform_vector_size
[dst
] += size
;
651 this->uniform_vector_size
[src
] = 0;
654 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
657 this->uniforms
= new_uniform_count
;
659 /* Now, update the instructions for our repacked uniforms. */
660 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
661 for (int i
= 0 ; i
< 3; i
++) {
662 int src
= inst
->src
[i
].reg
;
664 if (inst
->src
[i
].file
!= UNIFORM
)
667 inst
->src
[i
].reg
= new_loc
[src
];
669 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
670 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
671 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
672 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
673 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
679 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
681 * While GLSL IR also performs this optimization, we end up with it in
682 * our instruction stream for a couple of reasons. One is that we
683 * sometimes generate silly instructions, for example in array access
684 * where we'll generate "ADD offset, index, base" even if base is 0.
685 * The other is that GLSL IR's constant propagation doesn't track the
686 * components of aggregates, so some VS patterns (initialize matrix to
687 * 0, accumulate in vertex blending factors) end up breaking down to
688 * instructions involving 0.
691 vec4_visitor::opt_algebraic()
693 bool progress
= false;
695 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
696 switch (inst
->opcode
) {
698 if (inst
->src
[1].is_zero()) {
699 inst
->opcode
= BRW_OPCODE_MOV
;
700 inst
->src
[1] = src_reg();
706 if (inst
->src
[1].is_zero()) {
707 inst
->opcode
= BRW_OPCODE_MOV
;
708 switch (inst
->src
[0].type
) {
709 case BRW_REGISTER_TYPE_F
:
710 inst
->src
[0] = src_reg(0.0f
);
712 case BRW_REGISTER_TYPE_D
:
713 inst
->src
[0] = src_reg(0);
715 case BRW_REGISTER_TYPE_UD
:
716 inst
->src
[0] = src_reg(0u);
719 unreachable("not reached");
721 inst
->src
[1] = src_reg();
723 } else if (inst
->src
[1].is_one()) {
724 inst
->opcode
= BRW_OPCODE_MOV
;
725 inst
->src
[1] = src_reg();
735 invalidate_live_intervals();
741 * Only a limited number of hardware registers may be used for push
742 * constants, so this turns access to the overflowed constants into
746 vec4_visitor::move_push_constants_to_pull_constants()
748 int pull_constant_loc
[this->uniforms
];
750 /* Only allow 32 registers (256 uniform components) as push constants,
751 * which is the limit on gen6.
753 * If changing this value, note the limitation about total_regs in
756 int max_uniform_components
= 32 * 8;
757 if (this->uniforms
* 4 <= max_uniform_components
)
760 /* Make some sort of choice as to which uniforms get sent to pull
761 * constants. We could potentially do something clever here like
762 * look for the most infrequently used uniform vec4s, but leave
765 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
766 pull_constant_loc
[i
/ 4] = -1;
768 if (i
>= max_uniform_components
) {
769 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
771 /* Try to find an existing copy of this uniform in the pull
772 * constants if it was part of an array access already.
774 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
777 for (matches
= 0; matches
< 4; matches
++) {
778 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
783 pull_constant_loc
[i
/ 4] = j
/ 4;
788 if (pull_constant_loc
[i
/ 4] == -1) {
789 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
790 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
792 for (int j
= 0; j
< 4; j
++) {
793 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
800 /* Now actually rewrite usage of the things we've moved to pull
803 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
804 for (int i
= 0 ; i
< 3; i
++) {
805 if (inst
->src
[i
].file
!= UNIFORM
||
806 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
809 int uniform
= inst
->src
[i
].reg
;
811 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
813 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
814 pull_constant_loc
[uniform
]);
816 inst
->src
[i
].file
= temp
.file
;
817 inst
->src
[i
].reg
= temp
.reg
;
818 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
819 inst
->src
[i
].reladdr
= NULL
;
823 /* Repack push constants to remove the now-unused ones. */
824 pack_uniform_registers();
828 * Sets the dependency control fields on instructions after register
829 * allocation and before the generator is run.
831 * When you have a sequence of instructions like:
833 * DP4 temp.x vertex uniform[0]
834 * DP4 temp.y vertex uniform[0]
835 * DP4 temp.z vertex uniform[0]
836 * DP4 temp.w vertex uniform[0]
838 * The hardware doesn't know that it can actually run the later instructions
839 * while the previous ones are in flight, producing stalls. However, we have
840 * manual fields we can set in the instructions that let it do so.
843 vec4_visitor::opt_set_dependency_control()
845 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
846 uint8_t grf_channels_written
[BRW_MAX_GRF
];
847 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
848 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
852 assert(prog_data
->total_grf
||
853 !"Must be called after register allocation");
855 foreach_block (block
, cfg
) {
856 memset(last_grf_write
, 0, sizeof(last_grf_write
));
857 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
859 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
860 /* If we read from a register that we were doing dependency control
861 * on, don't do dependency control across the read.
863 for (int i
= 0; i
< 3; i
++) {
864 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
865 if (inst
->src
[i
].file
== GRF
) {
866 last_grf_write
[reg
] = NULL
;
867 } else if (inst
->src
[i
].file
== HW_REG
) {
868 memset(last_grf_write
, 0, sizeof(last_grf_write
));
871 assert(inst
->src
[i
].file
!= MRF
);
874 /* In the presence of send messages, totally interrupt dependency
875 * control. They're long enough that the chance of dependency
876 * control around them just doesn't matter.
879 memset(last_grf_write
, 0, sizeof(last_grf_write
));
880 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
884 /* It looks like setting dependency control on a predicated
885 * instruction hangs the GPU.
887 if (inst
->predicate
) {
888 memset(last_grf_write
, 0, sizeof(last_grf_write
));
889 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
893 /* Dependency control does not work well over math instructions.
895 if (inst
->is_math()) {
896 memset(last_grf_write
, 0, sizeof(last_grf_write
));
897 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
901 /* Now, see if we can do dependency control for this instruction
902 * against a previous one writing to its destination.
904 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
905 if (inst
->dst
.file
== GRF
) {
906 if (last_grf_write
[reg
] &&
907 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
908 last_grf_write
[reg
]->no_dd_clear
= true;
909 inst
->no_dd_check
= true;
911 grf_channels_written
[reg
] = 0;
914 last_grf_write
[reg
] = inst
;
915 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
916 } else if (inst
->dst
.file
== MRF
) {
917 if (last_mrf_write
[reg
] &&
918 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
919 last_mrf_write
[reg
]->no_dd_clear
= true;
920 inst
->no_dd_check
= true;
922 mrf_channels_written
[reg
] = 0;
925 last_mrf_write
[reg
] = inst
;
926 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
927 } else if (inst
->dst
.reg
== HW_REG
) {
928 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
929 memset(last_grf_write
, 0, sizeof(last_grf_write
));
930 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
931 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
938 vec4_instruction::can_reswizzle(int dst_writemask
,
942 /* If this instruction sets anything not referenced by swizzle, then we'd
943 * totally break it when we reswizzle.
945 if (dst
.writemask
& ~swizzle_mask
)
955 * For any channels in the swizzle's source that were populated by this
956 * instruction, rewrite the instruction to put the appropriate result directly
959 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
962 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
964 int new_writemask
= 0;
965 int new_swizzle
[4] = { 0 };
967 /* Dot product instructions write a single result into all channels. */
968 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
969 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
) {
970 for (int i
= 0; i
< 3; i
++) {
971 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
974 for (int c
= 0; c
< 4; c
++) {
975 new_swizzle
[c
] = BRW_GET_SWZ(src
[i
].swizzle
, BRW_GET_SWZ(swizzle
, c
));
978 src
[i
].swizzle
= BRW_SWIZZLE4(new_swizzle
[0], new_swizzle
[1],
979 new_swizzle
[2], new_swizzle
[3]);
983 for (int c
= 0; c
< 4; c
++) {
984 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
985 /* Skip components of the swizzle not used by the dst. */
986 if (!(dst_writemask
& (1 << c
)))
988 /* If we were populating this component, then populate the
989 * corresponding channel of the new dst.
991 if (dst
.writemask
& bit
)
992 new_writemask
|= (1 << c
);
994 dst
.writemask
= new_writemask
;
998 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
999 * just written and then MOVed into another reg and making the original write
1000 * of the GRF write directly to the final destination instead.
1003 vec4_visitor::opt_register_coalesce()
1005 bool progress
= false;
1008 calculate_live_intervals();
1010 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1014 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1015 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1017 inst
->src
[0].file
!= GRF
||
1018 inst
->dst
.type
!= inst
->src
[0].type
||
1019 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1022 bool to_mrf
= (inst
->dst
.file
== MRF
);
1024 /* Can't coalesce this GRF if someone else was going to
1027 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1028 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1029 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1030 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1033 /* We need to check interference with the final destination between this
1034 * instruction and the earliest instruction involved in writing the GRF
1035 * we're eliminating. To do that, keep track of which of our source
1036 * channels we've seen initialized.
1038 bool chans_needed
[4] = {false, false, false, false};
1039 int chans_remaining
= 0;
1040 int swizzle_mask
= 0;
1041 for (int i
= 0; i
< 4; i
++) {
1042 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1044 if (!(inst
->dst
.writemask
& (1 << i
)))
1047 swizzle_mask
|= (1 << chan
);
1049 if (!chans_needed
[chan
]) {
1050 chans_needed
[chan
] = true;
1055 /* Now walk up the instruction stream trying to see if we can rewrite
1056 * everything writing to the temporary to write into the destination
1059 vec4_instruction
*scan_inst
;
1060 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
1061 scan_inst
->prev
!= NULL
;
1062 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
1063 if (scan_inst
->dst
.file
== GRF
&&
1064 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1065 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1066 /* Found something writing to the reg we want to coalesce away. */
1068 /* SEND instructions can't have MRF as a destination. */
1069 if (scan_inst
->mlen
)
1072 if (brw
->gen
== 6) {
1073 /* gen6 math instructions must have the destination be
1074 * GRF, so no compute-to-MRF for them.
1076 if (scan_inst
->is_math()) {
1082 /* If we can't handle the swizzle, bail. */
1083 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1084 inst
->src
[0].swizzle
,
1089 /* Mark which channels we found unconditional writes for. */
1090 if (!scan_inst
->predicate
) {
1091 for (int i
= 0; i
< 4; i
++) {
1092 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1094 chans_needed
[i
] = false;
1100 if (chans_remaining
== 0)
1104 /* We don't handle flow control here. Most computation of values
1105 * that could be coalesced happens just before their use.
1107 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1108 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1109 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1110 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1114 /* You can't read from an MRF, so if someone else reads our MRF's
1115 * source GRF that we wanted to rewrite, that stops us. If it's a
1116 * GRF we're trying to coalesce to, we don't actually handle
1117 * rewriting sources so bail in that case as well.
1119 bool interfered
= false;
1120 for (int i
= 0; i
< 3; i
++) {
1121 if (scan_inst
->src
[i
].file
== GRF
&&
1122 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1123 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1130 /* If somebody else writes our destination here, we can't coalesce
1133 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1134 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1138 /* Check for reads of the register we're trying to coalesce into. We
1139 * can't go rewriting instructions above that to put some other value
1140 * in the register instead.
1142 if (to_mrf
&& scan_inst
->mlen
> 0) {
1143 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1144 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1148 for (int i
= 0; i
< 3; i
++) {
1149 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1150 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1151 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1160 if (chans_remaining
== 0) {
1161 /* If we've made it here, we have an MOV we want to coalesce out, and
1162 * a scan_inst pointing to the earliest instruction involved in
1163 * computing the value. Now go rewrite the instruction stream
1167 while (scan_inst
!= inst
) {
1168 if (scan_inst
->dst
.file
== GRF
&&
1169 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1170 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1171 scan_inst
->reswizzle(inst
->dst
.writemask
,
1172 inst
->src
[0].swizzle
);
1173 scan_inst
->dst
.file
= inst
->dst
.file
;
1174 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1175 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1176 scan_inst
->saturate
|= inst
->saturate
;
1178 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1180 inst
->remove(block
);
1186 invalidate_live_intervals(false);
1192 * Splits virtual GRFs requesting more than one contiguous physical register.
1194 * We initially create large virtual GRFs for temporary structures, arrays,
1195 * and matrices, so that the dereference visitor functions can add reg_offsets
1196 * to work their way down to the actual member being accessed. But when it
1197 * comes to optimization, we'd like to treat each register as individual
1198 * storage if possible.
1200 * So far, the only thing that might prevent splitting is a send message from
1204 vec4_visitor::split_virtual_grfs()
1206 int num_vars
= this->virtual_grf_count
;
1207 int new_virtual_grf
[num_vars
];
1208 bool split_grf
[num_vars
];
1210 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1212 /* Try to split anything > 0 sized. */
1213 for (int i
= 0; i
< num_vars
; i
++) {
1214 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1217 /* Check that the instructions are compatible with the registers we're trying
1220 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1221 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1224 if (inst
->is_send_from_grf()) {
1225 for (int i
= 0; i
< 3; i
++) {
1226 if (inst
->src
[i
].file
== GRF
) {
1227 split_grf
[inst
->src
[i
].reg
] = false;
1233 /* Allocate new space for split regs. Note that the virtual
1234 * numbers will be contiguous.
1236 for (int i
= 0; i
< num_vars
; i
++) {
1240 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1241 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1242 int reg
= virtual_grf_alloc(1);
1243 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1246 this->virtual_grf_sizes
[i
] = 1;
1249 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1250 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1251 inst
->dst
.reg_offset
!= 0) {
1252 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1253 inst
->dst
.reg_offset
- 1);
1254 inst
->dst
.reg_offset
= 0;
1256 for (int i
= 0; i
< 3; i
++) {
1257 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1258 inst
->src
[i
].reg_offset
!= 0) {
1259 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1260 inst
->src
[i
].reg_offset
- 1);
1261 inst
->src
[i
].reg_offset
= 0;
1265 invalidate_live_intervals(false);
1269 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1271 dump_instruction(be_inst
, stderr
);
1275 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1277 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1279 if (inst
->predicate
) {
1280 fprintf(file
, "(%cf0) ",
1281 inst
->predicate_inverse
? '-' : '+');
1284 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1285 if (inst
->conditional_mod
) {
1286 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1290 switch (inst
->dst
.file
) {
1292 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1295 fprintf(file
, "m%d", inst
->dst
.reg
);
1298 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1299 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1301 fprintf(file
, "null");
1303 case BRW_ARF_ADDRESS
:
1304 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1306 case BRW_ARF_ACCUMULATOR
:
1307 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1310 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1311 inst
->dst
.fixed_hw_reg
.subnr
);
1314 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1315 inst
->dst
.fixed_hw_reg
.subnr
);
1319 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1321 if (inst
->dst
.fixed_hw_reg
.subnr
)
1322 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1325 fprintf(file
, "(null)");
1328 fprintf(file
, "???");
1331 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1333 if (inst
->dst
.writemask
& 1)
1335 if (inst
->dst
.writemask
& 2)
1337 if (inst
->dst
.writemask
& 4)
1339 if (inst
->dst
.writemask
& 8)
1342 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1344 if (inst
->src
[0].file
!= BAD_FILE
)
1345 fprintf(file
, ", ");
1347 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1348 if (inst
->src
[i
].negate
)
1350 if (inst
->src
[i
].abs
)
1352 switch (inst
->src
[i
].file
) {
1354 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1357 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1360 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1363 switch (inst
->src
[i
].type
) {
1364 case BRW_REGISTER_TYPE_F
:
1365 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1367 case BRW_REGISTER_TYPE_D
:
1368 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1370 case BRW_REGISTER_TYPE_UD
:
1371 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1374 fprintf(file
, "???");
1379 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1381 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1383 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1384 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1386 fprintf(file
, "null");
1388 case BRW_ARF_ADDRESS
:
1389 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1391 case BRW_ARF_ACCUMULATOR
:
1392 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1395 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1396 inst
->src
[i
].fixed_hw_reg
.subnr
);
1399 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1400 inst
->src
[i
].fixed_hw_reg
.subnr
);
1404 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1406 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1407 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1408 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1412 fprintf(file
, "(null)");
1415 fprintf(file
, "???");
1419 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1420 if (inst
->src
[i
].reg_offset
!= 0 &&
1421 inst
->src
[i
].file
== GRF
&&
1422 virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1423 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1425 if (inst
->src
[i
].file
!= IMM
) {
1426 static const char *chans
[4] = {"x", "y", "z", "w"};
1428 for (int c
= 0; c
< 4; c
++) {
1429 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1433 if (inst
->src
[i
].abs
)
1436 if (inst
->src
[i
].file
!= IMM
) {
1437 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1440 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1441 fprintf(file
, ", ");
1444 fprintf(file
, "\n");
1448 static inline struct brw_reg
1449 attribute_to_hw_reg(int attr
, bool interleaved
)
1452 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1454 return brw_vec8_grf(attr
, 0);
1459 * Replace each register of type ATTR in this->instructions with a reference
1460 * to a fixed HW register.
1462 * If interleaved is true, then each attribute takes up half a register, with
1463 * register N containing attribute 2*N in its first half and attribute 2*N+1
1464 * in its second half (this corresponds to the payload setup used by geometry
1465 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1466 * false, then each attribute takes up a whole register, with register N
1467 * containing attribute N (this corresponds to the payload setup used by
1468 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1471 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1474 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1475 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1476 if (inst
->dst
.file
== ATTR
) {
1477 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1479 /* All attributes used in the shader need to have been assigned a
1480 * hardware register by the caller
1484 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1485 reg
.type
= inst
->dst
.type
;
1486 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1488 inst
->dst
.file
= HW_REG
;
1489 inst
->dst
.fixed_hw_reg
= reg
;
1492 for (int i
= 0; i
< 3; i
++) {
1493 if (inst
->src
[i
].file
!= ATTR
)
1496 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1498 /* All attributes used in the shader need to have been assigned a
1499 * hardware register by the caller
1503 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1504 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1505 reg
.type
= inst
->src
[i
].type
;
1506 if (inst
->src
[i
].abs
)
1508 if (inst
->src
[i
].negate
)
1511 inst
->src
[i
].file
= HW_REG
;
1512 inst
->src
[i
].fixed_hw_reg
= reg
;
1518 vec4_vs_visitor::setup_attributes(int payload_reg
)
1521 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1522 memset(attribute_map
, 0, sizeof(attribute_map
));
1525 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1526 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1527 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1532 /* VertexID is stored by the VF as the last vertex element, but we
1533 * don't represent it with a flag in inputs_read, so we call it
1536 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1537 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1541 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1543 /* The BSpec says we always have to read at least one thing from
1544 * the VF, and it appears that the hardware wedges otherwise.
1546 if (nr_attributes
== 0)
1549 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1551 unsigned vue_entries
=
1552 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1555 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1557 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1559 return payload_reg
+ nr_attributes
;
1563 vec4_visitor::setup_uniforms(int reg
)
1565 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1567 /* The pre-gen6 VS requires that some push constants get loaded no
1568 * matter what, or the GPU would hang.
1570 if (brw
->gen
< 6 && this->uniforms
== 0) {
1571 assert(this->uniforms
< this->uniform_array_size
);
1572 this->uniform_vector_size
[this->uniforms
] = 1;
1574 stage_prog_data
->param
=
1575 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1576 for (unsigned int i
= 0; i
< 4; i
++) {
1577 unsigned int slot
= this->uniforms
* 4 + i
;
1578 static gl_constant_value zero
= { 0.0 };
1579 stage_prog_data
->param
[slot
] = &zero
;
1585 reg
+= ALIGN(uniforms
, 2) / 2;
1588 stage_prog_data
->nr_params
= this->uniforms
* 4;
1590 prog_data
->base
.curb_read_length
=
1591 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1597 vec4_vs_visitor::setup_payload(void)
1601 /* The payload always contains important data in g0, which contains
1602 * the URB handles that are passed on to the URB write at the end
1603 * of the thread. So, we always start push constants at g1.
1607 reg
= setup_uniforms(reg
);
1609 reg
= setup_attributes(reg
);
1611 this->first_non_payload_grf
= reg
;
1615 vec4_visitor::get_timestamp()
1617 assert(brw
->gen
>= 7);
1619 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1622 BRW_REGISTER_TYPE_UD
,
1623 BRW_VERTICAL_STRIDE_0
,
1625 BRW_HORIZONTAL_STRIDE_4
,
1629 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1631 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1632 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1633 * even if it's not enabled in the dispatch.
1635 mov
->force_writemask_all
= true;
1637 return src_reg(dst
);
1641 vec4_visitor::emit_shader_time_begin()
1643 current_annotation
= "shader time start";
1644 shader_start_time
= get_timestamp();
1648 vec4_visitor::emit_shader_time_end()
1650 current_annotation
= "shader time end";
1651 src_reg shader_end_time
= get_timestamp();
1654 /* Check that there weren't any timestamp reset events (assuming these
1655 * were the only two timestamp reads that happened).
1657 src_reg reset_end
= shader_end_time
;
1658 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1659 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1660 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1662 emit(IF(BRW_PREDICATE_NORMAL
));
1664 /* Take the current timestamp and get the delta. */
1665 shader_start_time
.negate
= true;
1666 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1667 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1669 /* If there were no instructions between the two timestamp gets, the diff
1670 * is 2 cycles. Remove that overhead, so I can forget about that when
1671 * trying to determine the time taken for single instructions.
1673 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1675 emit_shader_time_write(st_base
, src_reg(diff
));
1676 emit_shader_time_write(st_written
, src_reg(1u));
1677 emit(BRW_OPCODE_ELSE
);
1678 emit_shader_time_write(st_reset
, src_reg(1u));
1679 emit(BRW_OPCODE_ENDIF
);
1683 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1686 int shader_time_index
=
1687 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1690 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1692 dst_reg offset
= dst
;
1696 offset
.type
= BRW_REGISTER_TYPE_UD
;
1697 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1699 time
.type
= BRW_REGISTER_TYPE_UD
;
1700 emit(MOV(time
, src_reg(value
)));
1702 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1708 sanity_param_count
= prog
->Parameters
->NumParameters
;
1710 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1711 emit_shader_time_begin();
1713 assign_common_binding_table_offsets(0);
1717 /* Generate VS IR for main(). (the visitor only descends into
1718 * functions called "main").
1721 visit_instructions(shader
->base
.ir
);
1723 emit_program_code();
1727 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1728 setup_uniform_clipplane_values();
1732 /* Before any optimization, push array accesses out to scratch
1733 * space where we need them to be. This pass may allocate new
1734 * virtual GRFs, so we want to do it early. It also makes sure
1735 * that we have reladdr computations available for CSE, since we'll
1736 * often do repeated subexpressions for those.
1739 move_grf_array_access_to_scratch();
1740 move_uniform_array_access_to_pull_constants();
1742 /* The ARB_vertex_program frontend emits pull constant loads directly
1743 * rather than using reladdr, so we don't need to walk through all the
1744 * instructions looking for things to move. There isn't anything.
1746 * We do still need to split things to vec4 size.
1748 split_uniform_registers();
1750 pack_uniform_registers();
1751 move_push_constants_to_pull_constants();
1752 split_virtual_grfs();
1754 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1756 #define OPT(pass, args...) do { \
1758 bool this_progress = pass(args); \
1760 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1761 char filename[64]; \
1762 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1763 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1765 backend_visitor::dump_instructions(filename); \
1768 progress = progress || this_progress; \
1772 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1774 snprintf(filename
, 64, "%s-%04d-00-start",
1775 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1777 backend_visitor::dump_instructions(filename
);
1787 OPT(opt_reduce_swizzle
);
1788 OPT(dead_code_eliminate
);
1789 OPT(dead_control_flow_eliminate
, this);
1790 OPT(opt_copy_propagation
);
1793 OPT(opt_register_coalesce
);
1803 /* Debug of register spilling: Go spill everything. */
1804 const int grf_count
= virtual_grf_count
;
1805 float spill_costs
[virtual_grf_count
];
1806 bool no_spill
[virtual_grf_count
];
1807 evaluate_spill_costs(spill_costs
, no_spill
);
1808 for (int i
= 0; i
< grf_count
; i
++) {
1815 while (!reg_allocate()) {
1820 opt_schedule_instructions();
1822 opt_set_dependency_control();
1824 /* If any state parameters were appended, then ParameterValues could have
1825 * been realloced, in which case the driver uniform storage set up by
1826 * _mesa_associate_uniform_storage() would point to freed memory. Make
1827 * sure that didn't happen.
1829 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1836 } /* namespace brw */
1841 * Compile a vertex shader.
1843 * Returns the final assembly and the program's size.
1846 brw_vs_emit(struct brw_context
*brw
,
1847 struct gl_shader_program
*prog
,
1848 struct brw_vs_compile
*c
,
1849 struct brw_vs_prog_data
*prog_data
,
1851 unsigned *final_assembly_size
)
1853 bool start_busy
= false;
1854 double start_time
= 0;
1856 if (unlikely(brw
->perf_debug
)) {
1857 start_busy
= (brw
->batch
.last_bo
&&
1858 drm_intel_bo_busy(brw
->batch
.last_bo
));
1859 start_time
= get_time();
1862 struct brw_shader
*shader
= NULL
;
1864 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1866 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1867 brw_dump_ir(brw
, "vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1869 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1872 prog
->LinkStatus
= false;
1873 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1876 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1882 const unsigned *assembly
= NULL
;
1883 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1884 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1885 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1887 if (unlikely(brw
->perf_debug
) && shader
) {
1888 if (shader
->compiled_once
) {
1889 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1891 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1892 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1893 (get_time() - start_time
) * 1000);
1895 shader
->compiled_once
= true;
1903 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1904 struct brw_vec4_prog_key
*key
,
1905 GLuint id
, struct gl_program
*prog
)
1907 key
->program_string_id
= id
;
1908 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1910 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1911 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1912 if (prog
->ShadowSamplers
& (1 << i
)) {
1913 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1914 key
->tex
.swizzles
[i
] =
1915 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1917 /* Color sampler: assume no swizzling. */
1918 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;