2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
94 this->fixed_hw_reg
.dw1
.f
= f
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
103 this->fixed_hw_reg
.dw1
.ud
= u
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
112 this->fixed_hw_reg
.dw1
.d
= i
;
115 src_reg::src_reg(struct brw_reg reg
)
120 this->fixed_hw_reg
= reg
;
121 this->type
= reg
.type
;
124 src_reg::src_reg(dst_reg reg
)
128 this->file
= reg
.file
;
130 this->reg_offset
= reg
.reg_offset
;
131 this->type
= reg
.type
;
132 this->reladdr
= reg
.reladdr
;
133 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 for (int i
= 0; i
< 4; i
++) {
140 if (!(reg
.writemask
& (1 << i
)))
143 swizzles
[next_chan
++] = last
= i
;
146 for (; next_chan
< 4; next_chan
++) {
147 swizzles
[next_chan
] = last
;
150 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
151 swizzles
[2], swizzles
[3]);
157 memset(this, 0, sizeof(*this));
158 this->file
= BAD_FILE
;
159 this->writemask
= WRITEMASK_XYZW
;
167 dst_reg::dst_reg(register_file file
, int reg
)
175 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
182 this->type
= brw_type_for_base_type(type
);
183 this->writemask
= writemask
;
186 dst_reg::dst_reg(struct brw_reg reg
)
191 this->fixed_hw_reg
= reg
;
192 this->type
= reg
.type
;
195 dst_reg::dst_reg(src_reg reg
)
199 this->file
= reg
.file
;
201 this->reg_offset
= reg
.reg_offset
;
202 this->type
= reg
.type
;
203 /* How should we do writemasking when converting from a src_reg? It seems
204 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
205 * what about for src.wx? Just special-case src.xxxx for now.
207 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
208 this->writemask
= WRITEMASK_X
;
210 this->writemask
= WRITEMASK_XYZW
;
211 this->reladdr
= reg
.reladdr
;
212 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
216 vec4_instruction::is_send_from_grf()
219 case SHADER_OPCODE_SHADER_TIME_ADD
:
220 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
228 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
230 if (brw
->gen
== 6 && is_math())
233 if (is_send_from_grf())
236 if (!backend_instruction::can_do_source_mods())
243 * Returns how many MRFs an opcode will write over.
245 * Note that this is not the 0 or 1 implied writes in an actual gen
246 * instruction -- the generate_* functions generate additional MOVs
250 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
255 switch (inst
->opcode
) {
256 case SHADER_OPCODE_RCP
:
257 case SHADER_OPCODE_RSQ
:
258 case SHADER_OPCODE_SQRT
:
259 case SHADER_OPCODE_EXP2
:
260 case SHADER_OPCODE_LOG2
:
261 case SHADER_OPCODE_SIN
:
262 case SHADER_OPCODE_COS
:
264 case SHADER_OPCODE_INT_QUOTIENT
:
265 case SHADER_OPCODE_INT_REMAINDER
:
266 case SHADER_OPCODE_POW
:
268 case VS_OPCODE_URB_WRITE
:
270 case VS_OPCODE_PULL_CONSTANT_LOAD
:
272 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
274 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
276 case GS_OPCODE_URB_WRITE
:
277 case GS_OPCODE_THREAD_END
:
279 case SHADER_OPCODE_SHADER_TIME_ADD
:
281 case SHADER_OPCODE_TEX
:
282 case SHADER_OPCODE_TXL
:
283 case SHADER_OPCODE_TXD
:
284 case SHADER_OPCODE_TXF
:
285 case SHADER_OPCODE_TXF_CMS
:
286 case SHADER_OPCODE_TXF_MCS
:
287 case SHADER_OPCODE_TXS
:
288 case SHADER_OPCODE_TG4
:
289 case SHADER_OPCODE_TG4_OFFSET
:
290 return inst
->header_present
? 1 : 0;
291 case SHADER_OPCODE_UNTYPED_ATOMIC
:
292 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
295 unreachable("not reached");
300 src_reg::equals(const src_reg
&r
) const
302 return (file
== r
.file
&&
304 reg_offset
== r
.reg_offset
&&
306 negate
== r
.negate
&&
308 swizzle
== r
.swizzle
&&
309 !reladdr
&& !r
.reladdr
&&
310 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
311 sizeof(fixed_hw_reg
)) == 0);
314 /* Replaces unused channels of a swizzle with channels that are used.
316 * For instance, this pass transforms
318 * mov vgrf4.yz, vgrf5.wxzy
322 * mov vgrf4.yz, vgrf5.xxzx
324 * This eliminates false uses of some channels, letting dead code elimination
325 * remove the instructions that wrote them.
328 vec4_visitor::opt_reduce_swizzle()
330 bool progress
= false;
332 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
333 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
)
338 /* Determine which channels of the sources are read. */
339 switch (inst
->opcode
) {
341 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
342 * but all four of src1.
362 swizzle
[0] = inst
->dst
.writemask
& WRITEMASK_X
? 0 : -1;
363 swizzle
[1] = inst
->dst
.writemask
& WRITEMASK_Y
? 1 : -1;
364 swizzle
[2] = inst
->dst
.writemask
& WRITEMASK_Z
? 2 : -1;
365 swizzle
[3] = inst
->dst
.writemask
& WRITEMASK_W
? 3 : -1;
369 /* Resolve unread channels (-1) by assigning them the swizzle of the
370 * first channel that is used.
372 int first_used_channel
= 0;
373 for (int i
= 0; i
< 4; i
++) {
374 if (swizzle
[i
] != -1) {
375 first_used_channel
= swizzle
[i
];
379 for (int i
= 0; i
< 4; i
++) {
380 if (swizzle
[i
] == -1) {
381 swizzle
[i
] = first_used_channel
;
385 /* Update sources' swizzles. */
386 for (int i
= 0; i
< 3; i
++) {
387 if (inst
->src
[i
].file
!= GRF
&&
388 inst
->src
[i
].file
!= ATTR
&&
389 inst
->src
[i
].file
!= UNIFORM
)
393 for (int j
= 0; j
< 4; j
++) {
394 swiz
[j
] = BRW_GET_SWZ(inst
->src
[i
].swizzle
, swizzle
[j
]);
397 unsigned new_swizzle
= BRW_SWIZZLE4(swiz
[0], swiz
[1], swiz
[2], swiz
[3]);
398 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
399 inst
->src
[i
].swizzle
= new_swizzle
;
406 invalidate_live_intervals();
412 try_eliminate_instruction(vec4_instruction
*inst
, int new_writemask
,
413 const struct brw_context
*brw
)
415 if (inst
->has_side_effects())
418 if (new_writemask
== 0) {
419 /* Don't dead code eliminate instructions that write to the
420 * accumulator as a side-effect. Instead just set the destination
421 * to the null register to free it.
423 if (inst
->writes_accumulator
|| inst
->writes_flag()) {
424 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
430 } else if (inst
->dst
.writemask
!= new_writemask
) {
431 switch (inst
->opcode
) {
432 case SHADER_OPCODE_TXF_CMS
:
433 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
434 case VS_OPCODE_PULL_CONSTANT_LOAD
:
435 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
438 /* Do not set a writemask on Gen6 for math instructions, those are
439 * executed using align1 mode that does not support a destination mask.
441 if (!(brw
->gen
== 6 && inst
->is_math()) && !inst
->is_tex()) {
442 inst
->dst
.writemask
= new_writemask
;
452 * Must be called after calculate_live_intervals() to remove unused
453 * writes to registers -- register allocation will fail otherwise
454 * because something deffed but not used won't be considered to
455 * interfere with other regs.
458 vec4_visitor::dead_code_eliminate()
460 bool progress
= false;
463 calculate_live_intervals();
465 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
468 bool inst_writes_flag
= false;
469 if (inst
->dst
.file
!= GRF
) {
470 if (inst
->dst
.is_null() && inst
->writes_flag()) {
471 inst_writes_flag
= true;
477 if (inst
->dst
.file
== GRF
) {
478 int write_mask
= inst
->dst
.writemask
;
480 for (int c
= 0; c
< 4; c
++) {
481 if (write_mask
& (1 << c
)) {
482 assert(this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] >= pc
);
483 if (this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] == pc
) {
484 write_mask
&= ~(1 << c
);
489 progress
= try_eliminate_instruction(inst
, write_mask
, brw
) ||
493 if (inst
->predicate
|| inst
->prev
== NULL
)
497 if (inst_writes_flag
) {
498 /* Arbitrarily chosen, other than not being an xyzw writemask. */
499 #define FLAG_WRITEMASK (1 << 5)
500 dead_channels
= inst
->reads_flag() ? 0 : FLAG_WRITEMASK
;
502 dead_channels
= inst
->dst
.writemask
;
504 for (int i
= 0; i
< 3; i
++) {
505 if (inst
->src
[i
].file
!= GRF
||
506 inst
->src
[i
].reg
!= inst
->dst
.reg
)
509 for (int j
= 0; j
< 4; j
++) {
510 int swiz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
511 dead_channels
&= ~(1 << swiz
);
516 for (exec_node
*node
= inst
->prev
, *prev
= node
->prev
;
517 prev
!= NULL
&& dead_channels
!= 0;
518 node
= prev
, prev
= prev
->prev
) {
519 vec4_instruction
*scan_inst
= (vec4_instruction
*)node
;
521 if (scan_inst
->is_control_flow())
524 if (inst_writes_flag
) {
525 if (scan_inst
->dst
.is_null() && scan_inst
->writes_flag()) {
529 } else if (scan_inst
->reads_flag()) {
534 if (inst
->dst
.file
== scan_inst
->dst
.file
&&
535 inst
->dst
.reg
== scan_inst
->dst
.reg
&&
536 inst
->dst
.reg_offset
== scan_inst
->dst
.reg_offset
) {
537 int new_writemask
= scan_inst
->dst
.writemask
& ~dead_channels
;
539 progress
= try_eliminate_instruction(scan_inst
, new_writemask
, brw
) ||
543 for (int i
= 0; i
< 3; i
++) {
544 if (scan_inst
->src
[i
].file
!= inst
->dst
.file
||
545 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
)
548 for (int j
= 0; j
< 4; j
++) {
549 int swiz
= BRW_GET_SWZ(scan_inst
->src
[i
].swizzle
, j
);
550 dead_channels
&= ~(1 << swiz
);
557 invalidate_live_intervals();
563 vec4_visitor::split_uniform_registers()
565 /* Prior to this, uniforms have been in an array sized according to
566 * the number of vector uniforms present, sparsely filled (so an
567 * aggregate results in reg indices being skipped over). Now we're
568 * going to cut those aggregates up so each .reg index is one
569 * vector. The goal is to make elimination of unused uniform
570 * components easier later.
572 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
573 for (int i
= 0 ; i
< 3; i
++) {
574 if (inst
->src
[i
].file
!= UNIFORM
)
577 assert(!inst
->src
[i
].reladdr
);
579 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
580 inst
->src
[i
].reg_offset
= 0;
584 /* Update that everything is now vector-sized. */
585 for (int i
= 0; i
< this->uniforms
; i
++) {
586 this->uniform_size
[i
] = 1;
591 vec4_visitor::pack_uniform_registers()
593 bool uniform_used
[this->uniforms
];
594 int new_loc
[this->uniforms
];
595 int new_chan
[this->uniforms
];
597 memset(uniform_used
, 0, sizeof(uniform_used
));
598 memset(new_loc
, 0, sizeof(new_loc
));
599 memset(new_chan
, 0, sizeof(new_chan
));
601 /* Find which uniform vectors are actually used by the program. We
602 * expect unused vector elements when we've moved array access out
603 * to pull constants, and from some GLSL code generators like wine.
605 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
606 for (int i
= 0 ; i
< 3; i
++) {
607 if (inst
->src
[i
].file
!= UNIFORM
)
610 uniform_used
[inst
->src
[i
].reg
] = true;
614 int new_uniform_count
= 0;
616 /* Now, figure out a packing of the live uniform vectors into our
619 for (int src
= 0; src
< uniforms
; src
++) {
620 assert(src
< uniform_array_size
);
621 int size
= this->uniform_vector_size
[src
];
623 if (!uniform_used
[src
]) {
624 this->uniform_vector_size
[src
] = 0;
629 /* Find the lowest place we can slot this uniform in. */
630 for (dst
= 0; dst
< src
; dst
++) {
631 if (this->uniform_vector_size
[dst
] + size
<= 4)
640 new_chan
[src
] = this->uniform_vector_size
[dst
];
642 /* Move the references to the data */
643 for (int j
= 0; j
< size
; j
++) {
644 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
645 stage_prog_data
->param
[src
* 4 + j
];
648 this->uniform_vector_size
[dst
] += size
;
649 this->uniform_vector_size
[src
] = 0;
652 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
655 this->uniforms
= new_uniform_count
;
657 /* Now, update the instructions for our repacked uniforms. */
658 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
659 for (int i
= 0 ; i
< 3; i
++) {
660 int src
= inst
->src
[i
].reg
;
662 if (inst
->src
[i
].file
!= UNIFORM
)
665 inst
->src
[i
].reg
= new_loc
[src
];
667 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
668 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
669 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
670 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
671 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
677 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
679 * While GLSL IR also performs this optimization, we end up with it in
680 * our instruction stream for a couple of reasons. One is that we
681 * sometimes generate silly instructions, for example in array access
682 * where we'll generate "ADD offset, index, base" even if base is 0.
683 * The other is that GLSL IR's constant propagation doesn't track the
684 * components of aggregates, so some VS patterns (initialize matrix to
685 * 0, accumulate in vertex blending factors) end up breaking down to
686 * instructions involving 0.
689 vec4_visitor::opt_algebraic()
691 bool progress
= false;
693 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
694 switch (inst
->opcode
) {
696 if (inst
->src
[1].is_zero()) {
697 inst
->opcode
= BRW_OPCODE_MOV
;
698 inst
->src
[1] = src_reg();
704 if (inst
->src
[1].is_zero()) {
705 inst
->opcode
= BRW_OPCODE_MOV
;
706 switch (inst
->src
[0].type
) {
707 case BRW_REGISTER_TYPE_F
:
708 inst
->src
[0] = src_reg(0.0f
);
710 case BRW_REGISTER_TYPE_D
:
711 inst
->src
[0] = src_reg(0);
713 case BRW_REGISTER_TYPE_UD
:
714 inst
->src
[0] = src_reg(0u);
717 unreachable("not reached");
719 inst
->src
[1] = src_reg();
721 } else if (inst
->src
[1].is_one()) {
722 inst
->opcode
= BRW_OPCODE_MOV
;
723 inst
->src
[1] = src_reg();
733 invalidate_live_intervals();
739 * Only a limited number of hardware registers may be used for push
740 * constants, so this turns access to the overflowed constants into
744 vec4_visitor::move_push_constants_to_pull_constants()
746 int pull_constant_loc
[this->uniforms
];
748 /* Only allow 32 registers (256 uniform components) as push constants,
749 * which is the limit on gen6.
751 * If changing this value, note the limitation about total_regs in
754 int max_uniform_components
= 32 * 8;
755 if (this->uniforms
* 4 <= max_uniform_components
)
758 /* Make some sort of choice as to which uniforms get sent to pull
759 * constants. We could potentially do something clever here like
760 * look for the most infrequently used uniform vec4s, but leave
763 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
764 pull_constant_loc
[i
/ 4] = -1;
766 if (i
>= max_uniform_components
) {
767 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
769 /* Try to find an existing copy of this uniform in the pull
770 * constants if it was part of an array access already.
772 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
775 for (matches
= 0; matches
< 4; matches
++) {
776 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
781 pull_constant_loc
[i
/ 4] = j
/ 4;
786 if (pull_constant_loc
[i
/ 4] == -1) {
787 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
788 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
790 for (int j
= 0; j
< 4; j
++) {
791 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
798 /* Now actually rewrite usage of the things we've moved to pull
801 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
802 for (int i
= 0 ; i
< 3; i
++) {
803 if (inst
->src
[i
].file
!= UNIFORM
||
804 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
807 int uniform
= inst
->src
[i
].reg
;
809 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
811 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
812 pull_constant_loc
[uniform
]);
814 inst
->src
[i
].file
= temp
.file
;
815 inst
->src
[i
].reg
= temp
.reg
;
816 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
817 inst
->src
[i
].reladdr
= NULL
;
821 /* Repack push constants to remove the now-unused ones. */
822 pack_uniform_registers();
826 * Sets the dependency control fields on instructions after register
827 * allocation and before the generator is run.
829 * When you have a sequence of instructions like:
831 * DP4 temp.x vertex uniform[0]
832 * DP4 temp.y vertex uniform[0]
833 * DP4 temp.z vertex uniform[0]
834 * DP4 temp.w vertex uniform[0]
836 * The hardware doesn't know that it can actually run the later instructions
837 * while the previous ones are in flight, producing stalls. However, we have
838 * manual fields we can set in the instructions that let it do so.
841 vec4_visitor::opt_set_dependency_control()
843 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
844 uint8_t grf_channels_written
[BRW_MAX_GRF
];
845 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
846 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
850 assert(prog_data
->total_grf
||
851 !"Must be called after register allocation");
853 foreach_block (block
, cfg
) {
854 memset(last_grf_write
, 0, sizeof(last_grf_write
));
855 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
857 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
858 /* If we read from a register that we were doing dependency control
859 * on, don't do dependency control across the read.
861 for (int i
= 0; i
< 3; i
++) {
862 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
863 if (inst
->src
[i
].file
== GRF
) {
864 last_grf_write
[reg
] = NULL
;
865 } else if (inst
->src
[i
].file
== HW_REG
) {
866 memset(last_grf_write
, 0, sizeof(last_grf_write
));
869 assert(inst
->src
[i
].file
!= MRF
);
872 /* In the presence of send messages, totally interrupt dependency
873 * control. They're long enough that the chance of dependency
874 * control around them just doesn't matter.
877 memset(last_grf_write
, 0, sizeof(last_grf_write
));
878 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
882 /* It looks like setting dependency control on a predicated
883 * instruction hangs the GPU.
885 if (inst
->predicate
) {
886 memset(last_grf_write
, 0, sizeof(last_grf_write
));
887 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
891 /* Dependency control does not work well over math instructions.
893 if (inst
->is_math()) {
894 memset(last_grf_write
, 0, sizeof(last_grf_write
));
895 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
899 /* Now, see if we can do dependency control for this instruction
900 * against a previous one writing to its destination.
902 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
903 if (inst
->dst
.file
== GRF
) {
904 if (last_grf_write
[reg
] &&
905 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
906 last_grf_write
[reg
]->no_dd_clear
= true;
907 inst
->no_dd_check
= true;
909 grf_channels_written
[reg
] = 0;
912 last_grf_write
[reg
] = inst
;
913 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
914 } else if (inst
->dst
.file
== MRF
) {
915 if (last_mrf_write
[reg
] &&
916 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
917 last_mrf_write
[reg
]->no_dd_clear
= true;
918 inst
->no_dd_check
= true;
920 mrf_channels_written
[reg
] = 0;
923 last_mrf_write
[reg
] = inst
;
924 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
925 } else if (inst
->dst
.reg
== HW_REG
) {
926 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
927 memset(last_grf_write
, 0, sizeof(last_grf_write
));
928 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
929 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
936 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
940 /* If this instruction sets anything not referenced by swizzle, then we'd
941 * totally break it when we reswizzle.
943 if (dst
.writemask
& ~swizzle_mask
)
948 if (!brw_is_single_value_swizzle(swizzle
)) {
949 /* Check if there happens to be no reswizzling required. */
950 for (int c
= 0; c
< 4; c
++) {
951 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
952 /* Skip components of the swizzle not used by the dst. */
953 if (!(dst_writemask
& (1 << c
)))
956 /* We don't do the reswizzling yet, so just sanity check that we
973 * For any channels in the swizzle's source that were populated by this
974 * instruction, rewrite the instruction to put the appropriate result directly
977 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
980 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
982 int new_writemask
= 0;
986 if (!brw_is_single_value_swizzle(swizzle
)) {
987 for (int c
= 0; c
< 4; c
++) {
988 /* Skip components of the swizzle not used by the dst. */
989 if (!(dst_writemask
& (1 << c
)))
992 /* We don't do the reswizzling yet, so just sanity check that we
995 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
1000 case BRW_OPCODE_DP4
:
1001 case BRW_OPCODE_DP3
:
1002 case BRW_OPCODE_DP2
:
1003 for (int c
= 0; c
< 4; c
++) {
1004 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
1005 /* Skip components of the swizzle not used by the dst. */
1006 if (!(dst_writemask
& (1 << c
)))
1008 /* If we were populating this component, then populate the
1009 * corresponding channel of the new dst.
1011 if (dst
.writemask
& bit
)
1012 new_writemask
|= (1 << c
);
1014 dst
.writemask
= new_writemask
;
1020 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1021 * just written and then MOVed into another reg and making the original write
1022 * of the GRF write directly to the final destination instead.
1025 vec4_visitor::opt_register_coalesce()
1027 bool progress
= false;
1030 calculate_live_intervals();
1032 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
1036 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1037 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1039 inst
->src
[0].file
!= GRF
||
1040 inst
->dst
.type
!= inst
->src
[0].type
||
1041 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1044 bool to_mrf
= (inst
->dst
.file
== MRF
);
1046 /* Can't coalesce this GRF if someone else was going to
1049 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1050 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1051 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1052 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1055 /* We need to check interference with the final destination between this
1056 * instruction and the earliest instruction involved in writing the GRF
1057 * we're eliminating. To do that, keep track of which of our source
1058 * channels we've seen initialized.
1060 bool chans_needed
[4] = {false, false, false, false};
1061 int chans_remaining
= 0;
1062 int swizzle_mask
= 0;
1063 for (int i
= 0; i
< 4; i
++) {
1064 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1066 if (!(inst
->dst
.writemask
& (1 << i
)))
1069 swizzle_mask
|= (1 << chan
);
1071 if (!chans_needed
[chan
]) {
1072 chans_needed
[chan
] = true;
1077 /* Now walk up the instruction stream trying to see if we can rewrite
1078 * everything writing to the temporary to write into the destination
1081 vec4_instruction
*scan_inst
;
1082 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
1083 scan_inst
->prev
!= NULL
;
1084 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
1085 if (scan_inst
->dst
.file
== GRF
&&
1086 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1087 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1088 /* Found something writing to the reg we want to coalesce away. */
1090 /* SEND instructions can't have MRF as a destination. */
1091 if (scan_inst
->mlen
)
1094 if (brw
->gen
== 6) {
1095 /* gen6 math instructions must have the destination be
1096 * GRF, so no compute-to-MRF for them.
1098 if (scan_inst
->is_math()) {
1104 /* If we can't handle the swizzle, bail. */
1105 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
1106 inst
->src
[0].swizzle
,
1111 /* Mark which channels we found unconditional writes for. */
1112 if (!scan_inst
->predicate
) {
1113 for (int i
= 0; i
< 4; i
++) {
1114 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1116 chans_needed
[i
] = false;
1122 if (chans_remaining
== 0)
1126 /* We don't handle flow control here. Most computation of values
1127 * that could be coalesced happens just before their use.
1129 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1130 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1131 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1132 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1136 /* You can't read from an MRF, so if someone else reads our MRF's
1137 * source GRF that we wanted to rewrite, that stops us. If it's a
1138 * GRF we're trying to coalesce to, we don't actually handle
1139 * rewriting sources so bail in that case as well.
1141 bool interfered
= false;
1142 for (int i
= 0; i
< 3; i
++) {
1143 if (scan_inst
->src
[i
].file
== GRF
&&
1144 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1145 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1152 /* If somebody else writes our destination here, we can't coalesce
1155 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1156 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1160 /* Check for reads of the register we're trying to coalesce into. We
1161 * can't go rewriting instructions above that to put some other value
1162 * in the register instead.
1164 if (to_mrf
&& scan_inst
->mlen
> 0) {
1165 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1166 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1170 for (int i
= 0; i
< 3; i
++) {
1171 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1172 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1173 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1182 if (chans_remaining
== 0) {
1183 /* If we've made it here, we have an MOV we want to coalesce out, and
1184 * a scan_inst pointing to the earliest instruction involved in
1185 * computing the value. Now go rewrite the instruction stream
1189 while (scan_inst
!= inst
) {
1190 if (scan_inst
->dst
.file
== GRF
&&
1191 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1192 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1193 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1194 inst
->src
[0].swizzle
);
1195 scan_inst
->dst
.file
= inst
->dst
.file
;
1196 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1197 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1198 scan_inst
->saturate
|= inst
->saturate
;
1200 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1208 invalidate_live_intervals();
1214 * Splits virtual GRFs requesting more than one contiguous physical register.
1216 * We initially create large virtual GRFs for temporary structures, arrays,
1217 * and matrices, so that the dereference visitor functions can add reg_offsets
1218 * to work their way down to the actual member being accessed. But when it
1219 * comes to optimization, we'd like to treat each register as individual
1220 * storage if possible.
1222 * So far, the only thing that might prevent splitting is a send message from
1226 vec4_visitor::split_virtual_grfs()
1228 int num_vars
= this->virtual_grf_count
;
1229 int new_virtual_grf
[num_vars
];
1230 bool split_grf
[num_vars
];
1232 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1234 /* Try to split anything > 0 sized. */
1235 for (int i
= 0; i
< num_vars
; i
++) {
1236 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1239 /* Check that the instructions are compatible with the registers we're trying
1242 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1243 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1246 if (inst
->is_send_from_grf()) {
1247 for (int i
= 0; i
< 3; i
++) {
1248 if (inst
->src
[i
].file
== GRF
) {
1249 split_grf
[inst
->src
[i
].reg
] = false;
1255 /* Allocate new space for split regs. Note that the virtual
1256 * numbers will be contiguous.
1258 for (int i
= 0; i
< num_vars
; i
++) {
1262 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1263 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1264 int reg
= virtual_grf_alloc(1);
1265 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1268 this->virtual_grf_sizes
[i
] = 1;
1271 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1272 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1273 inst
->dst
.reg_offset
!= 0) {
1274 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1275 inst
->dst
.reg_offset
- 1);
1276 inst
->dst
.reg_offset
= 0;
1278 for (int i
= 0; i
< 3; i
++) {
1279 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1280 inst
->src
[i
].reg_offset
!= 0) {
1281 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1282 inst
->src
[i
].reg_offset
- 1);
1283 inst
->src
[i
].reg_offset
= 0;
1287 invalidate_live_intervals();
1291 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1293 dump_instruction(be_inst
, stderr
);
1297 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1299 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1301 if (inst
->predicate
) {
1302 fprintf(file
, "(%cf0) ",
1303 inst
->predicate_inverse
? '-' : '+');
1306 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1307 if (inst
->conditional_mod
) {
1308 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1312 switch (inst
->dst
.file
) {
1314 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1317 fprintf(file
, "m%d", inst
->dst
.reg
);
1320 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1321 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1323 fprintf(file
, "null");
1325 case BRW_ARF_ADDRESS
:
1326 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1328 case BRW_ARF_ACCUMULATOR
:
1329 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1332 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1333 inst
->dst
.fixed_hw_reg
.subnr
);
1336 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1337 inst
->dst
.fixed_hw_reg
.subnr
);
1341 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1343 if (inst
->dst
.fixed_hw_reg
.subnr
)
1344 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1347 fprintf(file
, "(null)");
1350 fprintf(file
, "???");
1353 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1355 if (inst
->dst
.writemask
& 1)
1357 if (inst
->dst
.writemask
& 2)
1359 if (inst
->dst
.writemask
& 4)
1361 if (inst
->dst
.writemask
& 8)
1364 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
1366 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1367 if (inst
->src
[i
].negate
)
1369 if (inst
->src
[i
].abs
)
1371 switch (inst
->src
[i
].file
) {
1373 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1376 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1379 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1382 switch (inst
->src
[i
].type
) {
1383 case BRW_REGISTER_TYPE_F
:
1384 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1386 case BRW_REGISTER_TYPE_D
:
1387 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1389 case BRW_REGISTER_TYPE_UD
:
1390 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1393 fprintf(file
, "???");
1398 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1400 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1402 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1403 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1405 fprintf(file
, "null");
1407 case BRW_ARF_ADDRESS
:
1408 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1410 case BRW_ARF_ACCUMULATOR
:
1411 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1414 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1415 inst
->src
[i
].fixed_hw_reg
.subnr
);
1418 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1419 inst
->src
[i
].fixed_hw_reg
.subnr
);
1423 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1425 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1426 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1427 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1431 fprintf(file
, "(null)");
1434 fprintf(file
, "???");
1438 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1439 if (inst
->src
[i
].reg_offset
!= 0 &&
1440 inst
->src
[i
].file
== GRF
&&
1441 virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1442 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1444 if (inst
->src
[i
].file
!= IMM
) {
1445 static const char *chans
[4] = {"x", "y", "z", "w"};
1447 for (int c
= 0; c
< 4; c
++) {
1448 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1452 if (inst
->src
[i
].abs
)
1455 if (inst
->src
[i
].file
!= IMM
) {
1456 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1459 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1460 fprintf(file
, ", ");
1463 fprintf(file
, "\n");
1467 static inline struct brw_reg
1468 attribute_to_hw_reg(int attr
, bool interleaved
)
1471 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1473 return brw_vec8_grf(attr
, 0);
1478 * Replace each register of type ATTR in this->instructions with a reference
1479 * to a fixed HW register.
1481 * If interleaved is true, then each attribute takes up half a register, with
1482 * register N containing attribute 2*N in its first half and attribute 2*N+1
1483 * in its second half (this corresponds to the payload setup used by geometry
1484 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1485 * false, then each attribute takes up a whole register, with register N
1486 * containing attribute N (this corresponds to the payload setup used by
1487 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1490 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1493 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1494 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1495 if (inst
->dst
.file
== ATTR
) {
1496 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1498 /* All attributes used in the shader need to have been assigned a
1499 * hardware register by the caller
1503 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1504 reg
.type
= inst
->dst
.type
;
1505 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1507 inst
->dst
.file
= HW_REG
;
1508 inst
->dst
.fixed_hw_reg
= reg
;
1511 for (int i
= 0; i
< 3; i
++) {
1512 if (inst
->src
[i
].file
!= ATTR
)
1515 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1517 /* All attributes used in the shader need to have been assigned a
1518 * hardware register by the caller
1522 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1523 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1524 reg
.type
= inst
->src
[i
].type
;
1525 if (inst
->src
[i
].abs
)
1527 if (inst
->src
[i
].negate
)
1530 inst
->src
[i
].file
= HW_REG
;
1531 inst
->src
[i
].fixed_hw_reg
= reg
;
1537 vec4_vs_visitor::setup_attributes(int payload_reg
)
1540 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1541 memset(attribute_map
, 0, sizeof(attribute_map
));
1544 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1545 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1546 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1551 /* VertexID is stored by the VF as the last vertex element, but we
1552 * don't represent it with a flag in inputs_read, so we call it
1555 if (vs_prog_data
->uses_vertexid
) {
1556 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1560 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1562 /* The BSpec says we always have to read at least one thing from
1563 * the VF, and it appears that the hardware wedges otherwise.
1565 if (nr_attributes
== 0)
1568 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1570 unsigned vue_entries
=
1571 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1574 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1576 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1578 return payload_reg
+ nr_attributes
;
1582 vec4_visitor::setup_uniforms(int reg
)
1584 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1586 /* The pre-gen6 VS requires that some push constants get loaded no
1587 * matter what, or the GPU would hang.
1589 if (brw
->gen
< 6 && this->uniforms
== 0) {
1590 assert(this->uniforms
< this->uniform_array_size
);
1591 this->uniform_vector_size
[this->uniforms
] = 1;
1593 stage_prog_data
->param
=
1594 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1595 for (unsigned int i
= 0; i
< 4; i
++) {
1596 unsigned int slot
= this->uniforms
* 4 + i
;
1597 static gl_constant_value zero
= { 0.0 };
1598 stage_prog_data
->param
[slot
] = &zero
;
1604 reg
+= ALIGN(uniforms
, 2) / 2;
1607 stage_prog_data
->nr_params
= this->uniforms
* 4;
1609 prog_data
->curb_read_length
= reg
- prog_data
->base
.dispatch_grf_start_reg
;
1615 vec4_vs_visitor::setup_payload(void)
1619 /* The payload always contains important data in g0, which contains
1620 * the URB handles that are passed on to the URB write at the end
1621 * of the thread. So, we always start push constants at g1.
1625 reg
= setup_uniforms(reg
);
1627 reg
= setup_attributes(reg
);
1629 this->first_non_payload_grf
= reg
;
1633 vec4_visitor::get_timestamp()
1635 assert(brw
->gen
>= 7);
1637 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1640 BRW_REGISTER_TYPE_UD
,
1641 BRW_VERTICAL_STRIDE_0
,
1643 BRW_HORIZONTAL_STRIDE_4
,
1647 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1649 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1650 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1651 * even if it's not enabled in the dispatch.
1653 mov
->force_writemask_all
= true;
1655 return src_reg(dst
);
1659 vec4_visitor::emit_shader_time_begin()
1661 current_annotation
= "shader time start";
1662 shader_start_time
= get_timestamp();
1666 vec4_visitor::emit_shader_time_end()
1668 current_annotation
= "shader time end";
1669 src_reg shader_end_time
= get_timestamp();
1672 /* Check that there weren't any timestamp reset events (assuming these
1673 * were the only two timestamp reads that happened).
1675 src_reg reset_end
= shader_end_time
;
1676 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1677 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1678 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1680 emit(IF(BRW_PREDICATE_NORMAL
));
1682 /* Take the current timestamp and get the delta. */
1683 shader_start_time
.negate
= true;
1684 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1685 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1687 /* If there were no instructions between the two timestamp gets, the diff
1688 * is 2 cycles. Remove that overhead, so I can forget about that when
1689 * trying to determine the time taken for single instructions.
1691 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1693 emit_shader_time_write(st_base
, src_reg(diff
));
1694 emit_shader_time_write(st_written
, src_reg(1u));
1695 emit(BRW_OPCODE_ELSE
);
1696 emit_shader_time_write(st_reset
, src_reg(1u));
1697 emit(BRW_OPCODE_ENDIF
);
1701 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1704 int shader_time_index
=
1705 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1708 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1710 dst_reg offset
= dst
;
1714 offset
.type
= BRW_REGISTER_TYPE_UD
;
1715 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1717 time
.type
= BRW_REGISTER_TYPE_UD
;
1718 emit(MOV(time
, src_reg(value
)));
1720 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1726 sanity_param_count
= prog
->Parameters
->NumParameters
;
1728 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1729 emit_shader_time_begin();
1731 assign_common_binding_table_offsets(0);
1735 /* Generate VS IR for main(). (the visitor only descends into
1736 * functions called "main").
1739 visit_instructions(shader
->base
.ir
);
1741 emit_program_code();
1745 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1746 setup_uniform_clipplane_values();
1750 /* Before any optimization, push array accesses out to scratch
1751 * space where we need them to be. This pass may allocate new
1752 * virtual GRFs, so we want to do it early. It also makes sure
1753 * that we have reladdr computations available for CSE, since we'll
1754 * often do repeated subexpressions for those.
1757 move_grf_array_access_to_scratch();
1758 move_uniform_array_access_to_pull_constants();
1760 /* The ARB_vertex_program frontend emits pull constant loads directly
1761 * rather than using reladdr, so we don't need to walk through all the
1762 * instructions looking for things to move. There isn't anything.
1764 * We do still need to split things to vec4 size.
1766 split_uniform_registers();
1768 pack_uniform_registers();
1769 move_push_constants_to_pull_constants();
1770 split_virtual_grfs();
1772 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1774 #define OPT(pass, args...) do { \
1776 bool this_progress = pass(args); \
1778 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1779 char filename[64]; \
1780 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1781 stage_name, shader_prog->Name, iteration, pass_num); \
1783 backend_visitor::dump_instructions(filename); \
1786 progress = progress || this_progress; \
1790 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1792 snprintf(filename
, 64, "%s-%04d-00-start",
1793 stage_name
, shader_prog
->Name
);
1795 backend_visitor::dump_instructions(filename
);
1805 OPT(opt_reduce_swizzle
);
1806 OPT(dead_code_eliminate
);
1807 OPT(dead_control_flow_eliminate
, this);
1808 OPT(opt_copy_propagation
);
1811 OPT(opt_register_coalesce
);
1821 /* Debug of register spilling: Go spill everything. */
1822 const int grf_count
= virtual_grf_count
;
1823 float spill_costs
[virtual_grf_count
];
1824 bool no_spill
[virtual_grf_count
];
1825 evaluate_spill_costs(spill_costs
, no_spill
);
1826 for (int i
= 0; i
< grf_count
; i
++) {
1833 while (!reg_allocate()) {
1838 opt_schedule_instructions();
1840 opt_set_dependency_control();
1842 /* If any state parameters were appended, then ParameterValues could have
1843 * been realloced, in which case the driver uniform storage set up by
1844 * _mesa_associate_uniform_storage() would point to freed memory. Make
1845 * sure that didn't happen.
1847 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1854 } /* namespace brw */
1859 * Compile a vertex shader.
1861 * Returns the final assembly and the program's size.
1864 brw_vs_emit(struct brw_context
*brw
,
1865 struct gl_shader_program
*prog
,
1866 struct brw_vs_compile
*c
,
1867 struct brw_vs_prog_data
*prog_data
,
1869 unsigned *final_assembly_size
)
1871 bool start_busy
= false;
1872 double start_time
= 0;
1874 if (unlikely(brw
->perf_debug
)) {
1875 start_busy
= (brw
->batch
.last_bo
&&
1876 drm_intel_bo_busy(brw
->batch
.last_bo
));
1877 start_time
= get_time();
1880 struct brw_shader
*shader
= NULL
;
1882 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1884 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1885 brw_dump_ir(brw
, "vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1887 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1890 prog
->LinkStatus
= false;
1891 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1894 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1900 const unsigned *assembly
= NULL
;
1901 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1902 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1903 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1905 if (unlikely(brw
->perf_debug
) && shader
) {
1906 if (shader
->compiled_once
) {
1907 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1909 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1910 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1911 (get_time() - start_time
) * 1000);
1913 shader
->compiled_once
= true;
1921 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1922 struct brw_vec4_prog_key
*key
,
1923 GLuint id
, struct gl_program
*prog
)
1925 key
->program_string_id
= id
;
1926 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1928 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1929 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1930 if (prog
->ShadowSamplers
& (1 << i
)) {
1931 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1932 key
->tex
.swizzles
[i
] =
1933 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1935 /* Color sampler: assume no swizzling. */
1936 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;