2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_dead_control_flow.h"
31 #include "main/macros.h"
32 #include "main/shaderobj.h"
33 #include "program/prog_print.h"
34 #include "program/prog_parameter.h"
37 #define MAX_INSTRUCTION (1 << 30)
44 * Common helper for constructing swizzles. When only a subset of
45 * channels of a vec4 are used, we don't want to reference the other
46 * channels, as that will tell optimization passes that those other
50 swizzle_for_size(int size
)
52 static const unsigned size_swizzles
[4] = {
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
56 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
59 assert((size
>= 1) && (size
<= 4));
60 return size_swizzles
[size
- 1];
66 memset(this, 0, sizeof(*this));
68 this->file
= BAD_FILE
;
71 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= BRW_SWIZZLE_XYZW
;
83 /** Generic unset register constructor. */
89 src_reg::src_reg(float f
)
94 this->type
= BRW_REGISTER_TYPE_F
;
95 this->fixed_hw_reg
.dw1
.f
= f
;
98 src_reg::src_reg(uint32_t u
)
103 this->type
= BRW_REGISTER_TYPE_UD
;
104 this->fixed_hw_reg
.dw1
.ud
= u
;
107 src_reg::src_reg(int32_t i
)
112 this->type
= BRW_REGISTER_TYPE_D
;
113 this->fixed_hw_reg
.dw1
.d
= i
;
116 src_reg::src_reg(uint8_t vf
[4])
121 this->type
= BRW_REGISTER_TYPE_VF
;
122 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
125 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
130 this->type
= BRW_REGISTER_TYPE_VF
;
131 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
137 src_reg::src_reg(struct brw_reg reg
)
142 this->fixed_hw_reg
= reg
;
143 this->type
= reg
.type
;
146 src_reg::src_reg(dst_reg reg
)
150 this->file
= reg
.file
;
152 this->reg_offset
= reg
.reg_offset
;
153 this->type
= reg
.type
;
154 this->reladdr
= reg
.reladdr
;
155 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
161 for (int i
= 0; i
< 4; i
++) {
162 if (!(reg
.writemask
& (1 << i
)))
165 swizzles
[next_chan
++] = last
= i
;
168 for (; next_chan
< 4; next_chan
++) {
169 swizzles
[next_chan
] = last
;
172 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
173 swizzles
[2], swizzles
[3]);
179 memset(this, 0, sizeof(*this));
180 this->file
= BAD_FILE
;
181 this->writemask
= WRITEMASK_XYZW
;
189 dst_reg::dst_reg(register_file file
, int reg
)
197 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
204 this->type
= brw_type_for_base_type(type
);
205 this->writemask
= writemask
;
208 dst_reg::dst_reg(struct brw_reg reg
)
213 this->fixed_hw_reg
= reg
;
214 this->type
= reg
.type
;
217 dst_reg::dst_reg(src_reg reg
)
221 this->file
= reg
.file
;
223 this->reg_offset
= reg
.reg_offset
;
224 this->type
= reg
.type
;
225 /* How should we do writemasking when converting from a src_reg? It seems
226 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
227 * what about for src.wx? Just special-case src.xxxx for now.
229 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
230 this->writemask
= WRITEMASK_X
;
232 this->writemask
= WRITEMASK_XYZW
;
233 this->reladdr
= reg
.reladdr
;
234 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
238 dst_reg::equals(const dst_reg
&r
) const
240 return (file
== r
.file
&&
242 reg_offset
== r
.reg_offset
&&
244 negate
== r
.negate
&&
246 writemask
== r
.writemask
&&
247 (reladdr
== r
.reladdr
||
248 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
249 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
250 sizeof(fixed_hw_reg
)) == 0);
254 vec4_instruction::is_send_from_grf()
257 case SHADER_OPCODE_SHADER_TIME_ADD
:
258 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
266 vec4_instruction::regs_read(unsigned arg
) const
268 if (src
[arg
].file
== BAD_FILE
)
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 return arg
== 0 ? mlen
: 1;
275 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
276 return arg
== 1 ? mlen
: 1;
284 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
286 if (brw
->gen
== 6 && is_math())
289 if (is_send_from_grf())
292 if (!backend_instruction::can_do_source_mods())
299 * Returns how many MRFs an opcode will write over.
301 * Note that this is not the 0 or 1 implied writes in an actual gen
302 * instruction -- the generate_* functions generate additional MOVs
306 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
308 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
311 switch (inst
->opcode
) {
312 case SHADER_OPCODE_RCP
:
313 case SHADER_OPCODE_RSQ
:
314 case SHADER_OPCODE_SQRT
:
315 case SHADER_OPCODE_EXP2
:
316 case SHADER_OPCODE_LOG2
:
317 case SHADER_OPCODE_SIN
:
318 case SHADER_OPCODE_COS
:
320 case SHADER_OPCODE_INT_QUOTIENT
:
321 case SHADER_OPCODE_INT_REMAINDER
:
322 case SHADER_OPCODE_POW
:
324 case VS_OPCODE_URB_WRITE
:
326 case VS_OPCODE_PULL_CONSTANT_LOAD
:
328 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
330 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
332 case GS_OPCODE_URB_WRITE
:
333 case GS_OPCODE_URB_WRITE_ALLOCATE
:
334 case GS_OPCODE_THREAD_END
:
336 case GS_OPCODE_FF_SYNC
:
338 case SHADER_OPCODE_SHADER_TIME_ADD
:
340 case SHADER_OPCODE_TEX
:
341 case SHADER_OPCODE_TXL
:
342 case SHADER_OPCODE_TXD
:
343 case SHADER_OPCODE_TXF
:
344 case SHADER_OPCODE_TXF_CMS
:
345 case SHADER_OPCODE_TXF_MCS
:
346 case SHADER_OPCODE_TXS
:
347 case SHADER_OPCODE_TG4
:
348 case SHADER_OPCODE_TG4_OFFSET
:
349 return inst
->header_present
? 1 : 0;
350 case SHADER_OPCODE_UNTYPED_ATOMIC
:
351 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
354 unreachable("not reached");
359 src_reg::equals(const src_reg
&r
) const
361 return (file
== r
.file
&&
363 reg_offset
== r
.reg_offset
&&
365 negate
== r
.negate
&&
367 swizzle
== r
.swizzle
&&
368 !reladdr
&& !r
.reladdr
&&
369 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
370 sizeof(fixed_hw_reg
)) == 0);
374 vec4_visitor::opt_vector_float()
376 bool progress
= false;
378 int last_reg
= -1, last_reg_offset
= -1;
379 enum register_file last_reg_file
= BAD_FILE
;
381 int remaining_channels
= 0;
384 vec4_instruction
*imm_inst
[4];
386 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
387 if (last_reg
!= inst
->dst
.reg
||
388 last_reg_offset
!= inst
->dst
.reg_offset
||
389 last_reg_file
!= inst
->dst
.file
) {
390 last_reg
= inst
->dst
.reg
;
391 last_reg_offset
= inst
->dst
.reg_offset
;
392 last_reg_file
= inst
->dst
.file
;
393 remaining_channels
= WRITEMASK_XYZW
;
398 if (inst
->opcode
!= BRW_OPCODE_MOV
||
399 inst
->dst
.writemask
== WRITEMASK_XYZW
||
400 inst
->src
[0].file
!= IMM
)
403 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
407 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
409 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
411 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
413 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
416 imm_inst
[inst_count
++] = inst
;
418 remaining_channels
&= ~inst
->dst
.writemask
;
419 if (remaining_channels
== 0) {
420 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
421 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
422 mov
->dst
.writemask
= WRITEMASK_XYZW
;
423 inst
->insert_after(block
, mov
);
426 for (int i
= 0; i
< inst_count
; i
++) {
427 imm_inst
[i
]->remove(block
);
434 invalidate_live_intervals();
439 /* Replaces unused channels of a swizzle with channels that are used.
441 * For instance, this pass transforms
443 * mov vgrf4.yz, vgrf5.wxzy
447 * mov vgrf4.yz, vgrf5.xxzx
449 * This eliminates false uses of some channels, letting dead code elimination
450 * remove the instructions that wrote them.
453 vec4_visitor::opt_reduce_swizzle()
455 bool progress
= false;
457 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
458 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
459 inst
->is_send_from_grf())
464 /* Determine which channels of the sources are read. */
465 switch (inst
->opcode
) {
466 case VEC4_OPCODE_PACK_BYTES
:
468 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
469 * but all four of src1.
471 swizzle
= brw_swizzle_for_size(4);
474 swizzle
= brw_swizzle_for_size(3);
477 swizzle
= brw_swizzle_for_size(2);
480 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
484 /* Update sources' swizzles. */
485 for (int i
= 0; i
< 3; i
++) {
486 if (inst
->src
[i
].file
!= GRF
&&
487 inst
->src
[i
].file
!= ATTR
&&
488 inst
->src
[i
].file
!= UNIFORM
)
491 const unsigned new_swizzle
=
492 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
493 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
494 inst
->src
[i
].swizzle
= new_swizzle
;
501 invalidate_live_intervals();
507 vec4_visitor::split_uniform_registers()
509 /* Prior to this, uniforms have been in an array sized according to
510 * the number of vector uniforms present, sparsely filled (so an
511 * aggregate results in reg indices being skipped over). Now we're
512 * going to cut those aggregates up so each .reg index is one
513 * vector. The goal is to make elimination of unused uniform
514 * components easier later.
516 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
517 for (int i
= 0 ; i
< 3; i
++) {
518 if (inst
->src
[i
].file
!= UNIFORM
)
521 assert(!inst
->src
[i
].reladdr
);
523 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
524 inst
->src
[i
].reg_offset
= 0;
528 /* Update that everything is now vector-sized. */
529 for (int i
= 0; i
< this->uniforms
; i
++) {
530 this->uniform_size
[i
] = 1;
535 vec4_visitor::pack_uniform_registers()
537 bool uniform_used
[this->uniforms
];
538 int new_loc
[this->uniforms
];
539 int new_chan
[this->uniforms
];
541 memset(uniform_used
, 0, sizeof(uniform_used
));
542 memset(new_loc
, 0, sizeof(new_loc
));
543 memset(new_chan
, 0, sizeof(new_chan
));
545 /* Find which uniform vectors are actually used by the program. We
546 * expect unused vector elements when we've moved array access out
547 * to pull constants, and from some GLSL code generators like wine.
549 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
550 for (int i
= 0 ; i
< 3; i
++) {
551 if (inst
->src
[i
].file
!= UNIFORM
)
554 uniform_used
[inst
->src
[i
].reg
] = true;
558 int new_uniform_count
= 0;
560 /* Now, figure out a packing of the live uniform vectors into our
563 for (int src
= 0; src
< uniforms
; src
++) {
564 assert(src
< uniform_array_size
);
565 int size
= this->uniform_vector_size
[src
];
567 if (!uniform_used
[src
]) {
568 this->uniform_vector_size
[src
] = 0;
573 /* Find the lowest place we can slot this uniform in. */
574 for (dst
= 0; dst
< src
; dst
++) {
575 if (this->uniform_vector_size
[dst
] + size
<= 4)
584 new_chan
[src
] = this->uniform_vector_size
[dst
];
586 /* Move the references to the data */
587 for (int j
= 0; j
< size
; j
++) {
588 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
589 stage_prog_data
->param
[src
* 4 + j
];
592 this->uniform_vector_size
[dst
] += size
;
593 this->uniform_vector_size
[src
] = 0;
596 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
599 this->uniforms
= new_uniform_count
;
601 /* Now, update the instructions for our repacked uniforms. */
602 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
603 for (int i
= 0 ; i
< 3; i
++) {
604 int src
= inst
->src
[i
].reg
;
606 if (inst
->src
[i
].file
!= UNIFORM
)
609 inst
->src
[i
].reg
= new_loc
[src
];
611 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
612 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
613 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
614 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
615 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
621 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
623 * While GLSL IR also performs this optimization, we end up with it in
624 * our instruction stream for a couple of reasons. One is that we
625 * sometimes generate silly instructions, for example in array access
626 * where we'll generate "ADD offset, index, base" even if base is 0.
627 * The other is that GLSL IR's constant propagation doesn't track the
628 * components of aggregates, so some VS patterns (initialize matrix to
629 * 0, accumulate in vertex blending factors) end up breaking down to
630 * instructions involving 0.
633 vec4_visitor::opt_algebraic()
635 bool progress
= false;
637 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
638 switch (inst
->opcode
) {
640 if (inst
->src
[0].file
!= IMM
)
643 if (inst
->saturate
) {
644 if (inst
->dst
.type
!= inst
->src
[0].type
)
645 assert(!"unimplemented: saturate mixed types");
647 if (brw_saturate_immediate(inst
->dst
.type
,
648 &inst
->src
[0].fixed_hw_reg
)) {
649 inst
->saturate
= false;
655 case VEC4_OPCODE_UNPACK_UNIFORM
:
656 if (inst
->src
[0].file
!= UNIFORM
) {
657 inst
->opcode
= BRW_OPCODE_MOV
;
663 if (inst
->src
[1].is_zero()) {
664 inst
->opcode
= BRW_OPCODE_MOV
;
665 inst
->src
[1] = src_reg();
671 if (inst
->src
[1].is_zero()) {
672 inst
->opcode
= BRW_OPCODE_MOV
;
673 switch (inst
->src
[0].type
) {
674 case BRW_REGISTER_TYPE_F
:
675 inst
->src
[0] = src_reg(0.0f
);
677 case BRW_REGISTER_TYPE_D
:
678 inst
->src
[0] = src_reg(0);
680 case BRW_REGISTER_TYPE_UD
:
681 inst
->src
[0] = src_reg(0u);
684 unreachable("not reached");
686 inst
->src
[1] = src_reg();
688 } else if (inst
->src
[1].is_one()) {
689 inst
->opcode
= BRW_OPCODE_MOV
;
690 inst
->src
[1] = src_reg();
692 } else if (inst
->src
[1].is_negative_one()) {
693 inst
->opcode
= BRW_OPCODE_MOV
;
694 inst
->src
[0].negate
= !inst
->src
[0].negate
;
695 inst
->src
[1] = src_reg();
700 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
702 inst
->src
[0].negate
&&
703 inst
->src
[1].is_zero()) {
704 inst
->src
[0].abs
= false;
705 inst
->src
[0].negate
= false;
706 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
711 case SHADER_OPCODE_RCP
: {
712 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
713 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
714 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
715 inst
->opcode
= SHADER_OPCODE_RSQ
;
716 inst
->src
[0] = prev
->src
[0];
728 invalidate_live_intervals();
734 * Only a limited number of hardware registers may be used for push
735 * constants, so this turns access to the overflowed constants into
739 vec4_visitor::move_push_constants_to_pull_constants()
741 int pull_constant_loc
[this->uniforms
];
743 /* Only allow 32 registers (256 uniform components) as push constants,
744 * which is the limit on gen6.
746 * If changing this value, note the limitation about total_regs in
749 int max_uniform_components
= 32 * 8;
750 if (this->uniforms
* 4 <= max_uniform_components
)
753 /* Make some sort of choice as to which uniforms get sent to pull
754 * constants. We could potentially do something clever here like
755 * look for the most infrequently used uniform vec4s, but leave
758 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
759 pull_constant_loc
[i
/ 4] = -1;
761 if (i
>= max_uniform_components
) {
762 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
764 /* Try to find an existing copy of this uniform in the pull
765 * constants if it was part of an array access already.
767 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
770 for (matches
= 0; matches
< 4; matches
++) {
771 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
776 pull_constant_loc
[i
/ 4] = j
/ 4;
781 if (pull_constant_loc
[i
/ 4] == -1) {
782 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
783 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
785 for (int j
= 0; j
< 4; j
++) {
786 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
793 /* Now actually rewrite usage of the things we've moved to pull
796 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
797 for (int i
= 0 ; i
< 3; i
++) {
798 if (inst
->src
[i
].file
!= UNIFORM
||
799 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
802 int uniform
= inst
->src
[i
].reg
;
804 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
806 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
807 pull_constant_loc
[uniform
]);
809 inst
->src
[i
].file
= temp
.file
;
810 inst
->src
[i
].reg
= temp
.reg
;
811 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
812 inst
->src
[i
].reladdr
= NULL
;
816 /* Repack push constants to remove the now-unused ones. */
817 pack_uniform_registers();
820 /* Conditions for which we want to avoid setting the dependency control bits */
822 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
824 #define IS_DWORD(reg) \
825 (reg.type == BRW_REGISTER_TYPE_UD || \
826 reg.type == BRW_REGISTER_TYPE_D)
828 /* "When source or destination datatype is 64b or operation is integer DWord
829 * multiply, DepCtrl must not be used."
830 * May apply to future SoCs as well.
832 if (brw
->is_cherryview
) {
833 if (inst
->opcode
== BRW_OPCODE_MUL
&&
834 IS_DWORD(inst
->src
[0]) &&
835 IS_DWORD(inst
->src
[1]))
841 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
847 * In the presence of send messages, totally interrupt dependency
848 * control. They're long enough that the chance of dependency
849 * control around them just doesn't matter.
852 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
853 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
854 * completes the scoreboard clear must have a non-zero execution mask. This
855 * means, if any kind of predication can change the execution mask or channel
856 * enable of the last instruction, the optimization must be avoided. This is
857 * to avoid instructions being shot down the pipeline when no writes are
861 * Dependency control does not work well over math instructions.
862 * NB: Discovered empirically
864 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
868 * Sets the dependency control fields on instructions after register
869 * allocation and before the generator is run.
871 * When you have a sequence of instructions like:
873 * DP4 temp.x vertex uniform[0]
874 * DP4 temp.y vertex uniform[0]
875 * DP4 temp.z vertex uniform[0]
876 * DP4 temp.w vertex uniform[0]
878 * The hardware doesn't know that it can actually run the later instructions
879 * while the previous ones are in flight, producing stalls. However, we have
880 * manual fields we can set in the instructions that let it do so.
883 vec4_visitor::opt_set_dependency_control()
885 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
886 uint8_t grf_channels_written
[BRW_MAX_GRF
];
887 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
888 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
890 assert(prog_data
->total_grf
||
891 !"Must be called after register allocation");
893 foreach_block (block
, cfg
) {
894 memset(last_grf_write
, 0, sizeof(last_grf_write
));
895 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
897 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
898 /* If we read from a register that we were doing dependency control
899 * on, don't do dependency control across the read.
901 for (int i
= 0; i
< 3; i
++) {
902 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
903 if (inst
->src
[i
].file
== GRF
) {
904 last_grf_write
[reg
] = NULL
;
905 } else if (inst
->src
[i
].file
== HW_REG
) {
906 memset(last_grf_write
, 0, sizeof(last_grf_write
));
909 assert(inst
->src
[i
].file
!= MRF
);
912 if (is_dep_ctrl_unsafe(inst
)) {
913 memset(last_grf_write
, 0, sizeof(last_grf_write
));
914 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
918 /* Now, see if we can do dependency control for this instruction
919 * against a previous one writing to its destination.
921 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
922 if (inst
->dst
.file
== GRF
) {
923 if (last_grf_write
[reg
] &&
924 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
925 last_grf_write
[reg
]->no_dd_clear
= true;
926 inst
->no_dd_check
= true;
928 grf_channels_written
[reg
] = 0;
931 last_grf_write
[reg
] = inst
;
932 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
933 } else if (inst
->dst
.file
== MRF
) {
934 if (last_mrf_write
[reg
] &&
935 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
936 last_mrf_write
[reg
]->no_dd_clear
= true;
937 inst
->no_dd_check
= true;
939 mrf_channels_written
[reg
] = 0;
942 last_mrf_write
[reg
] = inst
;
943 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
944 } else if (inst
->dst
.reg
== HW_REG
) {
945 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
946 memset(last_grf_write
, 0, sizeof(last_grf_write
));
947 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
948 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
955 vec4_instruction::can_reswizzle(int dst_writemask
,
959 /* If this instruction sets anything not referenced by swizzle, then we'd
960 * totally break it when we reswizzle.
962 if (dst
.writemask
& ~swizzle_mask
)
972 * For any channels in the swizzle's source that were populated by this
973 * instruction, rewrite the instruction to put the appropriate result directly
976 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
979 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
981 /* Destination write mask doesn't correspond to source swizzle for the dot
982 * product and pack_bytes instructions.
984 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
985 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
986 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
987 for (int i
= 0; i
< 3; i
++) {
988 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
991 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
995 /* Apply the specified swizzle and writemask to the original mask of
996 * written components.
998 dst
.writemask
= dst_writemask
&
999 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1003 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1004 * just written and then MOVed into another reg and making the original write
1005 * of the GRF write directly to the final destination instead.
1008 vec4_visitor::opt_register_coalesce()
1010 bool progress
= false;
1013 calculate_live_intervals();
1015 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1019 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1020 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1022 inst
->src
[0].file
!= GRF
||
1023 inst
->dst
.type
!= inst
->src
[0].type
||
1024 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1027 bool to_mrf
= (inst
->dst
.file
== MRF
);
1029 /* Can't coalesce this GRF if someone else was going to
1032 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1033 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1034 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1035 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1038 /* We need to check interference with the final destination between this
1039 * instruction and the earliest instruction involved in writing the GRF
1040 * we're eliminating. To do that, keep track of which of our source
1041 * channels we've seen initialized.
1043 bool chans_needed
[4] = {false, false, false, false};
1044 int chans_remaining
= 0;
1045 int swizzle_mask
= 0;
1046 for (int i
= 0; i
< 4; i
++) {
1047 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1049 if (!(inst
->dst
.writemask
& (1 << i
)))
1052 swizzle_mask
|= (1 << chan
);
1054 if (!chans_needed
[chan
]) {
1055 chans_needed
[chan
] = true;
1060 /* Now walk up the instruction stream trying to see if we can rewrite
1061 * everything writing to the temporary to write into the destination
1064 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1065 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1067 _scan_inst
= scan_inst
;
1069 if (scan_inst
->dst
.file
== GRF
&&
1070 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1071 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1072 /* Found something writing to the reg we want to coalesce away. */
1074 /* SEND instructions can't have MRF as a destination. */
1075 if (scan_inst
->mlen
)
1078 if (brw
->gen
== 6) {
1079 /* gen6 math instructions must have the destination be
1080 * GRF, so no compute-to-MRF for them.
1082 if (scan_inst
->is_math()) {
1088 /* If we can't handle the swizzle, bail. */
1089 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1090 inst
->src
[0].swizzle
,
1095 /* Mark which channels we found unconditional writes for. */
1096 if (!scan_inst
->predicate
) {
1097 for (int i
= 0; i
< 4; i
++) {
1098 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1100 chans_needed
[i
] = false;
1106 if (chans_remaining
== 0)
1110 /* You can't read from an MRF, so if someone else reads our MRF's
1111 * source GRF that we wanted to rewrite, that stops us. If it's a
1112 * GRF we're trying to coalesce to, we don't actually handle
1113 * rewriting sources so bail in that case as well.
1115 bool interfered
= false;
1116 for (int i
= 0; i
< 3; i
++) {
1117 if (scan_inst
->src
[i
].file
== GRF
&&
1118 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1119 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1126 /* If somebody else writes our destination here, we can't coalesce
1129 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1130 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1134 /* Check for reads of the register we're trying to coalesce into. We
1135 * can't go rewriting instructions above that to put some other value
1136 * in the register instead.
1138 if (to_mrf
&& scan_inst
->mlen
> 0) {
1139 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1140 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1144 for (int i
= 0; i
< 3; i
++) {
1145 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1146 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1147 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1156 if (chans_remaining
== 0) {
1157 /* If we've made it here, we have an MOV we want to coalesce out, and
1158 * a scan_inst pointing to the earliest instruction involved in
1159 * computing the value. Now go rewrite the instruction stream
1162 vec4_instruction
*scan_inst
= _scan_inst
;
1163 while (scan_inst
!= inst
) {
1164 if (scan_inst
->dst
.file
== GRF
&&
1165 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1166 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1167 scan_inst
->reswizzle(inst
->dst
.writemask
,
1168 inst
->src
[0].swizzle
);
1169 scan_inst
->dst
.file
= inst
->dst
.file
;
1170 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1171 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1172 scan_inst
->saturate
|= inst
->saturate
;
1174 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1176 inst
->remove(block
);
1182 invalidate_live_intervals();
1188 * Splits virtual GRFs requesting more than one contiguous physical register.
1190 * We initially create large virtual GRFs for temporary structures, arrays,
1191 * and matrices, so that the dereference visitor functions can add reg_offsets
1192 * to work their way down to the actual member being accessed. But when it
1193 * comes to optimization, we'd like to treat each register as individual
1194 * storage if possible.
1196 * So far, the only thing that might prevent splitting is a send message from
1200 vec4_visitor::split_virtual_grfs()
1202 int num_vars
= this->alloc
.count
;
1203 int new_virtual_grf
[num_vars
];
1204 bool split_grf
[num_vars
];
1206 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1208 /* Try to split anything > 0 sized. */
1209 for (int i
= 0; i
< num_vars
; i
++) {
1210 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1213 /* Check that the instructions are compatible with the registers we're trying
1216 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1217 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1220 if (inst
->is_send_from_grf()) {
1221 for (int i
= 0; i
< 3; i
++) {
1222 if (inst
->src
[i
].file
== GRF
) {
1223 split_grf
[inst
->src
[i
].reg
] = false;
1229 /* Allocate new space for split regs. Note that the virtual
1230 * numbers will be contiguous.
1232 for (int i
= 0; i
< num_vars
; i
++) {
1236 new_virtual_grf
[i
] = alloc
.allocate(1);
1237 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1238 unsigned reg
= alloc
.allocate(1);
1239 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1242 this->alloc
.sizes
[i
] = 1;
1245 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1246 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1247 inst
->dst
.reg_offset
!= 0) {
1248 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1249 inst
->dst
.reg_offset
- 1);
1250 inst
->dst
.reg_offset
= 0;
1252 for (int i
= 0; i
< 3; i
++) {
1253 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1254 inst
->src
[i
].reg_offset
!= 0) {
1255 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1256 inst
->src
[i
].reg_offset
- 1);
1257 inst
->src
[i
].reg_offset
= 0;
1261 invalidate_live_intervals();
1265 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1267 dump_instruction(be_inst
, stderr
);
1271 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1273 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1275 if (inst
->predicate
) {
1276 fprintf(file
, "(%cf0.%d) ",
1277 inst
->predicate_inverse
? '-' : '+',
1281 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1283 fprintf(file
, ".sat");
1284 if (inst
->conditional_mod
) {
1285 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1286 if (!inst
->predicate
&&
1287 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1288 inst
->opcode
!= BRW_OPCODE_IF
&&
1289 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1290 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1295 switch (inst
->dst
.file
) {
1297 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1300 fprintf(file
, "m%d", inst
->dst
.reg
);
1303 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1304 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1306 fprintf(file
, "null");
1308 case BRW_ARF_ADDRESS
:
1309 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1311 case BRW_ARF_ACCUMULATOR
:
1312 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1315 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1316 inst
->dst
.fixed_hw_reg
.subnr
);
1319 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1320 inst
->dst
.fixed_hw_reg
.subnr
);
1324 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1326 if (inst
->dst
.fixed_hw_reg
.subnr
)
1327 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1330 fprintf(file
, "(null)");
1333 fprintf(file
, "???");
1336 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1338 if (inst
->dst
.writemask
& 1)
1340 if (inst
->dst
.writemask
& 2)
1342 if (inst
->dst
.writemask
& 4)
1344 if (inst
->dst
.writemask
& 8)
1347 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1349 if (inst
->src
[0].file
!= BAD_FILE
)
1350 fprintf(file
, ", ");
1352 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1353 if (inst
->src
[i
].negate
)
1355 if (inst
->src
[i
].abs
)
1357 switch (inst
->src
[i
].file
) {
1359 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1362 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1365 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1368 switch (inst
->src
[i
].type
) {
1369 case BRW_REGISTER_TYPE_F
:
1370 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1372 case BRW_REGISTER_TYPE_D
:
1373 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1375 case BRW_REGISTER_TYPE_UD
:
1376 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1378 case BRW_REGISTER_TYPE_VF
:
1379 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1380 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1381 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1382 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1383 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1386 fprintf(file
, "???");
1391 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1393 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1395 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1396 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1398 fprintf(file
, "null");
1400 case BRW_ARF_ADDRESS
:
1401 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1403 case BRW_ARF_ACCUMULATOR
:
1404 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1407 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1408 inst
->src
[i
].fixed_hw_reg
.subnr
);
1411 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1412 inst
->src
[i
].fixed_hw_reg
.subnr
);
1416 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1418 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1419 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1420 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1424 fprintf(file
, "(null)");
1427 fprintf(file
, "???");
1431 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1432 if (inst
->src
[i
].reg_offset
!= 0 &&
1433 inst
->src
[i
].file
== GRF
&&
1434 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1435 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1437 if (inst
->src
[i
].file
!= IMM
) {
1438 static const char *chans
[4] = {"x", "y", "z", "w"};
1440 for (int c
= 0; c
< 4; c
++) {
1441 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1445 if (inst
->src
[i
].abs
)
1448 if (inst
->src
[i
].file
!= IMM
) {
1449 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1452 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1453 fprintf(file
, ", ");
1456 fprintf(file
, "\n");
1460 static inline struct brw_reg
1461 attribute_to_hw_reg(int attr
, bool interleaved
)
1464 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1466 return brw_vec8_grf(attr
, 0);
1471 * Replace each register of type ATTR in this->instructions with a reference
1472 * to a fixed HW register.
1474 * If interleaved is true, then each attribute takes up half a register, with
1475 * register N containing attribute 2*N in its first half and attribute 2*N+1
1476 * in its second half (this corresponds to the payload setup used by geometry
1477 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1478 * false, then each attribute takes up a whole register, with register N
1479 * containing attribute N (this corresponds to the payload setup used by
1480 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1483 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1486 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1487 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1488 if (inst
->dst
.file
== ATTR
) {
1489 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1491 /* All attributes used in the shader need to have been assigned a
1492 * hardware register by the caller
1496 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1497 reg
.type
= inst
->dst
.type
;
1498 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1500 inst
->dst
.file
= HW_REG
;
1501 inst
->dst
.fixed_hw_reg
= reg
;
1504 for (int i
= 0; i
< 3; i
++) {
1505 if (inst
->src
[i
].file
!= ATTR
)
1508 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1510 /* All attributes used in the shader need to have been assigned a
1511 * hardware register by the caller
1515 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1516 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1517 reg
.type
= inst
->src
[i
].type
;
1518 if (inst
->src
[i
].abs
)
1520 if (inst
->src
[i
].negate
)
1523 inst
->src
[i
].file
= HW_REG
;
1524 inst
->src
[i
].fixed_hw_reg
= reg
;
1530 vec4_vs_visitor::setup_attributes(int payload_reg
)
1533 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1534 memset(attribute_map
, 0, sizeof(attribute_map
));
1537 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1538 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1539 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1544 /* VertexID is stored by the VF as the last vertex element, but we
1545 * don't represent it with a flag in inputs_read, so we call it
1548 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1549 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1553 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1555 /* The BSpec says we always have to read at least one thing from
1556 * the VF, and it appears that the hardware wedges otherwise.
1558 if (nr_attributes
== 0)
1561 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1563 unsigned vue_entries
=
1564 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1567 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1569 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1571 return payload_reg
+ nr_attributes
;
1575 vec4_visitor::setup_uniforms(int reg
)
1577 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1579 /* The pre-gen6 VS requires that some push constants get loaded no
1580 * matter what, or the GPU would hang.
1582 if (brw
->gen
< 6 && this->uniforms
== 0) {
1583 assert(this->uniforms
< this->uniform_array_size
);
1584 this->uniform_vector_size
[this->uniforms
] = 1;
1586 stage_prog_data
->param
=
1587 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1588 for (unsigned int i
= 0; i
< 4; i
++) {
1589 unsigned int slot
= this->uniforms
* 4 + i
;
1590 static gl_constant_value zero
= { 0.0 };
1591 stage_prog_data
->param
[slot
] = &zero
;
1597 reg
+= ALIGN(uniforms
, 2) / 2;
1600 stage_prog_data
->nr_params
= this->uniforms
* 4;
1602 prog_data
->base
.curb_read_length
=
1603 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1609 vec4_vs_visitor::setup_payload(void)
1613 /* The payload always contains important data in g0, which contains
1614 * the URB handles that are passed on to the URB write at the end
1615 * of the thread. So, we always start push constants at g1.
1619 reg
= setup_uniforms(reg
);
1621 reg
= setup_attributes(reg
);
1623 this->first_non_payload_grf
= reg
;
1627 vec4_visitor::assign_binding_table_offsets()
1629 assign_common_binding_table_offsets(0);
1633 vec4_visitor::get_timestamp()
1635 assert(brw
->gen
>= 7);
1637 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1642 BRW_REGISTER_TYPE_UD
,
1643 BRW_VERTICAL_STRIDE_0
,
1645 BRW_HORIZONTAL_STRIDE_4
,
1649 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1651 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1652 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1653 * even if it's not enabled in the dispatch.
1655 mov
->force_writemask_all
= true;
1657 return src_reg(dst
);
1661 vec4_visitor::emit_shader_time_begin()
1663 current_annotation
= "shader time start";
1664 shader_start_time
= get_timestamp();
1668 vec4_visitor::emit_shader_time_end()
1670 current_annotation
= "shader time end";
1671 src_reg shader_end_time
= get_timestamp();
1674 /* Check that there weren't any timestamp reset events (assuming these
1675 * were the only two timestamp reads that happened).
1677 src_reg reset_end
= shader_end_time
;
1678 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1679 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1680 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1682 emit(IF(BRW_PREDICATE_NORMAL
));
1684 /* Take the current timestamp and get the delta. */
1685 shader_start_time
.negate
= true;
1686 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1687 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1689 /* If there were no instructions between the two timestamp gets, the diff
1690 * is 2 cycles. Remove that overhead, so I can forget about that when
1691 * trying to determine the time taken for single instructions.
1693 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1695 emit_shader_time_write(st_base
, src_reg(diff
));
1696 emit_shader_time_write(st_written
, src_reg(1u));
1697 emit(BRW_OPCODE_ELSE
);
1698 emit_shader_time_write(st_reset
, src_reg(1u));
1699 emit(BRW_OPCODE_ENDIF
);
1703 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1706 int shader_time_index
=
1707 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1710 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1712 dst_reg offset
= dst
;
1716 offset
.type
= BRW_REGISTER_TYPE_UD
;
1717 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1719 time
.type
= BRW_REGISTER_TYPE_UD
;
1720 emit(MOV(time
, src_reg(value
)));
1722 vec4_instruction
*inst
=
1723 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1730 sanity_param_count
= prog
->Parameters
->NumParameters
;
1732 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1733 emit_shader_time_begin();
1735 assign_binding_table_offsets();
1739 /* Generate VS IR for main(). (the visitor only descends into
1740 * functions called "main").
1743 visit_instructions(shader
->base
.ir
);
1745 emit_program_code();
1749 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1750 setup_uniform_clipplane_values();
1756 /* Before any optimization, push array accesses out to scratch
1757 * space where we need them to be. This pass may allocate new
1758 * virtual GRFs, so we want to do it early. It also makes sure
1759 * that we have reladdr computations available for CSE, since we'll
1760 * often do repeated subexpressions for those.
1763 move_grf_array_access_to_scratch();
1764 move_uniform_array_access_to_pull_constants();
1766 /* The ARB_vertex_program frontend emits pull constant loads directly
1767 * rather than using reladdr, so we don't need to walk through all the
1768 * instructions looking for things to move. There isn't anything.
1770 * We do still need to split things to vec4 size.
1772 split_uniform_registers();
1774 pack_uniform_registers();
1775 move_push_constants_to_pull_constants();
1776 split_virtual_grfs();
1778 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1780 #define OPT(pass, args...) ({ \
1782 bool this_progress = pass(args); \
1784 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1785 char filename[64]; \
1786 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1787 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1789 backend_visitor::dump_instructions(filename); \
1792 progress = progress || this_progress; \
1797 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1799 snprintf(filename
, 64, "%s-%04d-00-start",
1800 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1802 backend_visitor::dump_instructions(filename
);
1813 OPT(opt_reduce_swizzle
);
1814 OPT(dead_code_eliminate
);
1815 OPT(dead_control_flow_eliminate
, this);
1816 OPT(opt_copy_propagation
);
1819 OPT(opt_register_coalesce
);
1824 if (OPT(opt_vector_float
)) {
1826 OPT(opt_copy_propagation
, false);
1827 OPT(opt_copy_propagation
, true);
1828 OPT(dead_code_eliminate
);
1837 /* Debug of register spilling: Go spill everything. */
1838 const int grf_count
= alloc
.count
;
1839 float spill_costs
[alloc
.count
];
1840 bool no_spill
[alloc
.count
];
1841 evaluate_spill_costs(spill_costs
, no_spill
);
1842 for (int i
= 0; i
< grf_count
; i
++) {
1849 while (!reg_allocate()) {
1854 opt_schedule_instructions();
1856 opt_set_dependency_control();
1858 /* If any state parameters were appended, then ParameterValues could have
1859 * been realloced, in which case the driver uniform storage set up by
1860 * _mesa_associate_uniform_storage() would point to freed memory. Make
1861 * sure that didn't happen.
1863 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1868 } /* namespace brw */
1873 * Compile a vertex shader.
1875 * Returns the final assembly and the program's size.
1878 brw_vs_emit(struct brw_context
*brw
,
1879 struct gl_shader_program
*prog
,
1880 struct brw_vs_compile
*c
,
1881 struct brw_vs_prog_data
*prog_data
,
1883 unsigned *final_assembly_size
)
1885 bool start_busy
= false;
1886 double start_time
= 0;
1887 const unsigned *assembly
= NULL
;
1889 if (unlikely(brw
->perf_debug
)) {
1890 start_busy
= (brw
->batch
.last_bo
&&
1891 drm_intel_bo_busy(brw
->batch
.last_bo
));
1892 start_time
= get_time();
1895 struct brw_shader
*shader
= NULL
;
1897 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1899 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1900 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1902 if (prog
&& brw
->gen
>= 8 && brw
->scalar_vs
) {
1903 fs_visitor
v(brw
, mem_ctx
, &c
->key
, prog_data
, prog
, &c
->vp
->program
, 8);
1906 prog
->LinkStatus
= false;
1907 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1910 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1916 fs_generator
g(brw
, mem_ctx
, (void *) &c
->key
, &prog_data
->base
.base
,
1917 &c
->vp
->program
.Base
, v
.promoted_constants
,
1918 v
.runtime_check_aads_emit
, "VS");
1919 if (INTEL_DEBUG
& DEBUG_VS
) {
1920 char *name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1921 prog
->Label
? prog
->Label
: "unnamed",
1923 g
.enable_debug(name
);
1925 g
.generate_code(v
.cfg
, 8);
1926 assembly
= g
.get_assembly(final_assembly_size
);
1929 prog_data
->base
.simd8
= true;
1930 c
->base
.last_scratch
= v
.last_scratch
;
1934 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1937 prog
->LinkStatus
= false;
1938 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1941 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1947 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1948 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
1949 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1952 if (unlikely(brw
->perf_debug
) && shader
) {
1953 if (shader
->compiled_once
) {
1954 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1956 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1957 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1958 (get_time() - start_time
) * 1000);
1960 shader
->compiled_once
= true;
1968 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1969 struct brw_vue_prog_key
*key
,
1970 GLuint id
, struct gl_program
*prog
)
1972 struct brw_context
*brw
= brw_context(ctx
);
1973 key
->program_string_id
= id
;
1975 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
1976 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1977 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1978 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
1979 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1980 key
->tex
.swizzles
[i
] =
1981 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1983 /* Color sampler: assume no swizzling. */
1984 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;