2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
30 #define MAX_INSTRUCTION (1 << 30)
35 vec4_instruction::is_math()
37 return (opcode
== SHADER_OPCODE_RCP
||
38 opcode
== SHADER_OPCODE_RSQ
||
39 opcode
== SHADER_OPCODE_SQRT
||
40 opcode
== SHADER_OPCODE_EXP2
||
41 opcode
== SHADER_OPCODE_LOG2
||
42 opcode
== SHADER_OPCODE_SIN
||
43 opcode
== SHADER_OPCODE_COS
||
44 opcode
== SHADER_OPCODE_POW
);
47 * Returns how many MRFs an opcode will write over.
49 * Note that this is not the 0 or 1 implied writes in an actual gen
50 * instruction -- the generate_* functions generate additional MOVs
54 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
59 switch (inst
->opcode
) {
60 case SHADER_OPCODE_RCP
:
61 case SHADER_OPCODE_RSQ
:
62 case SHADER_OPCODE_SQRT
:
63 case SHADER_OPCODE_EXP2
:
64 case SHADER_OPCODE_LOG2
:
65 case SHADER_OPCODE_SIN
:
66 case SHADER_OPCODE_COS
:
68 case SHADER_OPCODE_POW
:
70 case VS_OPCODE_URB_WRITE
:
72 case VS_OPCODE_PULL_CONSTANT_LOAD
:
74 case VS_OPCODE_SCRATCH_READ
:
76 case VS_OPCODE_SCRATCH_WRITE
:
79 assert(!"not reached");
85 src_reg::equals(src_reg
*r
)
87 return (file
== r
->file
&&
89 reg_offset
== r
->reg_offset
&&
91 negate
== r
->negate
&&
93 swizzle
== r
->swizzle
&&
94 !reladdr
&& !r
->reladdr
&&
95 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
96 sizeof(fixed_hw_reg
)) == 0 &&
101 vec4_visitor::calculate_live_intervals()
103 int *def
= ralloc_array(mem_ctx
, int, virtual_grf_count
);
104 int *use
= ralloc_array(mem_ctx
, int, virtual_grf_count
);
108 if (this->live_intervals_valid
)
111 for (int i
= 0; i
< virtual_grf_count
; i
++) {
112 def
[i
] = MAX_INSTRUCTION
;
117 foreach_list(node
, &this->instructions
) {
118 vec4_instruction
*inst
= (vec4_instruction
*)node
;
120 if (inst
->opcode
== BRW_OPCODE_DO
) {
121 if (loop_depth
++ == 0)
123 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
126 if (loop_depth
== 0) {
127 /* Patches up the use of vars marked for being live across
130 for (int i
= 0; i
< virtual_grf_count
; i
++) {
131 if (use
[i
] == loop_start
) {
137 for (unsigned int i
= 0; i
< 3; i
++) {
138 if (inst
->src
[i
].file
== GRF
) {
139 int reg
= inst
->src
[i
].reg
;
144 def
[reg
] = MIN2(loop_start
, def
[reg
]);
145 use
[reg
] = loop_start
;
147 /* Nobody else is going to go smash our start to
148 * later in the loop now, because def[reg] now
149 * points before the bb header.
154 if (inst
->dst
.file
== GRF
) {
155 int reg
= inst
->dst
.reg
;
158 def
[reg
] = MIN2(def
[reg
], ip
);
160 def
[reg
] = MIN2(def
[reg
], loop_start
);
168 ralloc_free(this->virtual_grf_def
);
169 ralloc_free(this->virtual_grf_use
);
170 this->virtual_grf_def
= def
;
171 this->virtual_grf_use
= use
;
173 this->live_intervals_valid
= true;
177 vec4_visitor::virtual_grf_interferes(int a
, int b
)
179 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
180 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
182 /* We can't handle dead register writes here, without iterating
183 * over the whole instruction stream to find every single dead
184 * write to that register to compare to the live interval of the
185 * other register. Just assert that dead_code_eliminate() has been
188 assert((this->virtual_grf_use
[a
] != -1 ||
189 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
190 (this->virtual_grf_use
[b
] != -1 ||
191 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
197 * Must be called after calculate_live_intervales() to remove unused
198 * writes to registers -- register allocation will fail otherwise
199 * because something deffed but not used won't be considered to
200 * interfere with other regs.
203 vec4_visitor::dead_code_eliminate()
205 bool progress
= false;
208 calculate_live_intervals();
210 foreach_list_safe(node
, &this->instructions
) {
211 vec4_instruction
*inst
= (vec4_instruction
*)node
;
213 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
222 live_intervals_valid
= false;
228 vec4_visitor::split_uniform_registers()
230 /* Prior to this, uniforms have been in an array sized according to
231 * the number of vector uniforms present, sparsely filled (so an
232 * aggregate results in reg indices being skipped over). Now we're
233 * going to cut those aggregates up so each .reg index is one
234 * vector. The goal is to make elimination of unused uniform
235 * components easier later.
237 foreach_list(node
, &this->instructions
) {
238 vec4_instruction
*inst
= (vec4_instruction
*)node
;
240 for (int i
= 0 ; i
< 3; i
++) {
241 if (inst
->src
[i
].file
!= UNIFORM
)
244 assert(!inst
->src
[i
].reladdr
);
246 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
247 inst
->src
[i
].reg_offset
= 0;
251 /* Update that everything is now vector-sized. */
252 for (int i
= 0; i
< this->uniforms
; i
++) {
253 this->uniform_size
[i
] = 1;
258 vec4_visitor::pack_uniform_registers()
260 bool uniform_used
[this->uniforms
];
261 int new_loc
[this->uniforms
];
262 int new_chan
[this->uniforms
];
264 memset(uniform_used
, 0, sizeof(uniform_used
));
265 memset(new_loc
, 0, sizeof(new_loc
));
266 memset(new_chan
, 0, sizeof(new_chan
));
268 /* Find which uniform vectors are actually used by the program. We
269 * expect unused vector elements when we've moved array access out
270 * to pull constants, and from some GLSL code generators like wine.
272 foreach_list(node
, &this->instructions
) {
273 vec4_instruction
*inst
= (vec4_instruction
*)node
;
275 for (int i
= 0 ; i
< 3; i
++) {
276 if (inst
->src
[i
].file
!= UNIFORM
)
279 uniform_used
[inst
->src
[i
].reg
] = true;
283 int new_uniform_count
= 0;
285 /* Now, figure out a packing of the live uniform vectors into our
288 for (int src
= 0; src
< uniforms
; src
++) {
289 int size
= this->uniform_vector_size
[src
];
291 if (!uniform_used
[src
]) {
292 this->uniform_vector_size
[src
] = 0;
297 /* Find the lowest place we can slot this uniform in. */
298 for (dst
= 0; dst
< src
; dst
++) {
299 if (this->uniform_vector_size
[dst
] + size
<= 4)
308 new_chan
[src
] = this->uniform_vector_size
[dst
];
310 /* Move the references to the data */
311 for (int j
= 0; j
< size
; j
++) {
312 c
->prog_data
.param
[dst
* 4 + new_chan
[src
] + j
] =
313 c
->prog_data
.param
[src
* 4 + j
];
316 this->uniform_vector_size
[dst
] += size
;
317 this->uniform_vector_size
[src
] = 0;
320 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
323 this->uniforms
= new_uniform_count
;
325 /* Now, update the instructions for our repacked uniforms. */
326 foreach_list(node
, &this->instructions
) {
327 vec4_instruction
*inst
= (vec4_instruction
*)node
;
329 for (int i
= 0 ; i
< 3; i
++) {
330 int src
= inst
->src
[i
].reg
;
332 if (inst
->src
[i
].file
!= UNIFORM
)
335 inst
->src
[i
].reg
= new_loc
[src
];
337 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
338 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
339 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
340 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
341 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
347 src_reg::is_zero() const
352 if (type
== BRW_REGISTER_TYPE_F
) {
360 src_reg::is_one() const
365 if (type
== BRW_REGISTER_TYPE_F
) {
373 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
375 * While GLSL IR also performs this optimization, we end up with it in
376 * our instruction stream for a couple of reasons. One is that we
377 * sometimes generate silly instructions, for example in array access
378 * where we'll generate "ADD offset, index, base" even if base is 0.
379 * The other is that GLSL IR's constant propagation doesn't track the
380 * components of aggregates, so some VS patterns (initialize matrix to
381 * 0, accumulate in vertex blending factors) end up breaking down to
382 * instructions involving 0.
385 vec4_visitor::opt_algebraic()
387 bool progress
= false;
389 foreach_list(node
, &this->instructions
) {
390 vec4_instruction
*inst
= (vec4_instruction
*)node
;
392 switch (inst
->opcode
) {
394 if (inst
->src
[1].is_zero()) {
395 inst
->opcode
= BRW_OPCODE_MOV
;
396 inst
->src
[1] = src_reg();
402 if (inst
->src
[1].is_zero()) {
403 inst
->opcode
= BRW_OPCODE_MOV
;
404 switch (inst
->src
[0].type
) {
405 case BRW_REGISTER_TYPE_F
:
406 inst
->src
[0] = src_reg(0.0f
);
408 case BRW_REGISTER_TYPE_D
:
409 inst
->src
[0] = src_reg(0);
411 case BRW_REGISTER_TYPE_UD
:
412 inst
->src
[0] = src_reg(0u);
415 assert(!"not reached");
416 inst
->src
[0] = src_reg(0.0f
);
419 inst
->src
[1] = src_reg();
421 } else if (inst
->src
[1].is_one()) {
422 inst
->opcode
= BRW_OPCODE_MOV
;
423 inst
->src
[1] = src_reg();
433 this->live_intervals_valid
= false;
439 * Only a limited number of hardware registers may be used for push
440 * constants, so this turns access to the overflowed constants into
444 vec4_visitor::move_push_constants_to_pull_constants()
446 int pull_constant_loc
[this->uniforms
];
448 /* Only allow 32 registers (256 uniform components) as push constants,
449 * which is the limit on gen6.
451 int max_uniform_components
= 32 * 8;
452 if (this->uniforms
* 4 <= max_uniform_components
)
455 /* Make some sort of choice as to which uniforms get sent to pull
456 * constants. We could potentially do something clever here like
457 * look for the most infrequently used uniform vec4s, but leave
460 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
461 pull_constant_loc
[i
/ 4] = -1;
463 if (i
>= max_uniform_components
) {
464 const float **values
= &prog_data
->param
[i
];
466 /* Try to find an existing copy of this uniform in the pull
467 * constants if it was part of an array access already.
469 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
472 for (matches
= 0; matches
< 4; matches
++) {
473 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
478 pull_constant_loc
[i
/ 4] = j
/ 4;
483 if (pull_constant_loc
[i
/ 4] == -1) {
484 assert(prog_data
->nr_pull_params
% 4 == 0);
485 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
487 for (int j
= 0; j
< 4; j
++) {
488 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
494 /* Now actually rewrite usage of the things we've moved to pull
497 foreach_list_safe(node
, &this->instructions
) {
498 vec4_instruction
*inst
= (vec4_instruction
*)node
;
500 for (int i
= 0 ; i
< 3; i
++) {
501 if (inst
->src
[i
].file
!= UNIFORM
||
502 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
505 int uniform
= inst
->src
[i
].reg
;
507 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
509 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
510 pull_constant_loc
[uniform
]);
512 inst
->src
[i
].file
= temp
.file
;
513 inst
->src
[i
].reg
= temp
.reg
;
514 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
515 inst
->src
[i
].reladdr
= NULL
;
519 /* Repack push constants to remove the now-unused ones. */
520 pack_uniform_registers();
523 } /* namespace brw */