2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(float f
)
79 this->type
= BRW_REGISTER_TYPE_F
;
80 this->fixed_hw_reg
.dw1
.f
= f
;
83 src_reg::src_reg(uint32_t u
)
88 this->type
= BRW_REGISTER_TYPE_UD
;
89 this->fixed_hw_reg
.dw1
.ud
= u
;
92 src_reg::src_reg(int32_t i
)
97 this->type
= BRW_REGISTER_TYPE_D
;
98 this->fixed_hw_reg
.dw1
.d
= i
;
101 src_reg::src_reg(uint8_t vf
[4])
106 this->type
= BRW_REGISTER_TYPE_VF
;
107 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
110 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
115 this->type
= BRW_REGISTER_TYPE_VF
;
116 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
122 src_reg::src_reg(struct brw_reg reg
)
127 this->fixed_hw_reg
= reg
;
128 this->type
= reg
.type
;
131 src_reg::src_reg(const dst_reg
®
)
135 this->file
= reg
.file
;
137 this->reg_offset
= reg
.reg_offset
;
138 this->type
= reg
.type
;
139 this->reladdr
= reg
.reladdr
;
140 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
141 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(register_file file
, int reg
, brw_reg_type type
,
184 this->writemask
= writemask
;
187 dst_reg::dst_reg(struct brw_reg reg
)
192 this->fixed_hw_reg
= reg
;
193 this->type
= reg
.type
;
196 dst_reg::dst_reg(const src_reg
®
)
200 this->file
= reg
.file
;
202 this->reg_offset
= reg
.reg_offset
;
203 this->type
= reg
.type
;
204 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
205 this->reladdr
= reg
.reladdr
;
206 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
210 dst_reg::equals(const dst_reg
&r
) const
212 return (file
== r
.file
&&
214 reg_offset
== r
.reg_offset
&&
216 negate
== r
.negate
&&
218 writemask
== r
.writemask
&&
219 (reladdr
== r
.reladdr
||
220 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
221 ((file
!= HW_REG
&& file
!= IMM
) ||
222 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
223 sizeof(fixed_hw_reg
)) == 0));
227 vec4_instruction::is_send_from_grf()
230 case SHADER_OPCODE_SHADER_TIME_ADD
:
231 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
232 case SHADER_OPCODE_UNTYPED_ATOMIC
:
233 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
234 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
235 case SHADER_OPCODE_TYPED_ATOMIC
:
236 case SHADER_OPCODE_TYPED_SURFACE_READ
:
237 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
245 vec4_instruction::regs_read(unsigned arg
) const
247 if (src
[arg
].file
== BAD_FILE
)
251 case SHADER_OPCODE_SHADER_TIME_ADD
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 return arg
== 0 ? mlen
: 1;
260 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
261 return arg
== 1 ? mlen
: 1;
269 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
271 if (devinfo
->gen
== 6 && is_math())
274 if (is_send_from_grf())
277 if (!backend_instruction::can_do_source_mods())
284 * Returns how many MRFs an opcode will write over.
286 * Note that this is not the 0 or 1 implied writes in an actual gen
287 * instruction -- the generate_* functions generate additional MOVs
291 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
293 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
296 switch (inst
->opcode
) {
297 case SHADER_OPCODE_RCP
:
298 case SHADER_OPCODE_RSQ
:
299 case SHADER_OPCODE_SQRT
:
300 case SHADER_OPCODE_EXP2
:
301 case SHADER_OPCODE_LOG2
:
302 case SHADER_OPCODE_SIN
:
303 case SHADER_OPCODE_COS
:
305 case SHADER_OPCODE_INT_QUOTIENT
:
306 case SHADER_OPCODE_INT_REMAINDER
:
307 case SHADER_OPCODE_POW
:
309 case VS_OPCODE_URB_WRITE
:
311 case VS_OPCODE_PULL_CONSTANT_LOAD
:
313 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
315 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
317 case GS_OPCODE_URB_WRITE
:
318 case GS_OPCODE_URB_WRITE_ALLOCATE
:
319 case GS_OPCODE_THREAD_END
:
321 case GS_OPCODE_FF_SYNC
:
323 case SHADER_OPCODE_SHADER_TIME_ADD
:
325 case SHADER_OPCODE_TEX
:
326 case SHADER_OPCODE_TXL
:
327 case SHADER_OPCODE_TXD
:
328 case SHADER_OPCODE_TXF
:
329 case SHADER_OPCODE_TXF_CMS
:
330 case SHADER_OPCODE_TXF_MCS
:
331 case SHADER_OPCODE_TXS
:
332 case SHADER_OPCODE_TG4
:
333 case SHADER_OPCODE_TG4_OFFSET
:
334 case SHADER_OPCODE_SAMPLEINFO
:
335 case VS_OPCODE_GET_BUFFER_SIZE
:
336 return inst
->header_size
;
338 unreachable("not reached");
343 src_reg::equals(const src_reg
&r
) const
345 return (file
== r
.file
&&
347 reg_offset
== r
.reg_offset
&&
349 negate
== r
.negate
&&
351 swizzle
== r
.swizzle
&&
352 !reladdr
&& !r
.reladdr
&&
353 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
354 sizeof(fixed_hw_reg
)) == 0);
358 vec4_visitor::opt_vector_float()
360 bool progress
= false;
362 int last_reg
= -1, last_reg_offset
= -1;
363 enum register_file last_reg_file
= BAD_FILE
;
365 int remaining_channels
= 0;
368 vec4_instruction
*imm_inst
[4];
370 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
371 if (last_reg
!= inst
->dst
.reg
||
372 last_reg_offset
!= inst
->dst
.reg_offset
||
373 last_reg_file
!= inst
->dst
.file
) {
374 last_reg
= inst
->dst
.reg
;
375 last_reg_offset
= inst
->dst
.reg_offset
;
376 last_reg_file
= inst
->dst
.file
;
377 remaining_channels
= WRITEMASK_XYZW
;
382 if (inst
->opcode
!= BRW_OPCODE_MOV
||
383 inst
->dst
.writemask
== WRITEMASK_XYZW
||
384 inst
->src
[0].file
!= IMM
)
387 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
391 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
393 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
395 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
397 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
400 imm_inst
[inst_count
++] = inst
;
402 remaining_channels
&= ~inst
->dst
.writemask
;
403 if (remaining_channels
== 0) {
404 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
405 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
406 mov
->dst
.writemask
= WRITEMASK_XYZW
;
407 inst
->insert_after(block
, mov
);
410 for (int i
= 0; i
< inst_count
; i
++) {
411 imm_inst
[i
]->remove(block
);
418 invalidate_live_intervals();
423 /* Replaces unused channels of a swizzle with channels that are used.
425 * For instance, this pass transforms
427 * mov vgrf4.yz, vgrf5.wxzy
431 * mov vgrf4.yz, vgrf5.xxzx
433 * This eliminates false uses of some channels, letting dead code elimination
434 * remove the instructions that wrote them.
437 vec4_visitor::opt_reduce_swizzle()
439 bool progress
= false;
441 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
442 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
443 inst
->is_send_from_grf())
448 /* Determine which channels of the sources are read. */
449 switch (inst
->opcode
) {
450 case VEC4_OPCODE_PACK_BYTES
:
452 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
453 * but all four of src1.
455 swizzle
= brw_swizzle_for_size(4);
458 swizzle
= brw_swizzle_for_size(3);
461 swizzle
= brw_swizzle_for_size(2);
464 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
468 /* Update sources' swizzles. */
469 for (int i
= 0; i
< 3; i
++) {
470 if (inst
->src
[i
].file
!= GRF
&&
471 inst
->src
[i
].file
!= ATTR
&&
472 inst
->src
[i
].file
!= UNIFORM
)
475 const unsigned new_swizzle
=
476 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
477 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
478 inst
->src
[i
].swizzle
= new_swizzle
;
485 invalidate_live_intervals();
491 vec4_visitor::split_uniform_registers()
493 /* Prior to this, uniforms have been in an array sized according to
494 * the number of vector uniforms present, sparsely filled (so an
495 * aggregate results in reg indices being skipped over). Now we're
496 * going to cut those aggregates up so each .reg index is one
497 * vector. The goal is to make elimination of unused uniform
498 * components easier later.
500 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
501 for (int i
= 0 ; i
< 3; i
++) {
502 if (inst
->src
[i
].file
!= UNIFORM
)
505 assert(!inst
->src
[i
].reladdr
);
507 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
508 inst
->src
[i
].reg_offset
= 0;
512 /* Update that everything is now vector-sized. */
513 for (int i
= 0; i
< this->uniforms
; i
++) {
514 this->uniform_size
[i
] = 1;
519 vec4_visitor::pack_uniform_registers()
521 uint8_t chans_used
[this->uniforms
];
522 int new_loc
[this->uniforms
];
523 int new_chan
[this->uniforms
];
525 memset(chans_used
, 0, sizeof(chans_used
));
526 memset(new_loc
, 0, sizeof(new_loc
));
527 memset(new_chan
, 0, sizeof(new_chan
));
529 /* Find which uniform vectors are actually used by the program. We
530 * expect unused vector elements when we've moved array access out
531 * to pull constants, and from some GLSL code generators like wine.
533 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
535 switch (inst
->opcode
) {
536 case VEC4_OPCODE_PACK_BYTES
:
548 readmask
= inst
->dst
.writemask
;
552 for (int i
= 0 ; i
< 3; i
++) {
553 if (inst
->src
[i
].file
!= UNIFORM
)
556 int reg
= inst
->src
[i
].reg
;
557 for (int c
= 0; c
< 4; c
++) {
558 if (!(readmask
& (1 << c
)))
561 chans_used
[reg
] = MAX2(chans_used
[reg
],
562 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
567 int new_uniform_count
= 0;
569 /* Now, figure out a packing of the live uniform vectors into our
572 for (int src
= 0; src
< uniforms
; src
++) {
573 assert(src
< uniform_array_size
);
574 int size
= chans_used
[src
];
580 /* Find the lowest place we can slot this uniform in. */
581 for (dst
= 0; dst
< src
; dst
++) {
582 if (chans_used
[dst
] + size
<= 4)
591 new_chan
[src
] = chans_used
[dst
];
593 /* Move the references to the data */
594 for (int j
= 0; j
< size
; j
++) {
595 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
596 stage_prog_data
->param
[src
* 4 + j
];
599 chans_used
[dst
] += size
;
603 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
606 this->uniforms
= new_uniform_count
;
608 /* Now, update the instructions for our repacked uniforms. */
609 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
610 for (int i
= 0 ; i
< 3; i
++) {
611 int src
= inst
->src
[i
].reg
;
613 if (inst
->src
[i
].file
!= UNIFORM
)
616 inst
->src
[i
].reg
= new_loc
[src
];
617 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
618 new_chan
[src
], new_chan
[src
]);
624 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
626 * While GLSL IR also performs this optimization, we end up with it in
627 * our instruction stream for a couple of reasons. One is that we
628 * sometimes generate silly instructions, for example in array access
629 * where we'll generate "ADD offset, index, base" even if base is 0.
630 * The other is that GLSL IR's constant propagation doesn't track the
631 * components of aggregates, so some VS patterns (initialize matrix to
632 * 0, accumulate in vertex blending factors) end up breaking down to
633 * instructions involving 0.
636 vec4_visitor::opt_algebraic()
638 bool progress
= false;
640 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
641 switch (inst
->opcode
) {
643 if (inst
->src
[0].file
!= IMM
)
646 if (inst
->saturate
) {
647 if (inst
->dst
.type
!= inst
->src
[0].type
)
648 assert(!"unimplemented: saturate mixed types");
650 if (brw_saturate_immediate(inst
->dst
.type
,
651 &inst
->src
[0].fixed_hw_reg
)) {
652 inst
->saturate
= false;
658 case VEC4_OPCODE_UNPACK_UNIFORM
:
659 if (inst
->src
[0].file
!= UNIFORM
) {
660 inst
->opcode
= BRW_OPCODE_MOV
;
666 if (inst
->src
[1].is_zero()) {
667 inst
->opcode
= BRW_OPCODE_MOV
;
668 inst
->src
[1] = src_reg();
674 if (inst
->src
[1].is_zero()) {
675 inst
->opcode
= BRW_OPCODE_MOV
;
676 switch (inst
->src
[0].type
) {
677 case BRW_REGISTER_TYPE_F
:
678 inst
->src
[0] = src_reg(0.0f
);
680 case BRW_REGISTER_TYPE_D
:
681 inst
->src
[0] = src_reg(0);
683 case BRW_REGISTER_TYPE_UD
:
684 inst
->src
[0] = src_reg(0u);
687 unreachable("not reached");
689 inst
->src
[1] = src_reg();
691 } else if (inst
->src
[1].is_one()) {
692 inst
->opcode
= BRW_OPCODE_MOV
;
693 inst
->src
[1] = src_reg();
695 } else if (inst
->src
[1].is_negative_one()) {
696 inst
->opcode
= BRW_OPCODE_MOV
;
697 inst
->src
[0].negate
= !inst
->src
[0].negate
;
698 inst
->src
[1] = src_reg();
703 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
705 inst
->src
[0].negate
&&
706 inst
->src
[1].is_zero()) {
707 inst
->src
[0].abs
= false;
708 inst
->src
[0].negate
= false;
709 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
714 case SHADER_OPCODE_RCP
: {
715 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
716 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
717 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
718 inst
->opcode
= SHADER_OPCODE_RSQ
;
719 inst
->src
[0] = prev
->src
[0];
725 case SHADER_OPCODE_BROADCAST
:
726 if (is_uniform(inst
->src
[0]) ||
727 inst
->src
[1].is_zero()) {
728 inst
->opcode
= BRW_OPCODE_MOV
;
729 inst
->src
[1] = src_reg();
730 inst
->force_writemask_all
= true;
741 invalidate_live_intervals();
747 * Only a limited number of hardware registers may be used for push
748 * constants, so this turns access to the overflowed constants into
752 vec4_visitor::move_push_constants_to_pull_constants()
754 int pull_constant_loc
[this->uniforms
];
756 /* Only allow 32 registers (256 uniform components) as push constants,
757 * which is the limit on gen6.
759 * If changing this value, note the limitation about total_regs in
762 int max_uniform_components
= 32 * 8;
763 if (this->uniforms
* 4 <= max_uniform_components
)
766 /* Make some sort of choice as to which uniforms get sent to pull
767 * constants. We could potentially do something clever here like
768 * look for the most infrequently used uniform vec4s, but leave
771 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
772 pull_constant_loc
[i
/ 4] = -1;
774 if (i
>= max_uniform_components
) {
775 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
777 /* Try to find an existing copy of this uniform in the pull
778 * constants if it was part of an array access already.
780 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
783 for (matches
= 0; matches
< 4; matches
++) {
784 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
789 pull_constant_loc
[i
/ 4] = j
/ 4;
794 if (pull_constant_loc
[i
/ 4] == -1) {
795 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
796 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
798 for (int j
= 0; j
< 4; j
++) {
799 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
806 /* Now actually rewrite usage of the things we've moved to pull
809 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
810 for (int i
= 0 ; i
< 3; i
++) {
811 if (inst
->src
[i
].file
!= UNIFORM
||
812 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
815 int uniform
= inst
->src
[i
].reg
;
817 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
819 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
820 pull_constant_loc
[uniform
]);
822 inst
->src
[i
].file
= temp
.file
;
823 inst
->src
[i
].reg
= temp
.reg
;
824 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
825 inst
->src
[i
].reladdr
= NULL
;
829 /* Repack push constants to remove the now-unused ones. */
830 pack_uniform_registers();
833 /* Conditions for which we want to avoid setting the dependency control bits */
835 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
837 #define IS_DWORD(reg) \
838 (reg.type == BRW_REGISTER_TYPE_UD || \
839 reg.type == BRW_REGISTER_TYPE_D)
841 /* "When source or destination datatype is 64b or operation is integer DWord
842 * multiply, DepCtrl must not be used."
843 * May apply to future SoCs as well.
845 if (devinfo
->is_cherryview
) {
846 if (inst
->opcode
== BRW_OPCODE_MUL
&&
847 IS_DWORD(inst
->src
[0]) &&
848 IS_DWORD(inst
->src
[1]))
853 if (devinfo
->gen
>= 8) {
854 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
860 * In the presence of send messages, totally interrupt dependency
861 * control. They're long enough that the chance of dependency
862 * control around them just doesn't matter.
865 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
866 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
867 * completes the scoreboard clear must have a non-zero execution mask. This
868 * means, if any kind of predication can change the execution mask or channel
869 * enable of the last instruction, the optimization must be avoided. This is
870 * to avoid instructions being shot down the pipeline when no writes are
874 * Dependency control does not work well over math instructions.
875 * NB: Discovered empirically
877 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
881 * Sets the dependency control fields on instructions after register
882 * allocation and before the generator is run.
884 * When you have a sequence of instructions like:
886 * DP4 temp.x vertex uniform[0]
887 * DP4 temp.y vertex uniform[0]
888 * DP4 temp.z vertex uniform[0]
889 * DP4 temp.w vertex uniform[0]
891 * The hardware doesn't know that it can actually run the later instructions
892 * while the previous ones are in flight, producing stalls. However, we have
893 * manual fields we can set in the instructions that let it do so.
896 vec4_visitor::opt_set_dependency_control()
898 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
899 uint8_t grf_channels_written
[BRW_MAX_GRF
];
900 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
901 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
903 assert(prog_data
->total_grf
||
904 !"Must be called after register allocation");
906 foreach_block (block
, cfg
) {
907 memset(last_grf_write
, 0, sizeof(last_grf_write
));
908 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
910 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
911 /* If we read from a register that we were doing dependency control
912 * on, don't do dependency control across the read.
914 for (int i
= 0; i
< 3; i
++) {
915 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
916 if (inst
->src
[i
].file
== GRF
) {
917 last_grf_write
[reg
] = NULL
;
918 } else if (inst
->src
[i
].file
== HW_REG
) {
919 memset(last_grf_write
, 0, sizeof(last_grf_write
));
922 assert(inst
->src
[i
].file
!= MRF
);
925 if (is_dep_ctrl_unsafe(inst
)) {
926 memset(last_grf_write
, 0, sizeof(last_grf_write
));
927 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
931 /* Now, see if we can do dependency control for this instruction
932 * against a previous one writing to its destination.
934 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
935 if (inst
->dst
.file
== GRF
) {
936 if (last_grf_write
[reg
] &&
937 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
938 last_grf_write
[reg
]->no_dd_clear
= true;
939 inst
->no_dd_check
= true;
941 grf_channels_written
[reg
] = 0;
944 last_grf_write
[reg
] = inst
;
945 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
946 } else if (inst
->dst
.file
== MRF
) {
947 if (last_mrf_write
[reg
] &&
948 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
949 last_mrf_write
[reg
]->no_dd_clear
= true;
950 inst
->no_dd_check
= true;
952 mrf_channels_written
[reg
] = 0;
955 last_mrf_write
[reg
] = inst
;
956 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
957 } else if (inst
->dst
.reg
== HW_REG
) {
958 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
959 memset(last_grf_write
, 0, sizeof(last_grf_write
));
960 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
961 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
968 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
973 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
974 * or writemasking are not allowed.
976 if (devinfo
->gen
== 6 && is_math() &&
977 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
980 /* If this instruction sets anything not referenced by swizzle, then we'd
981 * totally break it when we reswizzle.
983 if (dst
.writemask
& ~swizzle_mask
)
989 /* We can't use swizzles on the accumulator and that's really the only
990 * HW_REG we would care to reswizzle so just disallow them all.
992 for (int i
= 0; i
< 3; i
++) {
993 if (src
[i
].file
== HW_REG
)
1001 * For any channels in the swizzle's source that were populated by this
1002 * instruction, rewrite the instruction to put the appropriate result directly
1003 * in those channels.
1005 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1008 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1010 /* Destination write mask doesn't correspond to source swizzle for the dot
1011 * product and pack_bytes instructions.
1013 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1014 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1015 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1016 for (int i
= 0; i
< 3; i
++) {
1017 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1020 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1024 /* Apply the specified swizzle and writemask to the original mask of
1025 * written components.
1027 dst
.writemask
= dst_writemask
&
1028 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1032 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1033 * just written and then MOVed into another reg and making the original write
1034 * of the GRF write directly to the final destination instead.
1037 vec4_visitor::opt_register_coalesce()
1039 bool progress
= false;
1042 calculate_live_intervals();
1044 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1048 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1049 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1051 inst
->src
[0].file
!= GRF
||
1052 inst
->dst
.type
!= inst
->src
[0].type
||
1053 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1056 /* Remove no-op MOVs */
1057 if (inst
->dst
.file
== inst
->src
[0].file
&&
1058 inst
->dst
.reg
== inst
->src
[0].reg
&&
1059 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1060 bool is_nop_mov
= true;
1062 for (unsigned c
= 0; c
< 4; c
++) {
1063 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1066 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1073 inst
->remove(block
);
1078 bool to_mrf
= (inst
->dst
.file
== MRF
);
1080 /* Can't coalesce this GRF if someone else was going to
1083 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1086 /* We need to check interference with the final destination between this
1087 * instruction and the earliest instruction involved in writing the GRF
1088 * we're eliminating. To do that, keep track of which of our source
1089 * channels we've seen initialized.
1091 const unsigned chans_needed
=
1092 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1093 inst
->dst
.writemask
);
1094 unsigned chans_remaining
= chans_needed
;
1096 /* Now walk up the instruction stream trying to see if we can rewrite
1097 * everything writing to the temporary to write into the destination
1100 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1101 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1103 _scan_inst
= scan_inst
;
1105 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1106 /* Found something writing to the reg we want to coalesce away. */
1108 /* SEND instructions can't have MRF as a destination. */
1109 if (scan_inst
->mlen
)
1112 if (devinfo
->gen
== 6) {
1113 /* gen6 math instructions must have the destination be
1114 * GRF, so no compute-to-MRF for them.
1116 if (scan_inst
->is_math()) {
1122 /* This doesn't handle saturation on the instruction we
1123 * want to coalesce away if the register types do not match.
1124 * But if scan_inst is a non type-converting 'mov', we can fix
1127 if (inst
->saturate
&&
1128 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1129 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1130 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1133 /* If we can't handle the swizzle, bail. */
1134 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1135 inst
->src
[0].swizzle
,
1140 /* This doesn't handle coalescing of multiple registers. */
1141 if (scan_inst
->regs_written
> 1)
1144 /* Mark which channels we found unconditional writes for. */
1145 if (!scan_inst
->predicate
)
1146 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1148 if (chans_remaining
== 0)
1152 /* You can't read from an MRF, so if someone else reads our MRF's
1153 * source GRF that we wanted to rewrite, that stops us. If it's a
1154 * GRF we're trying to coalesce to, we don't actually handle
1155 * rewriting sources so bail in that case as well.
1157 bool interfered
= false;
1158 for (int i
= 0; i
< 3; i
++) {
1159 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1160 scan_inst
->regs_read(i
)))
1166 /* If somebody else writes the same channels of our destination here,
1167 * we can't coalesce before that.
1169 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1170 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1174 /* Check for reads of the register we're trying to coalesce into. We
1175 * can't go rewriting instructions above that to put some other value
1176 * in the register instead.
1178 if (to_mrf
&& scan_inst
->mlen
> 0) {
1179 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1180 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1184 for (int i
= 0; i
< 3; i
++) {
1185 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1186 scan_inst
->regs_read(i
)))
1194 if (chans_remaining
== 0) {
1195 /* If we've made it here, we have an MOV we want to coalesce out, and
1196 * a scan_inst pointing to the earliest instruction involved in
1197 * computing the value. Now go rewrite the instruction stream
1200 vec4_instruction
*scan_inst
= _scan_inst
;
1201 while (scan_inst
!= inst
) {
1202 if (scan_inst
->dst
.file
== GRF
&&
1203 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1204 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1205 scan_inst
->reswizzle(inst
->dst
.writemask
,
1206 inst
->src
[0].swizzle
);
1207 scan_inst
->dst
.file
= inst
->dst
.file
;
1208 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1209 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1210 if (inst
->saturate
&&
1211 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1212 /* If we have reached this point, scan_inst is a non
1213 * type-converting 'mov' and we can modify its register types
1214 * to match the ones in inst. Otherwise, we could have an
1215 * incorrect saturation result.
1217 scan_inst
->dst
.type
= inst
->dst
.type
;
1218 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1220 scan_inst
->saturate
|= inst
->saturate
;
1222 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1224 inst
->remove(block
);
1230 invalidate_live_intervals();
1236 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1237 * flow. We could probably do better here with some form of divergence
1241 vec4_visitor::eliminate_find_live_channel()
1243 bool progress
= false;
1246 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1247 switch (inst
->opcode
) {
1253 case BRW_OPCODE_ENDIF
:
1254 case BRW_OPCODE_WHILE
:
1258 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1260 inst
->opcode
= BRW_OPCODE_MOV
;
1261 inst
->src
[0] = src_reg(0);
1262 inst
->force_writemask_all
= true;
1276 * Splits virtual GRFs requesting more than one contiguous physical register.
1278 * We initially create large virtual GRFs for temporary structures, arrays,
1279 * and matrices, so that the dereference visitor functions can add reg_offsets
1280 * to work their way down to the actual member being accessed. But when it
1281 * comes to optimization, we'd like to treat each register as individual
1282 * storage if possible.
1284 * So far, the only thing that might prevent splitting is a send message from
1288 vec4_visitor::split_virtual_grfs()
1290 int num_vars
= this->alloc
.count
;
1291 int new_virtual_grf
[num_vars
];
1292 bool split_grf
[num_vars
];
1294 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1296 /* Try to split anything > 0 sized. */
1297 for (int i
= 0; i
< num_vars
; i
++) {
1298 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1301 /* Check that the instructions are compatible with the registers we're trying
1304 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1305 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1306 split_grf
[inst
->dst
.reg
] = false;
1308 for (int i
= 0; i
< 3; i
++) {
1309 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1310 split_grf
[inst
->src
[i
].reg
] = false;
1314 /* Allocate new space for split regs. Note that the virtual
1315 * numbers will be contiguous.
1317 for (int i
= 0; i
< num_vars
; i
++) {
1321 new_virtual_grf
[i
] = alloc
.allocate(1);
1322 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1323 unsigned reg
= alloc
.allocate(1);
1324 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1327 this->alloc
.sizes
[i
] = 1;
1330 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1331 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1332 inst
->dst
.reg_offset
!= 0) {
1333 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1334 inst
->dst
.reg_offset
- 1);
1335 inst
->dst
.reg_offset
= 0;
1337 for (int i
= 0; i
< 3; i
++) {
1338 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1339 inst
->src
[i
].reg_offset
!= 0) {
1340 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1341 inst
->src
[i
].reg_offset
- 1);
1342 inst
->src
[i
].reg_offset
= 0;
1346 invalidate_live_intervals();
1350 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1352 dump_instruction(be_inst
, stderr
);
1356 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1358 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1360 if (inst
->predicate
) {
1361 fprintf(file
, "(%cf0.%d) ",
1362 inst
->predicate_inverse
? '-' : '+',
1366 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1368 fprintf(file
, ".sat");
1369 if (inst
->conditional_mod
) {
1370 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1371 if (!inst
->predicate
&&
1372 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1373 inst
->opcode
!= BRW_OPCODE_IF
&&
1374 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1375 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1380 switch (inst
->dst
.file
) {
1382 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1385 fprintf(file
, "m%d", inst
->dst
.reg
);
1388 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1389 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1391 fprintf(file
, "null");
1393 case BRW_ARF_ADDRESS
:
1394 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1396 case BRW_ARF_ACCUMULATOR
:
1397 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1400 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1401 inst
->dst
.fixed_hw_reg
.subnr
);
1404 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1405 inst
->dst
.fixed_hw_reg
.subnr
);
1409 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1411 if (inst
->dst
.fixed_hw_reg
.subnr
)
1412 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1415 fprintf(file
, "(null)");
1418 fprintf(file
, "???");
1421 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1423 if (inst
->dst
.writemask
& 1)
1425 if (inst
->dst
.writemask
& 2)
1427 if (inst
->dst
.writemask
& 4)
1429 if (inst
->dst
.writemask
& 8)
1432 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1434 if (inst
->src
[0].file
!= BAD_FILE
)
1435 fprintf(file
, ", ");
1437 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1438 if (inst
->src
[i
].negate
)
1440 if (inst
->src
[i
].abs
)
1442 switch (inst
->src
[i
].file
) {
1444 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1447 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1450 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1453 switch (inst
->src
[i
].type
) {
1454 case BRW_REGISTER_TYPE_F
:
1455 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1457 case BRW_REGISTER_TYPE_D
:
1458 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1460 case BRW_REGISTER_TYPE_UD
:
1461 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1463 case BRW_REGISTER_TYPE_VF
:
1464 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1465 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1466 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1467 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1468 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1471 fprintf(file
, "???");
1476 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1478 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1480 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1481 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1483 fprintf(file
, "null");
1485 case BRW_ARF_ADDRESS
:
1486 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1488 case BRW_ARF_ACCUMULATOR
:
1489 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1492 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1493 inst
->src
[i
].fixed_hw_reg
.subnr
);
1496 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1497 inst
->src
[i
].fixed_hw_reg
.subnr
);
1501 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1503 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1504 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1505 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1509 fprintf(file
, "(null)");
1512 fprintf(file
, "???");
1516 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1517 if (inst
->src
[i
].reg_offset
!= 0 &&
1518 inst
->src
[i
].file
== GRF
&&
1519 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1520 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1522 if (inst
->src
[i
].file
!= IMM
) {
1523 static const char *chans
[4] = {"x", "y", "z", "w"};
1525 for (int c
= 0; c
< 4; c
++) {
1526 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1530 if (inst
->src
[i
].abs
)
1533 if (inst
->src
[i
].file
!= IMM
) {
1534 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1537 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1538 fprintf(file
, ", ");
1541 fprintf(file
, "\n");
1545 static inline struct brw_reg
1546 attribute_to_hw_reg(int attr
, bool interleaved
)
1549 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1551 return brw_vec8_grf(attr
, 0);
1556 * Replace each register of type ATTR in this->instructions with a reference
1557 * to a fixed HW register.
1559 * If interleaved is true, then each attribute takes up half a register, with
1560 * register N containing attribute 2*N in its first half and attribute 2*N+1
1561 * in its second half (this corresponds to the payload setup used by geometry
1562 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1563 * false, then each attribute takes up a whole register, with register N
1564 * containing attribute N (this corresponds to the payload setup used by
1565 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1568 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1571 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1572 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1573 if (inst
->dst
.file
== ATTR
) {
1574 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1576 /* All attributes used in the shader need to have been assigned a
1577 * hardware register by the caller
1581 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1582 reg
.type
= inst
->dst
.type
;
1583 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1585 inst
->dst
.file
= HW_REG
;
1586 inst
->dst
.fixed_hw_reg
= reg
;
1589 for (int i
= 0; i
< 3; i
++) {
1590 if (inst
->src
[i
].file
!= ATTR
)
1593 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1595 /* All attributes used in the shader need to have been assigned a
1596 * hardware register by the caller
1600 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1601 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1602 reg
.type
= inst
->src
[i
].type
;
1603 if (inst
->src
[i
].abs
)
1605 if (inst
->src
[i
].negate
)
1608 inst
->src
[i
].file
= HW_REG
;
1609 inst
->src
[i
].fixed_hw_reg
= reg
;
1615 vec4_vs_visitor::setup_attributes(int payload_reg
)
1618 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1619 memset(attribute_map
, 0, sizeof(attribute_map
));
1622 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1623 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1624 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1629 /* VertexID is stored by the VF as the last vertex element, but we
1630 * don't represent it with a flag in inputs_read, so we call it
1633 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1634 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1638 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1640 /* The BSpec says we always have to read at least one thing from
1641 * the VF, and it appears that the hardware wedges otherwise.
1643 if (nr_attributes
== 0)
1646 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1648 unsigned vue_entries
=
1649 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1651 if (devinfo
->gen
== 6)
1652 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1654 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1656 return payload_reg
+ nr_attributes
;
1660 vec4_visitor::setup_uniforms(int reg
)
1662 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1664 /* The pre-gen6 VS requires that some push constants get loaded no
1665 * matter what, or the GPU would hang.
1667 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1668 assert(this->uniforms
< this->uniform_array_size
);
1670 stage_prog_data
->param
=
1671 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1672 for (unsigned int i
= 0; i
< 4; i
++) {
1673 unsigned int slot
= this->uniforms
* 4 + i
;
1674 static gl_constant_value zero
= { 0.0 };
1675 stage_prog_data
->param
[slot
] = &zero
;
1681 reg
+= ALIGN(uniforms
, 2) / 2;
1684 stage_prog_data
->nr_params
= this->uniforms
* 4;
1686 prog_data
->base
.curb_read_length
=
1687 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1693 vec4_vs_visitor::setup_payload(void)
1697 /* The payload always contains important data in g0, which contains
1698 * the URB handles that are passed on to the URB write at the end
1699 * of the thread. So, we always start push constants at g1.
1703 reg
= setup_uniforms(reg
);
1705 reg
= setup_attributes(reg
);
1707 this->first_non_payload_grf
= reg
;
1711 vec4_visitor::assign_binding_table_offsets()
1713 brw_assign_common_binding_table_offsets(stage
, devinfo
, shader_prog
, prog
,
1714 stage_prog_data
, 0);
1718 vec4_visitor::get_timestamp()
1720 assert(devinfo
->gen
>= 7);
1722 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1727 BRW_REGISTER_TYPE_UD
,
1728 BRW_VERTICAL_STRIDE_0
,
1730 BRW_HORIZONTAL_STRIDE_4
,
1734 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1736 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1737 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1738 * even if it's not enabled in the dispatch.
1740 mov
->force_writemask_all
= true;
1742 return src_reg(dst
);
1746 vec4_visitor::emit_shader_time_begin()
1748 current_annotation
= "shader time start";
1749 shader_start_time
= get_timestamp();
1753 vec4_visitor::emit_shader_time_end()
1755 current_annotation
= "shader time end";
1756 src_reg shader_end_time
= get_timestamp();
1759 /* Check that there weren't any timestamp reset events (assuming these
1760 * were the only two timestamp reads that happened).
1762 src_reg reset_end
= shader_end_time
;
1763 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1764 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1765 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1767 emit(IF(BRW_PREDICATE_NORMAL
));
1769 /* Take the current timestamp and get the delta. */
1770 shader_start_time
.negate
= true;
1771 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1772 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1774 /* If there were no instructions between the two timestamp gets, the diff
1775 * is 2 cycles. Remove that overhead, so I can forget about that when
1776 * trying to determine the time taken for single instructions.
1778 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1780 emit_shader_time_write(0, src_reg(diff
));
1781 emit_shader_time_write(1, src_reg(1u));
1782 emit(BRW_OPCODE_ELSE
);
1783 emit_shader_time_write(2, src_reg(1u));
1784 emit(BRW_OPCODE_ENDIF
);
1788 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1791 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1793 dst_reg offset
= dst
;
1797 offset
.type
= BRW_REGISTER_TYPE_UD
;
1798 int index
= shader_time_index
* 3 + shader_time_subindex
;
1799 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1801 time
.type
= BRW_REGISTER_TYPE_UD
;
1802 emit(MOV(time
, src_reg(value
)));
1804 vec4_instruction
*inst
=
1805 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1812 sanity_param_count
= prog
->Parameters
->NumParameters
;
1814 if (shader_time_index
>= 0)
1815 emit_shader_time_begin();
1817 assign_binding_table_offsets();
1821 assert(prog
->nir
!= NULL
);
1831 /* Before any optimization, push array accesses out to scratch
1832 * space where we need them to be. This pass may allocate new
1833 * virtual GRFs, so we want to do it early. It also makes sure
1834 * that we have reladdr computations available for CSE, since we'll
1835 * often do repeated subexpressions for those.
1837 move_grf_array_access_to_scratch();
1838 move_uniform_array_access_to_pull_constants();
1840 pack_uniform_registers();
1841 move_push_constants_to_pull_constants();
1842 split_virtual_grfs();
1844 #define OPT(pass, args...) ({ \
1846 bool this_progress = pass(args); \
1848 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1849 char filename[64]; \
1850 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1851 stage_abbrev, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1853 backend_shader::dump_instructions(filename); \
1856 progress = progress || this_progress; \
1861 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1863 snprintf(filename
, 64, "%s-%04d-00-start",
1864 stage_abbrev
, shader_prog
? shader_prog
->Name
: 0);
1866 backend_shader::dump_instructions(filename
);
1877 OPT(opt_reduce_swizzle
);
1878 OPT(dead_code_eliminate
);
1879 OPT(dead_control_flow_eliminate
, this);
1880 OPT(opt_copy_propagation
);
1883 OPT(opt_register_coalesce
);
1884 OPT(eliminate_find_live_channel
);
1889 if (OPT(opt_vector_float
)) {
1891 OPT(opt_copy_propagation
, false);
1892 OPT(opt_copy_propagation
, true);
1893 OPT(dead_code_eliminate
);
1901 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1902 /* Debug of register spilling: Go spill everything. */
1903 const int grf_count
= alloc
.count
;
1904 float spill_costs
[alloc
.count
];
1905 bool no_spill
[alloc
.count
];
1906 evaluate_spill_costs(spill_costs
, no_spill
);
1907 for (int i
= 0; i
< grf_count
; i
++) {
1914 bool allocated_without_spills
= reg_allocate();
1916 if (!allocated_without_spills
) {
1917 compiler
->shader_perf_log(log_data
,
1918 "%s shader triggered register spilling. "
1919 "Try reducing the number of live vec4 values "
1920 "to improve performance.\n",
1923 while (!reg_allocate()) {
1929 opt_schedule_instructions();
1931 opt_set_dependency_control();
1933 if (last_scratch
> 0) {
1934 prog_data
->base
.total_scratch
=
1935 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1938 /* If any state parameters were appended, then ParameterValues could have
1939 * been realloced, in which case the driver uniform storage set up by
1940 * _mesa_associate_uniform_storage() would point to freed memory. Make
1941 * sure that didn't happen.
1943 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1948 } /* namespace brw */
1953 * Compile a vertex shader.
1955 * Returns the final assembly and the program's size.
1958 brw_vs_emit(struct brw_context
*brw
,
1960 const struct brw_vs_prog_key
*key
,
1961 struct brw_vs_prog_data
*prog_data
,
1962 struct gl_vertex_program
*vp
,
1963 struct gl_shader_program
*prog
,
1964 unsigned *final_assembly_size
)
1966 const unsigned *assembly
= NULL
;
1968 struct brw_shader
*shader
= NULL
;
1970 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1973 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1974 st_index
= brw_get_shader_time_index(brw
, prog
, &vp
->Base
, ST_VS
);
1976 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1977 brw_dump_ir("vertex", prog
, &shader
->base
, &vp
->Base
);
1979 if (brw
->intelScreen
->compiler
->scalar_vs
) {
1980 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1982 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
1983 mem_ctx
, MESA_SHADER_VERTEX
, key
,
1984 &prog_data
->base
.base
, prog
, &vp
->Base
,
1986 if (!v
.run_vs(brw_select_clip_planes(&brw
->ctx
))) {
1988 prog
->LinkStatus
= false;
1989 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1992 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1998 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
1999 mem_ctx
, (void *) key
, &prog_data
->base
.base
,
2000 &vp
->Base
, v
.promoted_constants
,
2001 v
.runtime_check_aads_emit
, "VS");
2002 if (INTEL_DEBUG
& DEBUG_VS
) {
2005 name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
2006 prog
->Label
? prog
->Label
: "unnamed",
2009 name
= ralloc_asprintf(mem_ctx
, "vertex program %d",
2012 g
.enable_debug(name
);
2014 g
.generate_code(v
.cfg
, 8);
2015 assembly
= g
.get_assembly(final_assembly_size
);
2019 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2021 vec4_vs_visitor
v(brw
->intelScreen
->compiler
, brw
, key
, prog_data
,
2022 vp
, prog
, brw_select_clip_planes(&brw
->ctx
),
2024 !_mesa_is_gles3(&brw
->ctx
));
2027 prog
->LinkStatus
= false;
2028 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
2031 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
2037 vec4_generator
g(brw
->intelScreen
->compiler
, brw
,
2038 prog
, &vp
->Base
, &prog_data
->base
,
2039 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
2040 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);