2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(struct ::brw_reg reg
) :
81 src_reg::src_reg(const dst_reg
®
) :
84 this->reladdr
= reg
.reladdr
;
85 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
91 memset(this, 0, sizeof(*this));
92 this->file
= BAD_FILE
;
93 this->writemask
= WRITEMASK_XYZW
;
101 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
109 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
116 this->type
= brw_type_for_base_type(type
);
117 this->writemask
= writemask
;
120 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
128 this->writemask
= writemask
;
131 dst_reg::dst_reg(struct ::brw_reg reg
) :
134 this->reg_offset
= 0;
135 this->reladdr
= NULL
;
138 dst_reg::dst_reg(const src_reg
®
) :
141 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
142 this->reladdr
= reg
.reladdr
;
146 dst_reg::equals(const dst_reg
&r
) const
148 return (this->backend_reg::equals(r
) &&
149 (reladdr
== r
.reladdr
||
150 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
154 vec4_instruction::is_send_from_grf()
157 case SHADER_OPCODE_SHADER_TIME_ADD
:
158 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
159 case SHADER_OPCODE_UNTYPED_ATOMIC
:
160 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
161 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
162 case SHADER_OPCODE_TYPED_ATOMIC
:
163 case SHADER_OPCODE_TYPED_SURFACE_READ
:
164 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
172 vec4_instruction::regs_read(unsigned arg
) const
174 if (src
[arg
].file
== BAD_FILE
)
178 case SHADER_OPCODE_SHADER_TIME_ADD
:
179 case SHADER_OPCODE_UNTYPED_ATOMIC
:
180 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
181 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
182 case SHADER_OPCODE_TYPED_ATOMIC
:
183 case SHADER_OPCODE_TYPED_SURFACE_READ
:
184 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
185 return arg
== 0 ? mlen
: 1;
187 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
188 return arg
== 1 ? mlen
: 1;
196 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
198 if (devinfo
->gen
== 6 && is_math())
201 if (is_send_from_grf())
204 if (!backend_instruction::can_do_source_mods())
211 vec4_instruction::can_change_types() const
213 return dst
.type
== src
[0].type
&&
214 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
215 (opcode
== BRW_OPCODE_MOV
||
216 (opcode
== BRW_OPCODE_SEL
&&
217 dst
.type
== src
[1].type
&&
218 predicate
!= BRW_PREDICATE_NONE
&&
219 !src
[1].abs
&& !src
[1].negate
));
223 * Returns how many MRFs an opcode will write over.
225 * Note that this is not the 0 or 1 implied writes in an actual gen
226 * instruction -- the generate_* functions generate additional MOVs
230 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
232 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
235 switch (inst
->opcode
) {
236 case SHADER_OPCODE_RCP
:
237 case SHADER_OPCODE_RSQ
:
238 case SHADER_OPCODE_SQRT
:
239 case SHADER_OPCODE_EXP2
:
240 case SHADER_OPCODE_LOG2
:
241 case SHADER_OPCODE_SIN
:
242 case SHADER_OPCODE_COS
:
244 case SHADER_OPCODE_INT_QUOTIENT
:
245 case SHADER_OPCODE_INT_REMAINDER
:
246 case SHADER_OPCODE_POW
:
248 case VS_OPCODE_URB_WRITE
:
250 case VS_OPCODE_PULL_CONSTANT_LOAD
:
252 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
254 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
256 case GS_OPCODE_URB_WRITE
:
257 case GS_OPCODE_URB_WRITE_ALLOCATE
:
258 case GS_OPCODE_THREAD_END
:
260 case GS_OPCODE_FF_SYNC
:
262 case SHADER_OPCODE_SHADER_TIME_ADD
:
264 case SHADER_OPCODE_TEX
:
265 case SHADER_OPCODE_TXL
:
266 case SHADER_OPCODE_TXD
:
267 case SHADER_OPCODE_TXF
:
268 case SHADER_OPCODE_TXF_CMS
:
269 case SHADER_OPCODE_TXF_CMS_W
:
270 case SHADER_OPCODE_TXF_MCS
:
271 case SHADER_OPCODE_TXS
:
272 case SHADER_OPCODE_TG4
:
273 case SHADER_OPCODE_TG4_OFFSET
:
274 case SHADER_OPCODE_SAMPLEINFO
:
275 case VS_OPCODE_GET_BUFFER_SIZE
:
276 return inst
->header_size
;
278 unreachable("not reached");
283 src_reg::equals(const src_reg
&r
) const
285 return (this->backend_reg::equals(r
) &&
286 !reladdr
&& !r
.reladdr
);
290 vec4_visitor::opt_vector_float()
292 bool progress
= false;
294 int last_reg
= -1, last_reg_offset
= -1;
295 enum brw_reg_file last_reg_file
= BAD_FILE
;
297 int remaining_channels
= 0;
300 vec4_instruction
*imm_inst
[4];
302 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
303 if (last_reg
!= inst
->dst
.nr
||
304 last_reg_offset
!= inst
->dst
.reg_offset
||
305 last_reg_file
!= inst
->dst
.file
) {
306 last_reg
= inst
->dst
.nr
;
307 last_reg_offset
= inst
->dst
.reg_offset
;
308 last_reg_file
= inst
->dst
.file
;
309 remaining_channels
= WRITEMASK_XYZW
;
314 if (inst
->opcode
!= BRW_OPCODE_MOV
||
315 inst
->dst
.writemask
== WRITEMASK_XYZW
||
316 inst
->src
[0].file
!= IMM
)
319 int vf
= brw_float_to_vf(inst
->src
[0].f
);
323 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
325 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
327 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
329 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
332 imm_inst
[inst_count
++] = inst
;
334 remaining_channels
&= ~inst
->dst
.writemask
;
335 if (remaining_channels
== 0) {
337 memcpy(&vf
, imm
, sizeof(vf
));
338 vec4_instruction
*mov
= MOV(inst
->dst
, brw_imm_vf(vf
));
339 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
340 mov
->dst
.writemask
= WRITEMASK_XYZW
;
341 inst
->insert_after(block
, mov
);
344 for (int i
= 0; i
< inst_count
; i
++) {
345 imm_inst
[i
]->remove(block
);
352 invalidate_live_intervals();
357 /* Replaces unused channels of a swizzle with channels that are used.
359 * For instance, this pass transforms
361 * mov vgrf4.yz, vgrf5.wxzy
365 * mov vgrf4.yz, vgrf5.xxzx
367 * This eliminates false uses of some channels, letting dead code elimination
368 * remove the instructions that wrote them.
371 vec4_visitor::opt_reduce_swizzle()
373 bool progress
= false;
375 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
376 if (inst
->dst
.file
== BAD_FILE
||
377 inst
->dst
.file
== ARF
||
378 inst
->dst
.file
== FIXED_GRF
||
379 inst
->is_send_from_grf())
384 /* Determine which channels of the sources are read. */
385 switch (inst
->opcode
) {
386 case VEC4_OPCODE_PACK_BYTES
:
388 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
389 * but all four of src1.
391 swizzle
= brw_swizzle_for_size(4);
394 swizzle
= brw_swizzle_for_size(3);
397 swizzle
= brw_swizzle_for_size(2);
400 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
404 /* Update sources' swizzles. */
405 for (int i
= 0; i
< 3; i
++) {
406 if (inst
->src
[i
].file
!= VGRF
&&
407 inst
->src
[i
].file
!= ATTR
&&
408 inst
->src
[i
].file
!= UNIFORM
)
411 const unsigned new_swizzle
=
412 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
413 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
414 inst
->src
[i
].swizzle
= new_swizzle
;
421 invalidate_live_intervals();
427 vec4_visitor::split_uniform_registers()
429 /* Prior to this, uniforms have been in an array sized according to
430 * the number of vector uniforms present, sparsely filled (so an
431 * aggregate results in reg indices being skipped over). Now we're
432 * going to cut those aggregates up so each .nr index is one
433 * vector. The goal is to make elimination of unused uniform
434 * components easier later.
436 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
437 for (int i
= 0 ; i
< 3; i
++) {
438 if (inst
->src
[i
].file
!= UNIFORM
)
441 assert(!inst
->src
[i
].reladdr
);
443 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
444 inst
->src
[i
].reg_offset
= 0;
448 /* Update that everything is now vector-sized. */
449 for (int i
= 0; i
< this->uniforms
; i
++) {
450 this->uniform_size
[i
] = 1;
455 vec4_visitor::pack_uniform_registers()
457 uint8_t chans_used
[this->uniforms
];
458 int new_loc
[this->uniforms
];
459 int new_chan
[this->uniforms
];
461 memset(chans_used
, 0, sizeof(chans_used
));
462 memset(new_loc
, 0, sizeof(new_loc
));
463 memset(new_chan
, 0, sizeof(new_chan
));
465 /* Find which uniform vectors are actually used by the program. We
466 * expect unused vector elements when we've moved array access out
467 * to pull constants, and from some GLSL code generators like wine.
469 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
471 switch (inst
->opcode
) {
472 case VEC4_OPCODE_PACK_BYTES
:
484 readmask
= inst
->dst
.writemask
;
488 for (int i
= 0 ; i
< 3; i
++) {
489 if (inst
->src
[i
].file
!= UNIFORM
)
492 int reg
= inst
->src
[i
].nr
;
493 for (int c
= 0; c
< 4; c
++) {
494 if (!(readmask
& (1 << c
)))
497 chans_used
[reg
] = MAX2(chans_used
[reg
],
498 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
503 int new_uniform_count
= 0;
505 /* Now, figure out a packing of the live uniform vectors into our
508 for (int src
= 0; src
< uniforms
; src
++) {
509 assert(src
< uniform_array_size
);
510 int size
= chans_used
[src
];
516 /* Find the lowest place we can slot this uniform in. */
517 for (dst
= 0; dst
< src
; dst
++) {
518 if (chans_used
[dst
] + size
<= 4)
527 new_chan
[src
] = chans_used
[dst
];
529 /* Move the references to the data */
530 for (int j
= 0; j
< size
; j
++) {
531 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
532 stage_prog_data
->param
[src
* 4 + j
];
535 chans_used
[dst
] += size
;
539 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
542 this->uniforms
= new_uniform_count
;
544 /* Now, update the instructions for our repacked uniforms. */
545 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
546 for (int i
= 0 ; i
< 3; i
++) {
547 int src
= inst
->src
[i
].nr
;
549 if (inst
->src
[i
].file
!= UNIFORM
)
552 inst
->src
[i
].nr
= new_loc
[src
];
553 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
554 new_chan
[src
], new_chan
[src
]);
560 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
562 * While GLSL IR also performs this optimization, we end up with it in
563 * our instruction stream for a couple of reasons. One is that we
564 * sometimes generate silly instructions, for example in array access
565 * where we'll generate "ADD offset, index, base" even if base is 0.
566 * The other is that GLSL IR's constant propagation doesn't track the
567 * components of aggregates, so some VS patterns (initialize matrix to
568 * 0, accumulate in vertex blending factors) end up breaking down to
569 * instructions involving 0.
572 vec4_visitor::opt_algebraic()
574 bool progress
= false;
576 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
577 switch (inst
->opcode
) {
579 if (inst
->src
[0].file
!= IMM
)
582 if (inst
->saturate
) {
583 if (inst
->dst
.type
!= inst
->src
[0].type
)
584 assert(!"unimplemented: saturate mixed types");
586 if (brw_saturate_immediate(inst
->dst
.type
,
587 &inst
->src
[0].as_brw_reg())) {
588 inst
->saturate
= false;
594 case VEC4_OPCODE_UNPACK_UNIFORM
:
595 if (inst
->src
[0].file
!= UNIFORM
) {
596 inst
->opcode
= BRW_OPCODE_MOV
;
602 if (inst
->src
[1].is_zero()) {
603 inst
->opcode
= BRW_OPCODE_MOV
;
604 inst
->src
[1] = src_reg();
610 if (inst
->src
[1].is_zero()) {
611 inst
->opcode
= BRW_OPCODE_MOV
;
612 switch (inst
->src
[0].type
) {
613 case BRW_REGISTER_TYPE_F
:
614 inst
->src
[0] = brw_imm_f(0.0f
);
616 case BRW_REGISTER_TYPE_D
:
617 inst
->src
[0] = brw_imm_d(0);
619 case BRW_REGISTER_TYPE_UD
:
620 inst
->src
[0] = brw_imm_ud(0u);
623 unreachable("not reached");
625 inst
->src
[1] = src_reg();
627 } else if (inst
->src
[1].is_one()) {
628 inst
->opcode
= BRW_OPCODE_MOV
;
629 inst
->src
[1] = src_reg();
631 } else if (inst
->src
[1].is_negative_one()) {
632 inst
->opcode
= BRW_OPCODE_MOV
;
633 inst
->src
[0].negate
= !inst
->src
[0].negate
;
634 inst
->src
[1] = src_reg();
639 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
641 inst
->src
[0].negate
&&
642 inst
->src
[1].is_zero()) {
643 inst
->src
[0].abs
= false;
644 inst
->src
[0].negate
= false;
645 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
650 case SHADER_OPCODE_RCP
: {
651 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
652 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
653 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
654 inst
->opcode
= SHADER_OPCODE_RSQ
;
655 inst
->src
[0] = prev
->src
[0];
661 case SHADER_OPCODE_BROADCAST
:
662 if (is_uniform(inst
->src
[0]) ||
663 inst
->src
[1].is_zero()) {
664 inst
->opcode
= BRW_OPCODE_MOV
;
665 inst
->src
[1] = src_reg();
666 inst
->force_writemask_all
= true;
677 invalidate_live_intervals();
683 * Only a limited number of hardware registers may be used for push
684 * constants, so this turns access to the overflowed constants into
688 vec4_visitor::move_push_constants_to_pull_constants()
690 int pull_constant_loc
[this->uniforms
];
692 /* Only allow 32 registers (256 uniform components) as push constants,
693 * which is the limit on gen6.
695 * If changing this value, note the limitation about total_regs in
698 int max_uniform_components
= 32 * 8;
699 if (this->uniforms
* 4 <= max_uniform_components
)
702 /* Make some sort of choice as to which uniforms get sent to pull
703 * constants. We could potentially do something clever here like
704 * look for the most infrequently used uniform vec4s, but leave
707 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
708 pull_constant_loc
[i
/ 4] = -1;
710 if (i
>= max_uniform_components
) {
711 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
713 /* Try to find an existing copy of this uniform in the pull
714 * constants if it was part of an array access already.
716 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
719 for (matches
= 0; matches
< 4; matches
++) {
720 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
725 pull_constant_loc
[i
/ 4] = j
/ 4;
730 if (pull_constant_loc
[i
/ 4] == -1) {
731 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
732 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
734 for (int j
= 0; j
< 4; j
++) {
735 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
742 /* Now actually rewrite usage of the things we've moved to pull
745 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
746 for (int i
= 0 ; i
< 3; i
++) {
747 if (inst
->src
[i
].file
!= UNIFORM
||
748 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
751 int uniform
= inst
->src
[i
].nr
;
753 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
755 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
756 pull_constant_loc
[uniform
]);
758 inst
->src
[i
].file
= temp
.file
;
759 inst
->src
[i
].nr
= temp
.nr
;
760 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
761 inst
->src
[i
].reladdr
= NULL
;
765 /* Repack push constants to remove the now-unused ones. */
766 pack_uniform_registers();
769 /* Conditions for which we want to avoid setting the dependency control bits */
771 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
773 #define IS_DWORD(reg) \
774 (reg.type == BRW_REGISTER_TYPE_UD || \
775 reg.type == BRW_REGISTER_TYPE_D)
777 /* "When source or destination datatype is 64b or operation is integer DWord
778 * multiply, DepCtrl must not be used."
779 * May apply to future SoCs as well.
781 if (devinfo
->is_cherryview
) {
782 if (inst
->opcode
== BRW_OPCODE_MUL
&&
783 IS_DWORD(inst
->src
[0]) &&
784 IS_DWORD(inst
->src
[1]))
789 if (devinfo
->gen
>= 8) {
790 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
796 * In the presence of send messages, totally interrupt dependency
797 * control. They're long enough that the chance of dependency
798 * control around them just doesn't matter.
801 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
802 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
803 * completes the scoreboard clear must have a non-zero execution mask. This
804 * means, if any kind of predication can change the execution mask or channel
805 * enable of the last instruction, the optimization must be avoided. This is
806 * to avoid instructions being shot down the pipeline when no writes are
810 * Dependency control does not work well over math instructions.
811 * NB: Discovered empirically
813 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
817 * Sets the dependency control fields on instructions after register
818 * allocation and before the generator is run.
820 * When you have a sequence of instructions like:
822 * DP4 temp.x vertex uniform[0]
823 * DP4 temp.y vertex uniform[0]
824 * DP4 temp.z vertex uniform[0]
825 * DP4 temp.w vertex uniform[0]
827 * The hardware doesn't know that it can actually run the later instructions
828 * while the previous ones are in flight, producing stalls. However, we have
829 * manual fields we can set in the instructions that let it do so.
832 vec4_visitor::opt_set_dependency_control()
834 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
835 uint8_t grf_channels_written
[BRW_MAX_GRF
];
836 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
837 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
839 assert(prog_data
->total_grf
||
840 !"Must be called after register allocation");
842 foreach_block (block
, cfg
) {
843 memset(last_grf_write
, 0, sizeof(last_grf_write
));
844 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
846 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
847 /* If we read from a register that we were doing dependency control
848 * on, don't do dependency control across the read.
850 for (int i
= 0; i
< 3; i
++) {
851 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
852 if (inst
->src
[i
].file
== VGRF
) {
853 last_grf_write
[reg
] = NULL
;
854 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
855 memset(last_grf_write
, 0, sizeof(last_grf_write
));
858 assert(inst
->src
[i
].file
!= MRF
);
861 if (is_dep_ctrl_unsafe(inst
)) {
862 memset(last_grf_write
, 0, sizeof(last_grf_write
));
863 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
867 /* Now, see if we can do dependency control for this instruction
868 * against a previous one writing to its destination.
870 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
871 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
872 if (last_grf_write
[reg
] &&
873 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
874 last_grf_write
[reg
]->no_dd_clear
= true;
875 inst
->no_dd_check
= true;
877 grf_channels_written
[reg
] = 0;
880 last_grf_write
[reg
] = inst
;
881 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
882 } else if (inst
->dst
.file
== MRF
) {
883 if (last_mrf_write
[reg
] &&
884 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
885 last_mrf_write
[reg
]->no_dd_clear
= true;
886 inst
->no_dd_check
= true;
888 mrf_channels_written
[reg
] = 0;
891 last_mrf_write
[reg
] = inst
;
892 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
899 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
904 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
905 * or writemasking are not allowed.
907 if (devinfo
->gen
== 6 && is_math() &&
908 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
911 /* If this instruction sets anything not referenced by swizzle, then we'd
912 * totally break it when we reswizzle.
914 if (dst
.writemask
& ~swizzle_mask
)
920 for (int i
= 0; i
< 3; i
++) {
921 if (src
[i
].is_accumulator())
929 * For any channels in the swizzle's source that were populated by this
930 * instruction, rewrite the instruction to put the appropriate result directly
933 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
936 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
938 /* Destination write mask doesn't correspond to source swizzle for the dot
939 * product and pack_bytes instructions.
941 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
942 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
943 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
944 for (int i
= 0; i
< 3; i
++) {
945 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
948 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
952 /* Apply the specified swizzle and writemask to the original mask of
953 * written components.
955 dst
.writemask
= dst_writemask
&
956 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
960 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
961 * just written and then MOVed into another reg and making the original write
962 * of the GRF write directly to the final destination instead.
965 vec4_visitor::opt_register_coalesce()
967 bool progress
= false;
970 calculate_live_intervals();
972 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
976 if (inst
->opcode
!= BRW_OPCODE_MOV
||
977 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
979 inst
->src
[0].file
!= VGRF
||
980 inst
->dst
.type
!= inst
->src
[0].type
||
981 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
984 /* Remove no-op MOVs */
985 if (inst
->dst
.file
== inst
->src
[0].file
&&
986 inst
->dst
.nr
== inst
->src
[0].nr
&&
987 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
988 bool is_nop_mov
= true;
990 for (unsigned c
= 0; c
< 4; c
++) {
991 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
994 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1001 inst
->remove(block
);
1006 bool to_mrf
= (inst
->dst
.file
== MRF
);
1008 /* Can't coalesce this GRF if someone else was going to
1011 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1014 /* We need to check interference with the final destination between this
1015 * instruction and the earliest instruction involved in writing the GRF
1016 * we're eliminating. To do that, keep track of which of our source
1017 * channels we've seen initialized.
1019 const unsigned chans_needed
=
1020 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1021 inst
->dst
.writemask
);
1022 unsigned chans_remaining
= chans_needed
;
1024 /* Now walk up the instruction stream trying to see if we can rewrite
1025 * everything writing to the temporary to write into the destination
1028 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1029 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1031 _scan_inst
= scan_inst
;
1033 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1034 /* Found something writing to the reg we want to coalesce away. */
1036 /* SEND instructions can't have MRF as a destination. */
1037 if (scan_inst
->mlen
)
1040 if (devinfo
->gen
== 6) {
1041 /* gen6 math instructions must have the destination be
1042 * VGRF, so no compute-to-MRF for them.
1044 if (scan_inst
->is_math()) {
1050 /* This doesn't handle saturation on the instruction we
1051 * want to coalesce away if the register types do not match.
1052 * But if scan_inst is a non type-converting 'mov', we can fix
1055 if (inst
->saturate
&&
1056 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1057 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1058 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1061 /* If we can't handle the swizzle, bail. */
1062 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1063 inst
->src
[0].swizzle
,
1068 /* This doesn't handle coalescing of multiple registers. */
1069 if (scan_inst
->regs_written
> 1)
1072 /* Mark which channels we found unconditional writes for. */
1073 if (!scan_inst
->predicate
)
1074 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1076 if (chans_remaining
== 0)
1080 /* You can't read from an MRF, so if someone else reads our MRF's
1081 * source GRF that we wanted to rewrite, that stops us. If it's a
1082 * GRF we're trying to coalesce to, we don't actually handle
1083 * rewriting sources so bail in that case as well.
1085 bool interfered
= false;
1086 for (int i
= 0; i
< 3; i
++) {
1087 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1088 scan_inst
->regs_read(i
)))
1094 /* If somebody else writes the same channels of our destination here,
1095 * we can't coalesce before that.
1097 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1098 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1102 /* Check for reads of the register we're trying to coalesce into. We
1103 * can't go rewriting instructions above that to put some other value
1104 * in the register instead.
1106 if (to_mrf
&& scan_inst
->mlen
> 0) {
1107 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1108 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1112 for (int i
= 0; i
< 3; i
++) {
1113 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1114 scan_inst
->regs_read(i
)))
1122 if (chans_remaining
== 0) {
1123 /* If we've made it here, we have an MOV we want to coalesce out, and
1124 * a scan_inst pointing to the earliest instruction involved in
1125 * computing the value. Now go rewrite the instruction stream
1128 vec4_instruction
*scan_inst
= _scan_inst
;
1129 while (scan_inst
!= inst
) {
1130 if (scan_inst
->dst
.file
== VGRF
&&
1131 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1132 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1133 scan_inst
->reswizzle(inst
->dst
.writemask
,
1134 inst
->src
[0].swizzle
);
1135 scan_inst
->dst
.file
= inst
->dst
.file
;
1136 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1137 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1138 if (inst
->saturate
&&
1139 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1140 /* If we have reached this point, scan_inst is a non
1141 * type-converting 'mov' and we can modify its register types
1142 * to match the ones in inst. Otherwise, we could have an
1143 * incorrect saturation result.
1145 scan_inst
->dst
.type
= inst
->dst
.type
;
1146 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1148 scan_inst
->saturate
|= inst
->saturate
;
1150 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1152 inst
->remove(block
);
1158 invalidate_live_intervals();
1164 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1165 * flow. We could probably do better here with some form of divergence
1169 vec4_visitor::eliminate_find_live_channel()
1171 bool progress
= false;
1174 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1175 switch (inst
->opcode
) {
1181 case BRW_OPCODE_ENDIF
:
1182 case BRW_OPCODE_WHILE
:
1186 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1188 inst
->opcode
= BRW_OPCODE_MOV
;
1189 inst
->src
[0] = brw_imm_d(0);
1190 inst
->force_writemask_all
= true;
1204 * Splits virtual GRFs requesting more than one contiguous physical register.
1206 * We initially create large virtual GRFs for temporary structures, arrays,
1207 * and matrices, so that the dereference visitor functions can add reg_offsets
1208 * to work their way down to the actual member being accessed. But when it
1209 * comes to optimization, we'd like to treat each register as individual
1210 * storage if possible.
1212 * So far, the only thing that might prevent splitting is a send message from
1216 vec4_visitor::split_virtual_grfs()
1218 int num_vars
= this->alloc
.count
;
1219 int new_virtual_grf
[num_vars
];
1220 bool split_grf
[num_vars
];
1222 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1224 /* Try to split anything > 0 sized. */
1225 for (int i
= 0; i
< num_vars
; i
++) {
1226 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1229 /* Check that the instructions are compatible with the registers we're trying
1232 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1233 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1234 split_grf
[inst
->dst
.nr
] = false;
1236 for (int i
= 0; i
< 3; i
++) {
1237 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1238 split_grf
[inst
->src
[i
].nr
] = false;
1242 /* Allocate new space for split regs. Note that the virtual
1243 * numbers will be contiguous.
1245 for (int i
= 0; i
< num_vars
; i
++) {
1249 new_virtual_grf
[i
] = alloc
.allocate(1);
1250 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1251 unsigned reg
= alloc
.allocate(1);
1252 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1255 this->alloc
.sizes
[i
] = 1;
1258 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1259 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1260 inst
->dst
.reg_offset
!= 0) {
1261 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1262 inst
->dst
.reg_offset
- 1);
1263 inst
->dst
.reg_offset
= 0;
1265 for (int i
= 0; i
< 3; i
++) {
1266 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1267 inst
->src
[i
].reg_offset
!= 0) {
1268 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1269 inst
->src
[i
].reg_offset
- 1);
1270 inst
->src
[i
].reg_offset
= 0;
1274 invalidate_live_intervals();
1278 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1280 dump_instruction(be_inst
, stderr
);
1284 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1286 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1288 if (inst
->predicate
) {
1289 fprintf(file
, "(%cf0.%d%s) ",
1290 inst
->predicate_inverse
? '-' : '+',
1292 pred_ctrl_align16
[inst
->predicate
]);
1295 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1297 fprintf(file
, ".sat");
1298 if (inst
->conditional_mod
) {
1299 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1300 if (!inst
->predicate
&&
1301 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1302 inst
->opcode
!= BRW_OPCODE_IF
&&
1303 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1304 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1309 switch (inst
->dst
.file
) {
1311 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1314 fprintf(file
, "g%d", inst
->dst
.nr
);
1317 fprintf(file
, "m%d", inst
->dst
.nr
);
1320 switch (inst
->dst
.nr
) {
1322 fprintf(file
, "null");
1324 case BRW_ARF_ADDRESS
:
1325 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1327 case BRW_ARF_ACCUMULATOR
:
1328 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1331 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1334 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1337 if (inst
->dst
.subnr
)
1338 fprintf(file
, "+%d", inst
->dst
.subnr
);
1341 fprintf(file
, "(null)");
1346 unreachable("not reached");
1348 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1350 if (inst
->dst
.writemask
& 1)
1352 if (inst
->dst
.writemask
& 2)
1354 if (inst
->dst
.writemask
& 4)
1356 if (inst
->dst
.writemask
& 8)
1359 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1361 if (inst
->src
[0].file
!= BAD_FILE
)
1362 fprintf(file
, ", ");
1364 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1365 if (inst
->src
[i
].negate
)
1367 if (inst
->src
[i
].abs
)
1369 switch (inst
->src
[i
].file
) {
1371 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1374 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1377 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1380 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1383 switch (inst
->src
[i
].type
) {
1384 case BRW_REGISTER_TYPE_F
:
1385 fprintf(file
, "%fF", inst
->src
[i
].f
);
1387 case BRW_REGISTER_TYPE_D
:
1388 fprintf(file
, "%dD", inst
->src
[i
].d
);
1390 case BRW_REGISTER_TYPE_UD
:
1391 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1393 case BRW_REGISTER_TYPE_VF
:
1394 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1395 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1396 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1397 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1398 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1401 fprintf(file
, "???");
1406 switch (inst
->src
[i
].nr
) {
1408 fprintf(file
, "null");
1410 case BRW_ARF_ADDRESS
:
1411 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1413 case BRW_ARF_ACCUMULATOR
:
1414 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1417 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1420 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1423 if (inst
->src
[i
].subnr
)
1424 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1427 fprintf(file
, "(null)");
1430 unreachable("not reached");
1433 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1434 if (inst
->src
[i
].reg_offset
!= 0 &&
1435 inst
->src
[i
].file
== VGRF
&&
1436 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1437 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1439 if (inst
->src
[i
].file
!= IMM
) {
1440 static const char *chans
[4] = {"x", "y", "z", "w"};
1442 for (int c
= 0; c
< 4; c
++) {
1443 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1447 if (inst
->src
[i
].abs
)
1450 if (inst
->src
[i
].file
!= IMM
) {
1451 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1454 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1455 fprintf(file
, ", ");
1458 if (inst
->force_writemask_all
)
1459 fprintf(file
, " NoMask");
1461 fprintf(file
, "\n");
1465 static inline struct brw_reg
1466 attribute_to_hw_reg(int attr
, bool interleaved
)
1469 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1471 return brw_vec8_grf(attr
, 0);
1476 * Replace each register of type ATTR in this->instructions with a reference
1477 * to a fixed HW register.
1479 * If interleaved is true, then each attribute takes up half a register, with
1480 * register N containing attribute 2*N in its first half and attribute 2*N+1
1481 * in its second half (this corresponds to the payload setup used by geometry
1482 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1483 * false, then each attribute takes up a whole register, with register N
1484 * containing attribute N (this corresponds to the payload setup used by
1485 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1488 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1491 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1492 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1493 if (inst
->dst
.file
== ATTR
) {
1494 int grf
= attribute_map
[inst
->dst
.nr
+ inst
->dst
.reg_offset
];
1496 /* All attributes used in the shader need to have been assigned a
1497 * hardware register by the caller
1501 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1502 reg
.type
= inst
->dst
.type
;
1503 reg
.writemask
= inst
->dst
.writemask
;
1508 for (int i
= 0; i
< 3; i
++) {
1509 if (inst
->src
[i
].file
!= ATTR
)
1512 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1514 /* All attributes used in the shader need to have been assigned a
1515 * hardware register by the caller
1519 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1520 reg
.swizzle
= inst
->src
[i
].swizzle
;
1521 reg
.type
= inst
->src
[i
].type
;
1522 if (inst
->src
[i
].abs
)
1524 if (inst
->src
[i
].negate
)
1533 vec4_vs_visitor::setup_attributes(int payload_reg
)
1536 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1537 memset(attribute_map
, 0, sizeof(attribute_map
));
1540 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1541 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1542 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1547 /* VertexID is stored by the VF as the last vertex element, but we
1548 * don't represent it with a flag in inputs_read, so we call it
1551 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1552 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1555 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1557 return payload_reg
+ vs_prog_data
->nr_attributes
;
1561 vec4_visitor::setup_uniforms(int reg
)
1563 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1565 /* The pre-gen6 VS requires that some push constants get loaded no
1566 * matter what, or the GPU would hang.
1568 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1569 assert(this->uniforms
< this->uniform_array_size
);
1571 stage_prog_data
->param
=
1572 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1573 for (unsigned int i
= 0; i
< 4; i
++) {
1574 unsigned int slot
= this->uniforms
* 4 + i
;
1575 static gl_constant_value zero
= { 0.0 };
1576 stage_prog_data
->param
[slot
] = &zero
;
1582 reg
+= ALIGN(uniforms
, 2) / 2;
1585 stage_prog_data
->nr_params
= this->uniforms
* 4;
1587 prog_data
->base
.curb_read_length
=
1588 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1594 vec4_vs_visitor::setup_payload(void)
1598 /* The payload always contains important data in g0, which contains
1599 * the URB handles that are passed on to the URB write at the end
1600 * of the thread. So, we always start push constants at g1.
1604 reg
= setup_uniforms(reg
);
1606 reg
= setup_attributes(reg
);
1608 this->first_non_payload_grf
= reg
;
1612 vec4_visitor::get_timestamp()
1614 assert(devinfo
->gen
>= 7);
1616 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1621 BRW_REGISTER_TYPE_UD
,
1622 BRW_VERTICAL_STRIDE_0
,
1624 BRW_HORIZONTAL_STRIDE_4
,
1628 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1630 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1631 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1632 * even if it's not enabled in the dispatch.
1634 mov
->force_writemask_all
= true;
1636 return src_reg(dst
);
1640 vec4_visitor::emit_shader_time_begin()
1642 current_annotation
= "shader time start";
1643 shader_start_time
= get_timestamp();
1647 vec4_visitor::emit_shader_time_end()
1649 current_annotation
= "shader time end";
1650 src_reg shader_end_time
= get_timestamp();
1653 /* Check that there weren't any timestamp reset events (assuming these
1654 * were the only two timestamp reads that happened).
1656 src_reg reset_end
= shader_end_time
;
1657 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1658 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1659 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1661 emit(IF(BRW_PREDICATE_NORMAL
));
1663 /* Take the current timestamp and get the delta. */
1664 shader_start_time
.negate
= true;
1665 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1666 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1668 /* If there were no instructions between the two timestamp gets, the diff
1669 * is 2 cycles. Remove that overhead, so I can forget about that when
1670 * trying to determine the time taken for single instructions.
1672 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1674 emit_shader_time_write(0, src_reg(diff
));
1675 emit_shader_time_write(1, brw_imm_ud(1u));
1676 emit(BRW_OPCODE_ELSE
);
1677 emit_shader_time_write(2, brw_imm_ud(1u));
1678 emit(BRW_OPCODE_ENDIF
);
1682 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1685 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1687 dst_reg offset
= dst
;
1691 offset
.type
= BRW_REGISTER_TYPE_UD
;
1692 int index
= shader_time_index
* 3 + shader_time_subindex
;
1693 emit(MOV(offset
, brw_imm_d(index
* SHADER_TIME_STRIDE
)));
1695 time
.type
= BRW_REGISTER_TYPE_UD
;
1696 emit(MOV(time
, value
));
1698 vec4_instruction
*inst
=
1699 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1704 vec4_visitor::convert_to_hw_regs()
1706 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1707 for (int i
= 0; i
< 3; i
++) {
1708 struct src_reg
&src
= inst
->src
[i
];
1712 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1713 reg
.type
= src
.type
;
1714 reg
.swizzle
= src
.swizzle
;
1716 reg
.negate
= src
.negate
;
1720 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1721 (src
.nr
+ src
.reg_offset
) / 2,
1722 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1724 reg
.type
= src
.type
;
1725 reg
.swizzle
= src
.swizzle
;
1727 reg
.negate
= src
.negate
;
1729 /* This should have been moved to pull constants. */
1730 assert(!src
.reladdr
);
1739 /* Probably unused. */
1740 reg
= brw_null_reg();
1745 unreachable("not reached");
1750 dst_reg
&dst
= inst
->dst
;
1753 switch (inst
->dst
.file
) {
1755 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1756 reg
.type
= dst
.type
;
1757 reg
.writemask
= dst
.writemask
;
1761 assert(((dst
.nr
+ dst
.reg_offset
) & ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
1762 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1763 reg
.type
= dst
.type
;
1764 reg
.writemask
= dst
.writemask
;
1769 reg
= dst
.as_brw_reg();
1773 reg
= brw_null_reg();
1779 unreachable("not reached");
1789 if (shader_time_index
>= 0)
1790 emit_shader_time_begin();
1803 /* Before any optimization, push array accesses out to scratch
1804 * space where we need them to be. This pass may allocate new
1805 * virtual GRFs, so we want to do it early. It also makes sure
1806 * that we have reladdr computations available for CSE, since we'll
1807 * often do repeated subexpressions for those.
1809 move_grf_array_access_to_scratch();
1810 move_uniform_array_access_to_pull_constants();
1812 pack_uniform_registers();
1813 move_push_constants_to_pull_constants();
1814 split_virtual_grfs();
1816 #define OPT(pass, args...) ({ \
1818 bool this_progress = pass(args); \
1820 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1821 char filename[64]; \
1822 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1823 stage_abbrev, nir->info.name, iteration, pass_num); \
1825 backend_shader::dump_instructions(filename); \
1828 progress = progress || this_progress; \
1833 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1835 snprintf(filename
, 64, "%s-%s-00-start",
1836 stage_abbrev
, nir
->info
.name
);
1838 backend_shader::dump_instructions(filename
);
1849 OPT(opt_predicated_break
, this);
1850 OPT(opt_reduce_swizzle
);
1851 OPT(dead_code_eliminate
);
1852 OPT(dead_control_flow_eliminate
, this);
1853 OPT(opt_copy_propagation
);
1854 OPT(opt_cmod_propagation
);
1857 OPT(opt_register_coalesce
);
1858 OPT(eliminate_find_live_channel
);
1863 if (OPT(opt_vector_float
)) {
1865 OPT(opt_copy_propagation
, false);
1866 OPT(opt_copy_propagation
, true);
1867 OPT(dead_code_eliminate
);
1875 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1876 /* Debug of register spilling: Go spill everything. */
1877 const int grf_count
= alloc
.count
;
1878 float spill_costs
[alloc
.count
];
1879 bool no_spill
[alloc
.count
];
1880 evaluate_spill_costs(spill_costs
, no_spill
);
1881 for (int i
= 0; i
< grf_count
; i
++) {
1888 bool allocated_without_spills
= reg_allocate();
1890 if (!allocated_without_spills
) {
1891 compiler
->shader_perf_log(log_data
,
1892 "%s shader triggered register spilling. "
1893 "Try reducing the number of live vec4 values "
1894 "to improve performance.\n",
1897 while (!reg_allocate()) {
1903 opt_schedule_instructions();
1905 opt_set_dependency_control();
1907 convert_to_hw_regs();
1909 if (last_scratch
> 0) {
1910 prog_data
->base
.total_scratch
=
1911 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1917 } /* namespace brw */
1922 * Compile a vertex shader.
1924 * Returns the final assembly and the program's size.
1927 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1929 const struct brw_vs_prog_key
*key
,
1930 struct brw_vs_prog_data
*prog_data
,
1931 const nir_shader
*src_shader
,
1932 gl_clip_plane
*clip_planes
,
1933 bool use_legacy_snorm_formula
,
1934 int shader_time_index
,
1935 unsigned *final_assembly_size
,
1938 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
1939 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
1940 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
1941 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
,
1942 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
1944 const unsigned *assembly
= NULL
;
1946 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
1948 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
1949 * incoming vertex attribute. So, add an extra slot.
1951 if (shader
->info
.system_values_read
&
1952 (BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
1953 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
1957 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
1958 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
1959 * vec4 mode, the hardware appears to wedge unless we read something.
1961 if (compiler
->scalar_stage
[MESA_SHADER_VERTEX
])
1962 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
1964 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
1966 prog_data
->nr_attributes
= nr_attributes
;
1968 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
1969 * (overwriting the original contents), we need to make sure the size is
1970 * the larger of the two.
1972 const unsigned vue_entries
=
1973 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
1975 if (compiler
->devinfo
->gen
== 6)
1976 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
1978 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
1980 if (compiler
->scalar_stage
[MESA_SHADER_VERTEX
]) {
1981 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1983 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
1984 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
1985 shader
, 8, shader_time_index
);
1986 if (!v
.run_vs(clip_planes
)) {
1988 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1993 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1994 &prog_data
->base
.base
, v
.promoted_constants
,
1995 v
.runtime_check_aads_emit
, "VS");
1996 if (INTEL_DEBUG
& DEBUG_VS
) {
1997 const char *debug_name
=
1998 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
1999 shader
->info
.label
? shader
->info
.label
: "unnamed",
2002 g
.enable_debug(debug_name
);
2004 g
.generate_code(v
.cfg
, 8);
2005 assembly
= g
.get_assembly(final_assembly_size
);
2009 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2011 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2012 shader
, clip_planes
, mem_ctx
,
2013 shader_time_index
, use_legacy_snorm_formula
);
2016 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2021 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2022 shader
, &prog_data
->base
, v
.cfg
,
2023 final_assembly_size
);