2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
66 /** Generic unset register constructor. */
72 src_reg::src_reg(float f
)
77 this->type
= BRW_REGISTER_TYPE_F
;
78 this->fixed_hw_reg
.dw1
.f
= f
;
81 src_reg::src_reg(uint32_t u
)
86 this->type
= BRW_REGISTER_TYPE_UD
;
87 this->fixed_hw_reg
.dw1
.ud
= u
;
90 src_reg::src_reg(int32_t i
)
95 this->type
= BRW_REGISTER_TYPE_D
;
96 this->fixed_hw_reg
.dw1
.d
= i
;
99 src_reg::src_reg(uint8_t vf
[4])
104 this->type
= BRW_REGISTER_TYPE_VF
;
105 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
108 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
113 this->type
= BRW_REGISTER_TYPE_VF
;
114 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
120 src_reg::src_reg(struct brw_reg reg
)
125 this->fixed_hw_reg
= reg
;
126 this->type
= reg
.type
;
129 src_reg::src_reg(const dst_reg
®
)
133 this->file
= reg
.file
;
135 this->reg_offset
= reg
.reg_offset
;
136 this->type
= reg
.type
;
137 this->reladdr
= reg
.reladdr
;
138 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
145 memset(this, 0, sizeof(*this));
146 this->file
= BAD_FILE
;
147 this->writemask
= WRITEMASK_XYZW
;
155 dst_reg::dst_reg(register_file file
, int reg
)
163 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
170 this->type
= brw_type_for_base_type(type
);
171 this->writemask
= writemask
;
174 dst_reg::dst_reg(register_file file
, int reg
, brw_reg_type type
,
182 this->writemask
= writemask
;
185 dst_reg::dst_reg(struct brw_reg reg
)
190 this->fixed_hw_reg
= reg
;
191 this->type
= reg
.type
;
194 dst_reg::dst_reg(const src_reg
®
)
198 this->file
= reg
.file
;
200 this->reg_offset
= reg
.reg_offset
;
201 this->type
= reg
.type
;
202 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
203 this->reladdr
= reg
.reladdr
;
204 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
208 dst_reg::equals(const dst_reg
&r
) const
210 return (file
== r
.file
&&
212 reg_offset
== r
.reg_offset
&&
214 negate
== r
.negate
&&
216 writemask
== r
.writemask
&&
217 (reladdr
== r
.reladdr
||
218 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
219 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
220 sizeof(fixed_hw_reg
)) == 0);
224 vec4_instruction::is_send_from_grf()
227 case SHADER_OPCODE_SHADER_TIME_ADD
:
228 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
229 case SHADER_OPCODE_UNTYPED_ATOMIC
:
230 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
231 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
232 case SHADER_OPCODE_TYPED_ATOMIC
:
233 case SHADER_OPCODE_TYPED_SURFACE_READ
:
234 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
242 vec4_instruction::regs_read(unsigned arg
) const
244 if (src
[arg
].file
== BAD_FILE
)
248 case SHADER_OPCODE_SHADER_TIME_ADD
:
249 case SHADER_OPCODE_UNTYPED_ATOMIC
:
250 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
251 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
252 case SHADER_OPCODE_TYPED_ATOMIC
:
253 case SHADER_OPCODE_TYPED_SURFACE_READ
:
254 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
255 return arg
== 0 ? mlen
: 1;
257 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
258 return arg
== 1 ? mlen
: 1;
266 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
268 if (devinfo
->gen
== 6 && is_math())
271 if (is_send_from_grf())
274 if (!backend_instruction::can_do_source_mods())
281 * Returns how many MRFs an opcode will write over.
283 * Note that this is not the 0 or 1 implied writes in an actual gen
284 * instruction -- the generate_* functions generate additional MOVs
288 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
290 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
293 switch (inst
->opcode
) {
294 case SHADER_OPCODE_RCP
:
295 case SHADER_OPCODE_RSQ
:
296 case SHADER_OPCODE_SQRT
:
297 case SHADER_OPCODE_EXP2
:
298 case SHADER_OPCODE_LOG2
:
299 case SHADER_OPCODE_SIN
:
300 case SHADER_OPCODE_COS
:
302 case SHADER_OPCODE_INT_QUOTIENT
:
303 case SHADER_OPCODE_INT_REMAINDER
:
304 case SHADER_OPCODE_POW
:
306 case VS_OPCODE_URB_WRITE
:
308 case VS_OPCODE_PULL_CONSTANT_LOAD
:
310 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
312 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
314 case GS_OPCODE_URB_WRITE
:
315 case GS_OPCODE_URB_WRITE_ALLOCATE
:
316 case GS_OPCODE_THREAD_END
:
318 case GS_OPCODE_FF_SYNC
:
320 case SHADER_OPCODE_SHADER_TIME_ADD
:
322 case SHADER_OPCODE_TEX
:
323 case SHADER_OPCODE_TXL
:
324 case SHADER_OPCODE_TXD
:
325 case SHADER_OPCODE_TXF
:
326 case SHADER_OPCODE_TXF_CMS
:
327 case SHADER_OPCODE_TXF_MCS
:
328 case SHADER_OPCODE_TXS
:
329 case SHADER_OPCODE_TG4
:
330 case SHADER_OPCODE_TG4_OFFSET
:
331 return inst
->header_size
;
333 unreachable("not reached");
338 src_reg::equals(const src_reg
&r
) const
340 return (file
== r
.file
&&
342 reg_offset
== r
.reg_offset
&&
344 negate
== r
.negate
&&
346 swizzle
== r
.swizzle
&&
347 !reladdr
&& !r
.reladdr
&&
348 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
349 sizeof(fixed_hw_reg
)) == 0);
353 vec4_visitor::opt_vector_float()
355 bool progress
= false;
357 int last_reg
= -1, last_reg_offset
= -1;
358 enum register_file last_reg_file
= BAD_FILE
;
360 int remaining_channels
= 0;
363 vec4_instruction
*imm_inst
[4];
365 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
366 if (last_reg
!= inst
->dst
.reg
||
367 last_reg_offset
!= inst
->dst
.reg_offset
||
368 last_reg_file
!= inst
->dst
.file
) {
369 last_reg
= inst
->dst
.reg
;
370 last_reg_offset
= inst
->dst
.reg_offset
;
371 last_reg_file
= inst
->dst
.file
;
372 remaining_channels
= WRITEMASK_XYZW
;
377 if (inst
->opcode
!= BRW_OPCODE_MOV
||
378 inst
->dst
.writemask
== WRITEMASK_XYZW
||
379 inst
->src
[0].file
!= IMM
)
382 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
386 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
388 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
390 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
392 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
395 imm_inst
[inst_count
++] = inst
;
397 remaining_channels
&= ~inst
->dst
.writemask
;
398 if (remaining_channels
== 0) {
399 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
400 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
401 mov
->dst
.writemask
= WRITEMASK_XYZW
;
402 inst
->insert_after(block
, mov
);
405 for (int i
= 0; i
< inst_count
; i
++) {
406 imm_inst
[i
]->remove(block
);
413 invalidate_live_intervals();
418 /* Replaces unused channels of a swizzle with channels that are used.
420 * For instance, this pass transforms
422 * mov vgrf4.yz, vgrf5.wxzy
426 * mov vgrf4.yz, vgrf5.xxzx
428 * This eliminates false uses of some channels, letting dead code elimination
429 * remove the instructions that wrote them.
432 vec4_visitor::opt_reduce_swizzle()
434 bool progress
= false;
436 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
437 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
438 inst
->is_send_from_grf())
443 /* Determine which channels of the sources are read. */
444 switch (inst
->opcode
) {
445 case VEC4_OPCODE_PACK_BYTES
:
447 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
448 * but all four of src1.
450 swizzle
= brw_swizzle_for_size(4);
453 swizzle
= brw_swizzle_for_size(3);
456 swizzle
= brw_swizzle_for_size(2);
459 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
463 /* Update sources' swizzles. */
464 for (int i
= 0; i
< 3; i
++) {
465 if (inst
->src
[i
].file
!= GRF
&&
466 inst
->src
[i
].file
!= ATTR
&&
467 inst
->src
[i
].file
!= UNIFORM
)
470 const unsigned new_swizzle
=
471 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
472 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
473 inst
->src
[i
].swizzle
= new_swizzle
;
480 invalidate_live_intervals();
486 vec4_visitor::split_uniform_registers()
488 /* Prior to this, uniforms have been in an array sized according to
489 * the number of vector uniforms present, sparsely filled (so an
490 * aggregate results in reg indices being skipped over). Now we're
491 * going to cut those aggregates up so each .reg index is one
492 * vector. The goal is to make elimination of unused uniform
493 * components easier later.
495 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
496 for (int i
= 0 ; i
< 3; i
++) {
497 if (inst
->src
[i
].file
!= UNIFORM
)
500 assert(!inst
->src
[i
].reladdr
);
502 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
503 inst
->src
[i
].reg_offset
= 0;
507 /* Update that everything is now vector-sized. */
508 for (int i
= 0; i
< this->uniforms
; i
++) {
509 this->uniform_size
[i
] = 1;
514 vec4_visitor::pack_uniform_registers()
516 bool uniform_used
[this->uniforms
];
517 int new_loc
[this->uniforms
];
518 int new_chan
[this->uniforms
];
520 memset(uniform_used
, 0, sizeof(uniform_used
));
521 memset(new_loc
, 0, sizeof(new_loc
));
522 memset(new_chan
, 0, sizeof(new_chan
));
524 /* Find which uniform vectors are actually used by the program. We
525 * expect unused vector elements when we've moved array access out
526 * to pull constants, and from some GLSL code generators like wine.
528 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
529 for (int i
= 0 ; i
< 3; i
++) {
530 if (inst
->src
[i
].file
!= UNIFORM
)
533 uniform_used
[inst
->src
[i
].reg
] = true;
537 int new_uniform_count
= 0;
539 /* Now, figure out a packing of the live uniform vectors into our
542 for (int src
= 0; src
< uniforms
; src
++) {
543 assert(src
< uniform_array_size
);
544 int size
= this->uniform_vector_size
[src
];
546 if (!uniform_used
[src
]) {
547 this->uniform_vector_size
[src
] = 0;
552 /* Find the lowest place we can slot this uniform in. */
553 for (dst
= 0; dst
< src
; dst
++) {
554 if (this->uniform_vector_size
[dst
] + size
<= 4)
563 new_chan
[src
] = this->uniform_vector_size
[dst
];
565 /* Move the references to the data */
566 for (int j
= 0; j
< size
; j
++) {
567 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
568 stage_prog_data
->param
[src
* 4 + j
];
571 this->uniform_vector_size
[dst
] += size
;
572 this->uniform_vector_size
[src
] = 0;
575 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
578 this->uniforms
= new_uniform_count
;
580 /* Now, update the instructions for our repacked uniforms. */
581 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
582 for (int i
= 0 ; i
< 3; i
++) {
583 int src
= inst
->src
[i
].reg
;
585 if (inst
->src
[i
].file
!= UNIFORM
)
588 inst
->src
[i
].reg
= new_loc
[src
];
589 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
590 new_chan
[src
], new_chan
[src
]);
596 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
598 * While GLSL IR also performs this optimization, we end up with it in
599 * our instruction stream for a couple of reasons. One is that we
600 * sometimes generate silly instructions, for example in array access
601 * where we'll generate "ADD offset, index, base" even if base is 0.
602 * The other is that GLSL IR's constant propagation doesn't track the
603 * components of aggregates, so some VS patterns (initialize matrix to
604 * 0, accumulate in vertex blending factors) end up breaking down to
605 * instructions involving 0.
608 vec4_visitor::opt_algebraic()
610 bool progress
= false;
612 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
613 switch (inst
->opcode
) {
615 if (inst
->src
[0].file
!= IMM
)
618 if (inst
->saturate
) {
619 if (inst
->dst
.type
!= inst
->src
[0].type
)
620 assert(!"unimplemented: saturate mixed types");
622 if (brw_saturate_immediate(inst
->dst
.type
,
623 &inst
->src
[0].fixed_hw_reg
)) {
624 inst
->saturate
= false;
630 case VEC4_OPCODE_UNPACK_UNIFORM
:
631 if (inst
->src
[0].file
!= UNIFORM
) {
632 inst
->opcode
= BRW_OPCODE_MOV
;
638 if (inst
->src
[1].is_zero()) {
639 inst
->opcode
= BRW_OPCODE_MOV
;
640 inst
->src
[1] = src_reg();
646 if (inst
->src
[1].is_zero()) {
647 inst
->opcode
= BRW_OPCODE_MOV
;
648 switch (inst
->src
[0].type
) {
649 case BRW_REGISTER_TYPE_F
:
650 inst
->src
[0] = src_reg(0.0f
);
652 case BRW_REGISTER_TYPE_D
:
653 inst
->src
[0] = src_reg(0);
655 case BRW_REGISTER_TYPE_UD
:
656 inst
->src
[0] = src_reg(0u);
659 unreachable("not reached");
661 inst
->src
[1] = src_reg();
663 } else if (inst
->src
[1].is_one()) {
664 inst
->opcode
= BRW_OPCODE_MOV
;
665 inst
->src
[1] = src_reg();
667 } else if (inst
->src
[1].is_negative_one()) {
668 inst
->opcode
= BRW_OPCODE_MOV
;
669 inst
->src
[0].negate
= !inst
->src
[0].negate
;
670 inst
->src
[1] = src_reg();
675 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
677 inst
->src
[0].negate
&&
678 inst
->src
[1].is_zero()) {
679 inst
->src
[0].abs
= false;
680 inst
->src
[0].negate
= false;
681 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
686 case SHADER_OPCODE_RCP
: {
687 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
688 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
689 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
690 inst
->opcode
= SHADER_OPCODE_RSQ
;
691 inst
->src
[0] = prev
->src
[0];
697 case SHADER_OPCODE_BROADCAST
:
698 if (is_uniform(inst
->src
[0]) ||
699 inst
->src
[1].is_zero()) {
700 inst
->opcode
= BRW_OPCODE_MOV
;
701 inst
->src
[1] = src_reg();
702 inst
->force_writemask_all
= true;
713 invalidate_live_intervals();
719 * Only a limited number of hardware registers may be used for push
720 * constants, so this turns access to the overflowed constants into
724 vec4_visitor::move_push_constants_to_pull_constants()
726 int pull_constant_loc
[this->uniforms
];
728 /* Only allow 32 registers (256 uniform components) as push constants,
729 * which is the limit on gen6.
731 * If changing this value, note the limitation about total_regs in
734 int max_uniform_components
= 32 * 8;
735 if (this->uniforms
* 4 <= max_uniform_components
)
738 /* Make some sort of choice as to which uniforms get sent to pull
739 * constants. We could potentially do something clever here like
740 * look for the most infrequently used uniform vec4s, but leave
743 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
744 pull_constant_loc
[i
/ 4] = -1;
746 if (i
>= max_uniform_components
) {
747 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
749 /* Try to find an existing copy of this uniform in the pull
750 * constants if it was part of an array access already.
752 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
755 for (matches
= 0; matches
< 4; matches
++) {
756 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
761 pull_constant_loc
[i
/ 4] = j
/ 4;
766 if (pull_constant_loc
[i
/ 4] == -1) {
767 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
768 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
770 for (int j
= 0; j
< 4; j
++) {
771 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
778 /* Now actually rewrite usage of the things we've moved to pull
781 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
782 for (int i
= 0 ; i
< 3; i
++) {
783 if (inst
->src
[i
].file
!= UNIFORM
||
784 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
787 int uniform
= inst
->src
[i
].reg
;
789 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
791 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
792 pull_constant_loc
[uniform
]);
794 inst
->src
[i
].file
= temp
.file
;
795 inst
->src
[i
].reg
= temp
.reg
;
796 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
797 inst
->src
[i
].reladdr
= NULL
;
801 /* Repack push constants to remove the now-unused ones. */
802 pack_uniform_registers();
805 /* Conditions for which we want to avoid setting the dependency control bits */
807 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
809 #define IS_DWORD(reg) \
810 (reg.type == BRW_REGISTER_TYPE_UD || \
811 reg.type == BRW_REGISTER_TYPE_D)
813 /* "When source or destination datatype is 64b or operation is integer DWord
814 * multiply, DepCtrl must not be used."
815 * May apply to future SoCs as well.
817 if (devinfo
->is_cherryview
) {
818 if (inst
->opcode
== BRW_OPCODE_MUL
&&
819 IS_DWORD(inst
->src
[0]) &&
820 IS_DWORD(inst
->src
[1]))
825 if (devinfo
->gen
>= 8) {
826 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
832 * In the presence of send messages, totally interrupt dependency
833 * control. They're long enough that the chance of dependency
834 * control around them just doesn't matter.
837 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
838 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
839 * completes the scoreboard clear must have a non-zero execution mask. This
840 * means, if any kind of predication can change the execution mask or channel
841 * enable of the last instruction, the optimization must be avoided. This is
842 * to avoid instructions being shot down the pipeline when no writes are
846 * Dependency control does not work well over math instructions.
847 * NB: Discovered empirically
849 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
853 * Sets the dependency control fields on instructions after register
854 * allocation and before the generator is run.
856 * When you have a sequence of instructions like:
858 * DP4 temp.x vertex uniform[0]
859 * DP4 temp.y vertex uniform[0]
860 * DP4 temp.z vertex uniform[0]
861 * DP4 temp.w vertex uniform[0]
863 * The hardware doesn't know that it can actually run the later instructions
864 * while the previous ones are in flight, producing stalls. However, we have
865 * manual fields we can set in the instructions that let it do so.
868 vec4_visitor::opt_set_dependency_control()
870 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
871 uint8_t grf_channels_written
[BRW_MAX_GRF
];
872 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
873 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
875 assert(prog_data
->total_grf
||
876 !"Must be called after register allocation");
878 foreach_block (block
, cfg
) {
879 memset(last_grf_write
, 0, sizeof(last_grf_write
));
880 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
882 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
883 /* If we read from a register that we were doing dependency control
884 * on, don't do dependency control across the read.
886 for (int i
= 0; i
< 3; i
++) {
887 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
888 if (inst
->src
[i
].file
== GRF
) {
889 last_grf_write
[reg
] = NULL
;
890 } else if (inst
->src
[i
].file
== HW_REG
) {
891 memset(last_grf_write
, 0, sizeof(last_grf_write
));
894 assert(inst
->src
[i
].file
!= MRF
);
897 if (is_dep_ctrl_unsafe(inst
)) {
898 memset(last_grf_write
, 0, sizeof(last_grf_write
));
899 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
903 /* Now, see if we can do dependency control for this instruction
904 * against a previous one writing to its destination.
906 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
907 if (inst
->dst
.file
== GRF
) {
908 if (last_grf_write
[reg
] &&
909 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
910 last_grf_write
[reg
]->no_dd_clear
= true;
911 inst
->no_dd_check
= true;
913 grf_channels_written
[reg
] = 0;
916 last_grf_write
[reg
] = inst
;
917 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
918 } else if (inst
->dst
.file
== MRF
) {
919 if (last_mrf_write
[reg
] &&
920 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
921 last_mrf_write
[reg
]->no_dd_clear
= true;
922 inst
->no_dd_check
= true;
924 mrf_channels_written
[reg
] = 0;
927 last_mrf_write
[reg
] = inst
;
928 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
929 } else if (inst
->dst
.reg
== HW_REG
) {
930 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
931 memset(last_grf_write
, 0, sizeof(last_grf_write
));
932 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
933 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
940 vec4_instruction::can_reswizzle(int dst_writemask
,
944 /* If this instruction sets anything not referenced by swizzle, then we'd
945 * totally break it when we reswizzle.
947 if (dst
.writemask
& ~swizzle_mask
)
957 * For any channels in the swizzle's source that were populated by this
958 * instruction, rewrite the instruction to put the appropriate result directly
961 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
964 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
966 /* Destination write mask doesn't correspond to source swizzle for the dot
967 * product and pack_bytes instructions.
969 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
970 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
971 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
972 for (int i
= 0; i
< 3; i
++) {
973 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
976 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
980 /* Apply the specified swizzle and writemask to the original mask of
981 * written components.
983 dst
.writemask
= dst_writemask
&
984 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
988 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
989 * just written and then MOVed into another reg and making the original write
990 * of the GRF write directly to the final destination instead.
993 vec4_visitor::opt_register_coalesce()
995 bool progress
= false;
998 calculate_live_intervals();
1000 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1004 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1005 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1007 inst
->src
[0].file
!= GRF
||
1008 inst
->dst
.type
!= inst
->src
[0].type
||
1009 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1012 bool to_mrf
= (inst
->dst
.file
== MRF
);
1014 /* Can't coalesce this GRF if someone else was going to
1017 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1020 /* We need to check interference with the final destination between this
1021 * instruction and the earliest instruction involved in writing the GRF
1022 * we're eliminating. To do that, keep track of which of our source
1023 * channels we've seen initialized.
1025 const unsigned chans_needed
=
1026 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1027 inst
->dst
.writemask
);
1028 unsigned chans_remaining
= chans_needed
;
1030 /* Now walk up the instruction stream trying to see if we can rewrite
1031 * everything writing to the temporary to write into the destination
1034 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1035 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1037 _scan_inst
= scan_inst
;
1039 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1040 /* Found something writing to the reg we want to coalesce away. */
1042 /* SEND instructions can't have MRF as a destination. */
1043 if (scan_inst
->mlen
)
1046 if (devinfo
->gen
== 6) {
1047 /* gen6 math instructions must have the destination be
1048 * GRF, so no compute-to-MRF for them.
1050 if (scan_inst
->is_math()) {
1056 /* If we can't handle the swizzle, bail. */
1057 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1058 inst
->src
[0].swizzle
,
1063 /* This doesn't handle coalescing of multiple registers. */
1064 if (scan_inst
->regs_written
> 1)
1067 /* Mark which channels we found unconditional writes for. */
1068 if (!scan_inst
->predicate
)
1069 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1071 if (chans_remaining
== 0)
1075 /* You can't read from an MRF, so if someone else reads our MRF's
1076 * source GRF that we wanted to rewrite, that stops us. If it's a
1077 * GRF we're trying to coalesce to, we don't actually handle
1078 * rewriting sources so bail in that case as well.
1080 bool interfered
= false;
1081 for (int i
= 0; i
< 3; i
++) {
1082 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1083 scan_inst
->regs_read(i
)))
1089 /* If somebody else writes our destination here, we can't coalesce
1092 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
))
1095 /* Check for reads of the register we're trying to coalesce into. We
1096 * can't go rewriting instructions above that to put some other value
1097 * in the register instead.
1099 if (to_mrf
&& scan_inst
->mlen
> 0) {
1100 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1101 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1105 for (int i
= 0; i
< 3; i
++) {
1106 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1107 scan_inst
->regs_read(i
)))
1115 if (chans_remaining
== 0) {
1116 /* If we've made it here, we have an MOV we want to coalesce out, and
1117 * a scan_inst pointing to the earliest instruction involved in
1118 * computing the value. Now go rewrite the instruction stream
1121 vec4_instruction
*scan_inst
= _scan_inst
;
1122 while (scan_inst
!= inst
) {
1123 if (scan_inst
->dst
.file
== GRF
&&
1124 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1125 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1126 scan_inst
->reswizzle(inst
->dst
.writemask
,
1127 inst
->src
[0].swizzle
);
1128 scan_inst
->dst
.file
= inst
->dst
.file
;
1129 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1130 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1131 scan_inst
->saturate
|= inst
->saturate
;
1133 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1135 inst
->remove(block
);
1141 invalidate_live_intervals();
1147 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1148 * flow. We could probably do better here with some form of divergence
1152 vec4_visitor::eliminate_find_live_channel()
1154 bool progress
= false;
1157 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1158 switch (inst
->opcode
) {
1164 case BRW_OPCODE_ENDIF
:
1165 case BRW_OPCODE_WHILE
:
1169 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1171 inst
->opcode
= BRW_OPCODE_MOV
;
1172 inst
->src
[0] = src_reg(0);
1173 inst
->force_writemask_all
= true;
1187 * Splits virtual GRFs requesting more than one contiguous physical register.
1189 * We initially create large virtual GRFs for temporary structures, arrays,
1190 * and matrices, so that the dereference visitor functions can add reg_offsets
1191 * to work their way down to the actual member being accessed. But when it
1192 * comes to optimization, we'd like to treat each register as individual
1193 * storage if possible.
1195 * So far, the only thing that might prevent splitting is a send message from
1199 vec4_visitor::split_virtual_grfs()
1201 int num_vars
= this->alloc
.count
;
1202 int new_virtual_grf
[num_vars
];
1203 bool split_grf
[num_vars
];
1205 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1207 /* Try to split anything > 0 sized. */
1208 for (int i
= 0; i
< num_vars
; i
++) {
1209 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1212 /* Check that the instructions are compatible with the registers we're trying
1215 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1216 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1217 split_grf
[inst
->dst
.reg
] = false;
1219 for (int i
= 0; i
< 3; i
++) {
1220 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1221 split_grf
[inst
->src
[i
].reg
] = false;
1225 /* Allocate new space for split regs. Note that the virtual
1226 * numbers will be contiguous.
1228 for (int i
= 0; i
< num_vars
; i
++) {
1232 new_virtual_grf
[i
] = alloc
.allocate(1);
1233 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1234 unsigned reg
= alloc
.allocate(1);
1235 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1238 this->alloc
.sizes
[i
] = 1;
1241 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1242 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1243 inst
->dst
.reg_offset
!= 0) {
1244 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1245 inst
->dst
.reg_offset
- 1);
1246 inst
->dst
.reg_offset
= 0;
1248 for (int i
= 0; i
< 3; i
++) {
1249 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1250 inst
->src
[i
].reg_offset
!= 0) {
1251 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1252 inst
->src
[i
].reg_offset
- 1);
1253 inst
->src
[i
].reg_offset
= 0;
1257 invalidate_live_intervals();
1261 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1263 dump_instruction(be_inst
, stderr
);
1267 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1269 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1271 if (inst
->predicate
) {
1272 fprintf(file
, "(%cf0.%d) ",
1273 inst
->predicate_inverse
? '-' : '+',
1277 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1279 fprintf(file
, ".sat");
1280 if (inst
->conditional_mod
) {
1281 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1282 if (!inst
->predicate
&&
1283 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1284 inst
->opcode
!= BRW_OPCODE_IF
&&
1285 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1286 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1291 switch (inst
->dst
.file
) {
1293 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1296 fprintf(file
, "m%d", inst
->dst
.reg
);
1299 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1300 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1302 fprintf(file
, "null");
1304 case BRW_ARF_ADDRESS
:
1305 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1307 case BRW_ARF_ACCUMULATOR
:
1308 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1311 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1312 inst
->dst
.fixed_hw_reg
.subnr
);
1315 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1316 inst
->dst
.fixed_hw_reg
.subnr
);
1320 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1322 if (inst
->dst
.fixed_hw_reg
.subnr
)
1323 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1326 fprintf(file
, "(null)");
1329 fprintf(file
, "???");
1332 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1334 if (inst
->dst
.writemask
& 1)
1336 if (inst
->dst
.writemask
& 2)
1338 if (inst
->dst
.writemask
& 4)
1340 if (inst
->dst
.writemask
& 8)
1343 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1345 if (inst
->src
[0].file
!= BAD_FILE
)
1346 fprintf(file
, ", ");
1348 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1349 if (inst
->src
[i
].negate
)
1351 if (inst
->src
[i
].abs
)
1353 switch (inst
->src
[i
].file
) {
1355 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1358 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1361 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1364 switch (inst
->src
[i
].type
) {
1365 case BRW_REGISTER_TYPE_F
:
1366 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1368 case BRW_REGISTER_TYPE_D
:
1369 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1371 case BRW_REGISTER_TYPE_UD
:
1372 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1374 case BRW_REGISTER_TYPE_VF
:
1375 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1376 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1377 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1378 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1379 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1382 fprintf(file
, "???");
1387 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1389 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1391 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1392 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1394 fprintf(file
, "null");
1396 case BRW_ARF_ADDRESS
:
1397 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1399 case BRW_ARF_ACCUMULATOR
:
1400 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1403 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1404 inst
->src
[i
].fixed_hw_reg
.subnr
);
1407 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1408 inst
->src
[i
].fixed_hw_reg
.subnr
);
1412 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1414 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1415 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1416 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1420 fprintf(file
, "(null)");
1423 fprintf(file
, "???");
1427 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1428 if (inst
->src
[i
].reg_offset
!= 0 &&
1429 inst
->src
[i
].file
== GRF
&&
1430 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1431 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1433 if (inst
->src
[i
].file
!= IMM
) {
1434 static const char *chans
[4] = {"x", "y", "z", "w"};
1436 for (int c
= 0; c
< 4; c
++) {
1437 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1441 if (inst
->src
[i
].abs
)
1444 if (inst
->src
[i
].file
!= IMM
) {
1445 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1448 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1449 fprintf(file
, ", ");
1452 fprintf(file
, "\n");
1456 static inline struct brw_reg
1457 attribute_to_hw_reg(int attr
, bool interleaved
)
1460 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1462 return brw_vec8_grf(attr
, 0);
1467 * Replace each register of type ATTR in this->instructions with a reference
1468 * to a fixed HW register.
1470 * If interleaved is true, then each attribute takes up half a register, with
1471 * register N containing attribute 2*N in its first half and attribute 2*N+1
1472 * in its second half (this corresponds to the payload setup used by geometry
1473 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1474 * false, then each attribute takes up a whole register, with register N
1475 * containing attribute N (this corresponds to the payload setup used by
1476 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1479 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1482 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1483 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1484 if (inst
->dst
.file
== ATTR
) {
1485 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1487 /* All attributes used in the shader need to have been assigned a
1488 * hardware register by the caller
1492 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1493 reg
.type
= inst
->dst
.type
;
1494 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1496 inst
->dst
.file
= HW_REG
;
1497 inst
->dst
.fixed_hw_reg
= reg
;
1500 for (int i
= 0; i
< 3; i
++) {
1501 if (inst
->src
[i
].file
!= ATTR
)
1504 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1506 /* All attributes used in the shader need to have been assigned a
1507 * hardware register by the caller
1511 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1512 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1513 reg
.type
= inst
->src
[i
].type
;
1514 if (inst
->src
[i
].abs
)
1516 if (inst
->src
[i
].negate
)
1519 inst
->src
[i
].file
= HW_REG
;
1520 inst
->src
[i
].fixed_hw_reg
= reg
;
1526 vec4_vs_visitor::setup_attributes(int payload_reg
)
1529 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1530 memset(attribute_map
, 0, sizeof(attribute_map
));
1533 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1534 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1535 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1540 /* VertexID is stored by the VF as the last vertex element, but we
1541 * don't represent it with a flag in inputs_read, so we call it
1544 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1545 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1549 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1551 /* The BSpec says we always have to read at least one thing from
1552 * the VF, and it appears that the hardware wedges otherwise.
1554 if (nr_attributes
== 0)
1557 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1559 unsigned vue_entries
=
1560 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1562 if (devinfo
->gen
== 6)
1563 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1565 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1567 return payload_reg
+ nr_attributes
;
1571 vec4_visitor::setup_uniforms(int reg
)
1573 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1575 /* The pre-gen6 VS requires that some push constants get loaded no
1576 * matter what, or the GPU would hang.
1578 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1579 assert(this->uniforms
< this->uniform_array_size
);
1580 this->uniform_vector_size
[this->uniforms
] = 1;
1582 stage_prog_data
->param
=
1583 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1584 for (unsigned int i
= 0; i
< 4; i
++) {
1585 unsigned int slot
= this->uniforms
* 4 + i
;
1586 static gl_constant_value zero
= { 0.0 };
1587 stage_prog_data
->param
[slot
] = &zero
;
1593 reg
+= ALIGN(uniforms
, 2) / 2;
1596 stage_prog_data
->nr_params
= this->uniforms
* 4;
1598 prog_data
->base
.curb_read_length
=
1599 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1605 vec4_vs_visitor::setup_payload(void)
1609 /* The payload always contains important data in g0, which contains
1610 * the URB handles that are passed on to the URB write at the end
1611 * of the thread. So, we always start push constants at g1.
1615 reg
= setup_uniforms(reg
);
1617 reg
= setup_attributes(reg
);
1619 this->first_non_payload_grf
= reg
;
1623 vec4_visitor::assign_binding_table_offsets()
1625 assign_common_binding_table_offsets(0);
1629 vec4_visitor::get_timestamp()
1631 assert(devinfo
->gen
>= 7);
1633 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1638 BRW_REGISTER_TYPE_UD
,
1639 BRW_VERTICAL_STRIDE_0
,
1641 BRW_HORIZONTAL_STRIDE_4
,
1645 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1647 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1648 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1649 * even if it's not enabled in the dispatch.
1651 mov
->force_writemask_all
= true;
1653 return src_reg(dst
);
1657 vec4_visitor::emit_shader_time_begin()
1659 current_annotation
= "shader time start";
1660 shader_start_time
= get_timestamp();
1664 vec4_visitor::emit_shader_time_end()
1666 current_annotation
= "shader time end";
1667 src_reg shader_end_time
= get_timestamp();
1670 /* Check that there weren't any timestamp reset events (assuming these
1671 * were the only two timestamp reads that happened).
1673 src_reg reset_end
= shader_end_time
;
1674 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1675 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1676 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1678 emit(IF(BRW_PREDICATE_NORMAL
));
1680 /* Take the current timestamp and get the delta. */
1681 shader_start_time
.negate
= true;
1682 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1683 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1685 /* If there were no instructions between the two timestamp gets, the diff
1686 * is 2 cycles. Remove that overhead, so I can forget about that when
1687 * trying to determine the time taken for single instructions.
1689 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1691 emit_shader_time_write(0, src_reg(diff
));
1692 emit_shader_time_write(1, src_reg(1u));
1693 emit(BRW_OPCODE_ELSE
);
1694 emit_shader_time_write(2, src_reg(1u));
1695 emit(BRW_OPCODE_ENDIF
);
1699 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1702 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1704 dst_reg offset
= dst
;
1708 offset
.type
= BRW_REGISTER_TYPE_UD
;
1709 int index
= shader_time_index
* 3 + shader_time_subindex
;
1710 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1712 time
.type
= BRW_REGISTER_TYPE_UD
;
1713 emit(MOV(time
, src_reg(value
)));
1715 vec4_instruction
*inst
=
1716 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1721 vec4_visitor::run(gl_clip_plane
*clip_planes
)
1724 compiler
->glsl_compiler_options
[stage
].NirOptions
!= NULL
;
1726 sanity_param_count
= prog
->Parameters
->NumParameters
;
1728 if (shader_time_index
>= 0)
1729 emit_shader_time_begin();
1731 assign_binding_table_offsets();
1737 assert(prog
->nir
!= NULL
);
1742 /* Generate VS IR for main(). (the visitor only descends into
1743 * functions called "main").
1745 visit_instructions(shader
->base
.ir
);
1748 emit_program_code();
1752 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1753 setup_uniform_clipplane_values(clip_planes
);
1759 /* Before any optimization, push array accesses out to scratch
1760 * space where we need them to be. This pass may allocate new
1761 * virtual GRFs, so we want to do it early. It also makes sure
1762 * that we have reladdr computations available for CSE, since we'll
1763 * often do repeated subexpressions for those.
1766 move_grf_array_access_to_scratch();
1767 move_uniform_array_access_to_pull_constants();
1769 /* The ARB_vertex_program frontend emits pull constant loads directly
1770 * rather than using reladdr, so we don't need to walk through all the
1771 * instructions looking for things to move. There isn't anything.
1773 * We do still need to split things to vec4 size.
1775 split_uniform_registers();
1777 pack_uniform_registers();
1778 move_push_constants_to_pull_constants();
1779 split_virtual_grfs();
1781 #define OPT(pass, args...) ({ \
1783 bool this_progress = pass(args); \
1785 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1786 char filename[64]; \
1787 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1788 stage_abbrev, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1790 backend_shader::dump_instructions(filename); \
1793 progress = progress || this_progress; \
1798 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1800 snprintf(filename
, 64, "%s-%04d-00-start",
1801 stage_abbrev
, shader_prog
? shader_prog
->Name
: 0);
1803 backend_shader::dump_instructions(filename
);
1814 OPT(opt_reduce_swizzle
);
1815 OPT(dead_code_eliminate
);
1816 OPT(dead_control_flow_eliminate
, this);
1817 OPT(opt_copy_propagation
);
1820 OPT(opt_register_coalesce
);
1821 OPT(eliminate_find_live_channel
);
1826 if (OPT(opt_vector_float
)) {
1828 OPT(opt_copy_propagation
, false);
1829 OPT(opt_copy_propagation
, true);
1830 OPT(dead_code_eliminate
);
1839 /* Debug of register spilling: Go spill everything. */
1840 const int grf_count
= alloc
.count
;
1841 float spill_costs
[alloc
.count
];
1842 bool no_spill
[alloc
.count
];
1843 evaluate_spill_costs(spill_costs
, no_spill
);
1844 for (int i
= 0; i
< grf_count
; i
++) {
1851 bool allocated_without_spills
= reg_allocate();
1853 if (!allocated_without_spills
) {
1854 compiler
->shader_perf_log(log_data
,
1855 "%s shader triggered register spilling. "
1856 "Try reducing the number of live vec4 values "
1857 "to improve performance.\n",
1860 while (!reg_allocate()) {
1866 opt_schedule_instructions();
1868 opt_set_dependency_control();
1870 if (last_scratch
> 0) {
1871 prog_data
->base
.total_scratch
=
1872 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1875 /* If any state parameters were appended, then ParameterValues could have
1876 * been realloced, in which case the driver uniform storage set up by
1877 * _mesa_associate_uniform_storage() would point to freed memory. Make
1878 * sure that didn't happen.
1880 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1885 } /* namespace brw */
1890 * Compile a vertex shader.
1892 * Returns the final assembly and the program's size.
1895 brw_vs_emit(struct brw_context
*brw
,
1897 const struct brw_vs_prog_key
*key
,
1898 struct brw_vs_prog_data
*prog_data
,
1899 struct gl_vertex_program
*vp
,
1900 struct gl_shader_program
*prog
,
1901 unsigned *final_assembly_size
)
1903 bool start_busy
= false;
1904 double start_time
= 0;
1905 const unsigned *assembly
= NULL
;
1907 if (unlikely(brw
->perf_debug
)) {
1908 start_busy
= (brw
->batch
.last_bo
&&
1909 drm_intel_bo_busy(brw
->batch
.last_bo
));
1910 start_time
= get_time();
1913 struct brw_shader
*shader
= NULL
;
1915 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1918 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1919 st_index
= brw_get_shader_time_index(brw
, prog
, &vp
->Base
, ST_VS
);
1921 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1922 brw_dump_ir("vertex", prog
, &shader
->base
, &vp
->Base
);
1924 if (brw
->intelScreen
->compiler
->scalar_vs
) {
1925 if (!vp
->Base
.nir
) {
1926 /* Normally we generate NIR in LinkShader() or
1927 * ProgramStringNotify(), but Mesa's fixed-function vertex program
1928 * handling doesn't notify the driver at all. Just do it here, at
1929 * the last minute, even though it's lame.
1931 assert(vp
->Base
.Id
== 0 && prog
== NULL
);
1933 brw_create_nir(brw
, NULL
, &vp
->Base
, MESA_SHADER_VERTEX
, true);
1936 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1938 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
1939 mem_ctx
, MESA_SHADER_VERTEX
, key
,
1940 &prog_data
->base
.base
, prog
, &vp
->Base
,
1942 if (!v
.run_vs(brw_select_clip_planes(&brw
->ctx
))) {
1944 prog
->LinkStatus
= false;
1945 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1948 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1954 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
1955 mem_ctx
, (void *) key
, &prog_data
->base
.base
,
1956 &vp
->Base
, v
.promoted_constants
,
1957 v
.runtime_check_aads_emit
, "VS");
1958 if (INTEL_DEBUG
& DEBUG_VS
) {
1961 name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1962 prog
->Label
? prog
->Label
: "unnamed",
1965 name
= ralloc_asprintf(mem_ctx
, "vertex program %d",
1968 g
.enable_debug(name
);
1970 g
.generate_code(v
.cfg
, 8);
1971 assembly
= g
.get_assembly(final_assembly_size
);
1975 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
1977 vec4_vs_visitor
v(brw
->intelScreen
->compiler
, brw
, key
, prog_data
,
1978 vp
, prog
, mem_ctx
, st_index
,
1979 !_mesa_is_gles3(&brw
->ctx
));
1980 if (!v
.run(brw_select_clip_planes(&brw
->ctx
))) {
1982 prog
->LinkStatus
= false;
1983 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1986 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1992 vec4_generator
g(brw
->intelScreen
->compiler
, brw
,
1993 prog
, &vp
->Base
, &prog_data
->base
,
1994 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
1995 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1998 if (unlikely(brw
->perf_debug
) && shader
) {
1999 if (shader
->compiled_once
) {
2000 brw_vs_debug_recompile(brw
, prog
, key
);
2002 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
2003 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
2004 (get_time() - start_time
) * 1000);
2006 shader
->compiled_once
= true;
2014 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
2015 struct brw_vue_prog_key
*key
,
2016 GLuint id
, struct gl_program
*prog
)
2018 struct brw_context
*brw
= brw_context(ctx
);
2019 key
->program_string_id
= id
;
2021 brw_setup_tex_for_precompile(brw
, &key
->tex
, prog
);