2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(float f
)
79 this->type
= BRW_REGISTER_TYPE_F
;
83 src_reg::src_reg(uint32_t u
)
88 this->type
= BRW_REGISTER_TYPE_UD
;
92 src_reg::src_reg(int32_t i
)
97 this->type
= BRW_REGISTER_TYPE_D
;
101 src_reg::src_reg(uint8_t vf
[4])
106 this->type
= BRW_REGISTER_TYPE_VF
;
107 memcpy(&this->ud
, vf
, sizeof(unsigned));
110 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
115 this->type
= BRW_REGISTER_TYPE_VF
;
116 this->ud
= (vf0
<< 0) | (vf1
<< 8) | (vf2
<< 16) | (vf3
<< 24);
119 src_reg::src_reg(struct brw_reg reg
) :
122 this->reg_offset
= 0;
123 this->reladdr
= NULL
;
126 src_reg::src_reg(const dst_reg
®
) :
127 backend_reg(static_cast<struct brw_reg
>(reg
))
129 this->reg_offset
= reg
.reg_offset
;
130 this->reladdr
= reg
.reladdr
;
131 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
137 memset(this, 0, sizeof(*this));
138 this->file
= BAD_FILE
;
139 this->writemask
= WRITEMASK_XYZW
;
147 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
155 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
162 this->type
= brw_type_for_base_type(type
);
163 this->writemask
= writemask
;
166 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
174 this->writemask
= writemask
;
177 dst_reg::dst_reg(struct brw_reg reg
) :
180 this->reg_offset
= 0;
181 this->reladdr
= NULL
;
184 dst_reg::dst_reg(const src_reg
®
) :
185 backend_reg(static_cast<struct brw_reg
>(reg
))
187 this->reg_offset
= reg
.reg_offset
;
188 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
189 this->reladdr
= reg
.reladdr
;
193 dst_reg::equals(const dst_reg
&r
) const
195 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
196 reg_offset
== r
.reg_offset
&&
197 (reladdr
== r
.reladdr
||
198 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
202 vec4_instruction::is_send_from_grf()
205 case SHADER_OPCODE_SHADER_TIME_ADD
:
206 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
207 case SHADER_OPCODE_UNTYPED_ATOMIC
:
208 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
209 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
210 case SHADER_OPCODE_TYPED_ATOMIC
:
211 case SHADER_OPCODE_TYPED_SURFACE_READ
:
212 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
220 vec4_instruction::regs_read(unsigned arg
) const
222 if (src
[arg
].file
== BAD_FILE
)
226 case SHADER_OPCODE_SHADER_TIME_ADD
:
227 case SHADER_OPCODE_UNTYPED_ATOMIC
:
228 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
229 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
230 case SHADER_OPCODE_TYPED_ATOMIC
:
231 case SHADER_OPCODE_TYPED_SURFACE_READ
:
232 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
233 return arg
== 0 ? mlen
: 1;
235 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
236 return arg
== 1 ? mlen
: 1;
244 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
246 if (devinfo
->gen
== 6 && is_math())
249 if (is_send_from_grf())
252 if (!backend_instruction::can_do_source_mods())
259 vec4_instruction::can_change_types() const
261 return dst
.type
== src
[0].type
&&
262 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
263 (opcode
== BRW_OPCODE_MOV
||
264 (opcode
== BRW_OPCODE_SEL
&&
265 dst
.type
== src
[1].type
&&
266 predicate
!= BRW_PREDICATE_NONE
&&
267 !src
[1].abs
&& !src
[1].negate
));
271 * Returns how many MRFs an opcode will write over.
273 * Note that this is not the 0 or 1 implied writes in an actual gen
274 * instruction -- the generate_* functions generate additional MOVs
278 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
280 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
283 switch (inst
->opcode
) {
284 case SHADER_OPCODE_RCP
:
285 case SHADER_OPCODE_RSQ
:
286 case SHADER_OPCODE_SQRT
:
287 case SHADER_OPCODE_EXP2
:
288 case SHADER_OPCODE_LOG2
:
289 case SHADER_OPCODE_SIN
:
290 case SHADER_OPCODE_COS
:
292 case SHADER_OPCODE_INT_QUOTIENT
:
293 case SHADER_OPCODE_INT_REMAINDER
:
294 case SHADER_OPCODE_POW
:
296 case VS_OPCODE_URB_WRITE
:
298 case VS_OPCODE_PULL_CONSTANT_LOAD
:
300 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
302 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
304 case GS_OPCODE_URB_WRITE
:
305 case GS_OPCODE_URB_WRITE_ALLOCATE
:
306 case GS_OPCODE_THREAD_END
:
308 case GS_OPCODE_FF_SYNC
:
310 case SHADER_OPCODE_SHADER_TIME_ADD
:
312 case SHADER_OPCODE_TEX
:
313 case SHADER_OPCODE_TXL
:
314 case SHADER_OPCODE_TXD
:
315 case SHADER_OPCODE_TXF
:
316 case SHADER_OPCODE_TXF_CMS
:
317 case SHADER_OPCODE_TXF_CMS_W
:
318 case SHADER_OPCODE_TXF_MCS
:
319 case SHADER_OPCODE_TXS
:
320 case SHADER_OPCODE_TG4
:
321 case SHADER_OPCODE_TG4_OFFSET
:
322 case SHADER_OPCODE_SAMPLEINFO
:
323 case VS_OPCODE_GET_BUFFER_SIZE
:
324 return inst
->header_size
;
326 unreachable("not reached");
331 src_reg::equals(const src_reg
&r
) const
333 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
334 reg_offset
== r
.reg_offset
&&
335 !reladdr
&& !r
.reladdr
);
339 vec4_visitor::opt_vector_float()
341 bool progress
= false;
343 int last_reg
= -1, last_reg_offset
= -1;
344 enum brw_reg_file last_reg_file
= BAD_FILE
;
346 int remaining_channels
= 0;
349 vec4_instruction
*imm_inst
[4];
351 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
352 if (last_reg
!= inst
->dst
.nr
||
353 last_reg_offset
!= inst
->dst
.reg_offset
||
354 last_reg_file
!= inst
->dst
.file
) {
355 last_reg
= inst
->dst
.nr
;
356 last_reg_offset
= inst
->dst
.reg_offset
;
357 last_reg_file
= inst
->dst
.file
;
358 remaining_channels
= WRITEMASK_XYZW
;
363 if (inst
->opcode
!= BRW_OPCODE_MOV
||
364 inst
->dst
.writemask
== WRITEMASK_XYZW
||
365 inst
->src
[0].file
!= IMM
)
368 int vf
= brw_float_to_vf(inst
->src
[0].f
);
372 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
374 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
376 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
378 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
381 imm_inst
[inst_count
++] = inst
;
383 remaining_channels
&= ~inst
->dst
.writemask
;
384 if (remaining_channels
== 0) {
385 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
386 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
387 mov
->dst
.writemask
= WRITEMASK_XYZW
;
388 inst
->insert_after(block
, mov
);
391 for (int i
= 0; i
< inst_count
; i
++) {
392 imm_inst
[i
]->remove(block
);
399 invalidate_live_intervals();
404 /* Replaces unused channels of a swizzle with channels that are used.
406 * For instance, this pass transforms
408 * mov vgrf4.yz, vgrf5.wxzy
412 * mov vgrf4.yz, vgrf5.xxzx
414 * This eliminates false uses of some channels, letting dead code elimination
415 * remove the instructions that wrote them.
418 vec4_visitor::opt_reduce_swizzle()
420 bool progress
= false;
422 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
423 if (inst
->dst
.file
== BAD_FILE
||
424 inst
->dst
.file
== ARF
||
425 inst
->dst
.file
== FIXED_GRF
||
426 inst
->is_send_from_grf())
431 /* Determine which channels of the sources are read. */
432 switch (inst
->opcode
) {
433 case VEC4_OPCODE_PACK_BYTES
:
435 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
436 * but all four of src1.
438 swizzle
= brw_swizzle_for_size(4);
441 swizzle
= brw_swizzle_for_size(3);
444 swizzle
= brw_swizzle_for_size(2);
447 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
451 /* Update sources' swizzles. */
452 for (int i
= 0; i
< 3; i
++) {
453 if (inst
->src
[i
].file
!= VGRF
&&
454 inst
->src
[i
].file
!= ATTR
&&
455 inst
->src
[i
].file
!= UNIFORM
)
458 const unsigned new_swizzle
=
459 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
460 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
461 inst
->src
[i
].swizzle
= new_swizzle
;
468 invalidate_live_intervals();
474 vec4_visitor::split_uniform_registers()
476 /* Prior to this, uniforms have been in an array sized according to
477 * the number of vector uniforms present, sparsely filled (so an
478 * aggregate results in reg indices being skipped over). Now we're
479 * going to cut those aggregates up so each .nr index is one
480 * vector. The goal is to make elimination of unused uniform
481 * components easier later.
483 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
484 for (int i
= 0 ; i
< 3; i
++) {
485 if (inst
->src
[i
].file
!= UNIFORM
)
488 assert(!inst
->src
[i
].reladdr
);
490 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
491 inst
->src
[i
].reg_offset
= 0;
495 /* Update that everything is now vector-sized. */
496 for (int i
= 0; i
< this->uniforms
; i
++) {
497 this->uniform_size
[i
] = 1;
502 vec4_visitor::pack_uniform_registers()
504 uint8_t chans_used
[this->uniforms
];
505 int new_loc
[this->uniforms
];
506 int new_chan
[this->uniforms
];
508 memset(chans_used
, 0, sizeof(chans_used
));
509 memset(new_loc
, 0, sizeof(new_loc
));
510 memset(new_chan
, 0, sizeof(new_chan
));
512 /* Find which uniform vectors are actually used by the program. We
513 * expect unused vector elements when we've moved array access out
514 * to pull constants, and from some GLSL code generators like wine.
516 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
518 switch (inst
->opcode
) {
519 case VEC4_OPCODE_PACK_BYTES
:
531 readmask
= inst
->dst
.writemask
;
535 for (int i
= 0 ; i
< 3; i
++) {
536 if (inst
->src
[i
].file
!= UNIFORM
)
539 int reg
= inst
->src
[i
].nr
;
540 for (int c
= 0; c
< 4; c
++) {
541 if (!(readmask
& (1 << c
)))
544 chans_used
[reg
] = MAX2(chans_used
[reg
],
545 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
550 int new_uniform_count
= 0;
552 /* Now, figure out a packing of the live uniform vectors into our
555 for (int src
= 0; src
< uniforms
; src
++) {
556 assert(src
< uniform_array_size
);
557 int size
= chans_used
[src
];
563 /* Find the lowest place we can slot this uniform in. */
564 for (dst
= 0; dst
< src
; dst
++) {
565 if (chans_used
[dst
] + size
<= 4)
574 new_chan
[src
] = chans_used
[dst
];
576 /* Move the references to the data */
577 for (int j
= 0; j
< size
; j
++) {
578 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
579 stage_prog_data
->param
[src
* 4 + j
];
582 chans_used
[dst
] += size
;
586 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
589 this->uniforms
= new_uniform_count
;
591 /* Now, update the instructions for our repacked uniforms. */
592 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
593 for (int i
= 0 ; i
< 3; i
++) {
594 int src
= inst
->src
[i
].nr
;
596 if (inst
->src
[i
].file
!= UNIFORM
)
599 inst
->src
[i
].nr
= new_loc
[src
];
600 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
601 new_chan
[src
], new_chan
[src
]);
607 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
609 * While GLSL IR also performs this optimization, we end up with it in
610 * our instruction stream for a couple of reasons. One is that we
611 * sometimes generate silly instructions, for example in array access
612 * where we'll generate "ADD offset, index, base" even if base is 0.
613 * The other is that GLSL IR's constant propagation doesn't track the
614 * components of aggregates, so some VS patterns (initialize matrix to
615 * 0, accumulate in vertex blending factors) end up breaking down to
616 * instructions involving 0.
619 vec4_visitor::opt_algebraic()
621 bool progress
= false;
623 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
624 switch (inst
->opcode
) {
626 if (inst
->src
[0].file
!= IMM
)
629 if (inst
->saturate
) {
630 if (inst
->dst
.type
!= inst
->src
[0].type
)
631 assert(!"unimplemented: saturate mixed types");
633 if (brw_saturate_immediate(inst
->dst
.type
, &inst
->src
[0])) {
634 inst
->saturate
= false;
640 case VEC4_OPCODE_UNPACK_UNIFORM
:
641 if (inst
->src
[0].file
!= UNIFORM
) {
642 inst
->opcode
= BRW_OPCODE_MOV
;
648 if (inst
->src
[1].is_zero()) {
649 inst
->opcode
= BRW_OPCODE_MOV
;
650 inst
->src
[1] = src_reg();
656 if (inst
->src
[1].is_zero()) {
657 inst
->opcode
= BRW_OPCODE_MOV
;
658 switch (inst
->src
[0].type
) {
659 case BRW_REGISTER_TYPE_F
:
660 inst
->src
[0] = src_reg(0.0f
);
662 case BRW_REGISTER_TYPE_D
:
663 inst
->src
[0] = src_reg(0);
665 case BRW_REGISTER_TYPE_UD
:
666 inst
->src
[0] = src_reg(0u);
669 unreachable("not reached");
671 inst
->src
[1] = src_reg();
673 } else if (inst
->src
[1].is_one()) {
674 inst
->opcode
= BRW_OPCODE_MOV
;
675 inst
->src
[1] = src_reg();
677 } else if (inst
->src
[1].is_negative_one()) {
678 inst
->opcode
= BRW_OPCODE_MOV
;
679 inst
->src
[0].negate
= !inst
->src
[0].negate
;
680 inst
->src
[1] = src_reg();
685 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
687 inst
->src
[0].negate
&&
688 inst
->src
[1].is_zero()) {
689 inst
->src
[0].abs
= false;
690 inst
->src
[0].negate
= false;
691 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
696 case SHADER_OPCODE_RCP
: {
697 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
698 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
699 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
700 inst
->opcode
= SHADER_OPCODE_RSQ
;
701 inst
->src
[0] = prev
->src
[0];
707 case SHADER_OPCODE_BROADCAST
:
708 if (is_uniform(inst
->src
[0]) ||
709 inst
->src
[1].is_zero()) {
710 inst
->opcode
= BRW_OPCODE_MOV
;
711 inst
->src
[1] = src_reg();
712 inst
->force_writemask_all
= true;
723 invalidate_live_intervals();
729 * Only a limited number of hardware registers may be used for push
730 * constants, so this turns access to the overflowed constants into
734 vec4_visitor::move_push_constants_to_pull_constants()
736 int pull_constant_loc
[this->uniforms
];
738 /* Only allow 32 registers (256 uniform components) as push constants,
739 * which is the limit on gen6.
741 * If changing this value, note the limitation about total_regs in
744 int max_uniform_components
= 32 * 8;
745 if (this->uniforms
* 4 <= max_uniform_components
)
748 /* Make some sort of choice as to which uniforms get sent to pull
749 * constants. We could potentially do something clever here like
750 * look for the most infrequently used uniform vec4s, but leave
753 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
754 pull_constant_loc
[i
/ 4] = -1;
756 if (i
>= max_uniform_components
) {
757 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
759 /* Try to find an existing copy of this uniform in the pull
760 * constants if it was part of an array access already.
762 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
765 for (matches
= 0; matches
< 4; matches
++) {
766 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
771 pull_constant_loc
[i
/ 4] = j
/ 4;
776 if (pull_constant_loc
[i
/ 4] == -1) {
777 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
778 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
780 for (int j
= 0; j
< 4; j
++) {
781 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
788 /* Now actually rewrite usage of the things we've moved to pull
791 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
792 for (int i
= 0 ; i
< 3; i
++) {
793 if (inst
->src
[i
].file
!= UNIFORM
||
794 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
797 int uniform
= inst
->src
[i
].nr
;
799 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
801 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
802 pull_constant_loc
[uniform
]);
804 inst
->src
[i
].file
= temp
.file
;
805 inst
->src
[i
].nr
= temp
.nr
;
806 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
807 inst
->src
[i
].reladdr
= NULL
;
811 /* Repack push constants to remove the now-unused ones. */
812 pack_uniform_registers();
815 /* Conditions for which we want to avoid setting the dependency control bits */
817 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
819 #define IS_DWORD(reg) \
820 (reg.type == BRW_REGISTER_TYPE_UD || \
821 reg.type == BRW_REGISTER_TYPE_D)
823 /* "When source or destination datatype is 64b or operation is integer DWord
824 * multiply, DepCtrl must not be used."
825 * May apply to future SoCs as well.
827 if (devinfo
->is_cherryview
) {
828 if (inst
->opcode
== BRW_OPCODE_MUL
&&
829 IS_DWORD(inst
->src
[0]) &&
830 IS_DWORD(inst
->src
[1]))
835 if (devinfo
->gen
>= 8) {
836 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
842 * In the presence of send messages, totally interrupt dependency
843 * control. They're long enough that the chance of dependency
844 * control around them just doesn't matter.
847 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
848 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
849 * completes the scoreboard clear must have a non-zero execution mask. This
850 * means, if any kind of predication can change the execution mask or channel
851 * enable of the last instruction, the optimization must be avoided. This is
852 * to avoid instructions being shot down the pipeline when no writes are
856 * Dependency control does not work well over math instructions.
857 * NB: Discovered empirically
859 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
863 * Sets the dependency control fields on instructions after register
864 * allocation and before the generator is run.
866 * When you have a sequence of instructions like:
868 * DP4 temp.x vertex uniform[0]
869 * DP4 temp.y vertex uniform[0]
870 * DP4 temp.z vertex uniform[0]
871 * DP4 temp.w vertex uniform[0]
873 * The hardware doesn't know that it can actually run the later instructions
874 * while the previous ones are in flight, producing stalls. However, we have
875 * manual fields we can set in the instructions that let it do so.
878 vec4_visitor::opt_set_dependency_control()
880 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
881 uint8_t grf_channels_written
[BRW_MAX_GRF
];
882 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
883 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
885 assert(prog_data
->total_grf
||
886 !"Must be called after register allocation");
888 foreach_block (block
, cfg
) {
889 memset(last_grf_write
, 0, sizeof(last_grf_write
));
890 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
892 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
893 /* If we read from a register that we were doing dependency control
894 * on, don't do dependency control across the read.
896 for (int i
= 0; i
< 3; i
++) {
897 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
898 if (inst
->src
[i
].file
== VGRF
) {
899 last_grf_write
[reg
] = NULL
;
900 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
901 memset(last_grf_write
, 0, sizeof(last_grf_write
));
904 assert(inst
->src
[i
].file
!= MRF
);
907 if (is_dep_ctrl_unsafe(inst
)) {
908 memset(last_grf_write
, 0, sizeof(last_grf_write
));
909 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
913 /* Now, see if we can do dependency control for this instruction
914 * against a previous one writing to its destination.
916 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
917 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
918 if (last_grf_write
[reg
] &&
919 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
920 last_grf_write
[reg
]->no_dd_clear
= true;
921 inst
->no_dd_check
= true;
923 grf_channels_written
[reg
] = 0;
926 last_grf_write
[reg
] = inst
;
927 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
928 } else if (inst
->dst
.file
== MRF
) {
929 if (last_mrf_write
[reg
] &&
930 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
931 last_mrf_write
[reg
]->no_dd_clear
= true;
932 inst
->no_dd_check
= true;
934 mrf_channels_written
[reg
] = 0;
937 last_mrf_write
[reg
] = inst
;
938 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
945 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
950 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
951 * or writemasking are not allowed.
953 if (devinfo
->gen
== 6 && is_math() &&
954 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
957 /* If this instruction sets anything not referenced by swizzle, then we'd
958 * totally break it when we reswizzle.
960 if (dst
.writemask
& ~swizzle_mask
)
966 for (int i
= 0; i
< 3; i
++) {
967 if (src
[i
].is_accumulator())
975 * For any channels in the swizzle's source that were populated by this
976 * instruction, rewrite the instruction to put the appropriate result directly
979 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
982 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
984 /* Destination write mask doesn't correspond to source swizzle for the dot
985 * product and pack_bytes instructions.
987 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
988 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
989 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
990 for (int i
= 0; i
< 3; i
++) {
991 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
994 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
998 /* Apply the specified swizzle and writemask to the original mask of
999 * written components.
1001 dst
.writemask
= dst_writemask
&
1002 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1006 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1007 * just written and then MOVed into another reg and making the original write
1008 * of the GRF write directly to the final destination instead.
1011 vec4_visitor::opt_register_coalesce()
1013 bool progress
= false;
1016 calculate_live_intervals();
1018 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1022 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1023 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1025 inst
->src
[0].file
!= VGRF
||
1026 inst
->dst
.type
!= inst
->src
[0].type
||
1027 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1030 /* Remove no-op MOVs */
1031 if (inst
->dst
.file
== inst
->src
[0].file
&&
1032 inst
->dst
.nr
== inst
->src
[0].nr
&&
1033 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1034 bool is_nop_mov
= true;
1036 for (unsigned c
= 0; c
< 4; c
++) {
1037 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1040 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1047 inst
->remove(block
);
1052 bool to_mrf
= (inst
->dst
.file
== MRF
);
1054 /* Can't coalesce this GRF if someone else was going to
1057 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1060 /* We need to check interference with the final destination between this
1061 * instruction and the earliest instruction involved in writing the GRF
1062 * we're eliminating. To do that, keep track of which of our source
1063 * channels we've seen initialized.
1065 const unsigned chans_needed
=
1066 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1067 inst
->dst
.writemask
);
1068 unsigned chans_remaining
= chans_needed
;
1070 /* Now walk up the instruction stream trying to see if we can rewrite
1071 * everything writing to the temporary to write into the destination
1074 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1075 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1077 _scan_inst
= scan_inst
;
1079 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1080 /* Found something writing to the reg we want to coalesce away. */
1082 /* SEND instructions can't have MRF as a destination. */
1083 if (scan_inst
->mlen
)
1086 if (devinfo
->gen
== 6) {
1087 /* gen6 math instructions must have the destination be
1088 * VGRF, so no compute-to-MRF for them.
1090 if (scan_inst
->is_math()) {
1096 /* This doesn't handle saturation on the instruction we
1097 * want to coalesce away if the register types do not match.
1098 * But if scan_inst is a non type-converting 'mov', we can fix
1101 if (inst
->saturate
&&
1102 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1103 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1104 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1107 /* If we can't handle the swizzle, bail. */
1108 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1109 inst
->src
[0].swizzle
,
1114 /* This doesn't handle coalescing of multiple registers. */
1115 if (scan_inst
->regs_written
> 1)
1118 /* Mark which channels we found unconditional writes for. */
1119 if (!scan_inst
->predicate
)
1120 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1122 if (chans_remaining
== 0)
1126 /* You can't read from an MRF, so if someone else reads our MRF's
1127 * source GRF that we wanted to rewrite, that stops us. If it's a
1128 * GRF we're trying to coalesce to, we don't actually handle
1129 * rewriting sources so bail in that case as well.
1131 bool interfered
= false;
1132 for (int i
= 0; i
< 3; i
++) {
1133 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1134 scan_inst
->regs_read(i
)))
1140 /* If somebody else writes the same channels of our destination here,
1141 * we can't coalesce before that.
1143 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1144 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1148 /* Check for reads of the register we're trying to coalesce into. We
1149 * can't go rewriting instructions above that to put some other value
1150 * in the register instead.
1152 if (to_mrf
&& scan_inst
->mlen
> 0) {
1153 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1154 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1158 for (int i
= 0; i
< 3; i
++) {
1159 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1160 scan_inst
->regs_read(i
)))
1168 if (chans_remaining
== 0) {
1169 /* If we've made it here, we have an MOV we want to coalesce out, and
1170 * a scan_inst pointing to the earliest instruction involved in
1171 * computing the value. Now go rewrite the instruction stream
1174 vec4_instruction
*scan_inst
= _scan_inst
;
1175 while (scan_inst
!= inst
) {
1176 if (scan_inst
->dst
.file
== VGRF
&&
1177 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1178 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1179 scan_inst
->reswizzle(inst
->dst
.writemask
,
1180 inst
->src
[0].swizzle
);
1181 scan_inst
->dst
.file
= inst
->dst
.file
;
1182 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1183 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1184 if (inst
->saturate
&&
1185 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1186 /* If we have reached this point, scan_inst is a non
1187 * type-converting 'mov' and we can modify its register types
1188 * to match the ones in inst. Otherwise, we could have an
1189 * incorrect saturation result.
1191 scan_inst
->dst
.type
= inst
->dst
.type
;
1192 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1194 scan_inst
->saturate
|= inst
->saturate
;
1196 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1198 inst
->remove(block
);
1204 invalidate_live_intervals();
1210 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1211 * flow. We could probably do better here with some form of divergence
1215 vec4_visitor::eliminate_find_live_channel()
1217 bool progress
= false;
1220 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1221 switch (inst
->opcode
) {
1227 case BRW_OPCODE_ENDIF
:
1228 case BRW_OPCODE_WHILE
:
1232 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1234 inst
->opcode
= BRW_OPCODE_MOV
;
1235 inst
->src
[0] = src_reg(0);
1236 inst
->force_writemask_all
= true;
1250 * Splits virtual GRFs requesting more than one contiguous physical register.
1252 * We initially create large virtual GRFs for temporary structures, arrays,
1253 * and matrices, so that the dereference visitor functions can add reg_offsets
1254 * to work their way down to the actual member being accessed. But when it
1255 * comes to optimization, we'd like to treat each register as individual
1256 * storage if possible.
1258 * So far, the only thing that might prevent splitting is a send message from
1262 vec4_visitor::split_virtual_grfs()
1264 int num_vars
= this->alloc
.count
;
1265 int new_virtual_grf
[num_vars
];
1266 bool split_grf
[num_vars
];
1268 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1270 /* Try to split anything > 0 sized. */
1271 for (int i
= 0; i
< num_vars
; i
++) {
1272 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1275 /* Check that the instructions are compatible with the registers we're trying
1278 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1279 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1280 split_grf
[inst
->dst
.nr
] = false;
1282 for (int i
= 0; i
< 3; i
++) {
1283 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1284 split_grf
[inst
->src
[i
].nr
] = false;
1288 /* Allocate new space for split regs. Note that the virtual
1289 * numbers will be contiguous.
1291 for (int i
= 0; i
< num_vars
; i
++) {
1295 new_virtual_grf
[i
] = alloc
.allocate(1);
1296 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1297 unsigned reg
= alloc
.allocate(1);
1298 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1301 this->alloc
.sizes
[i
] = 1;
1304 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1305 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1306 inst
->dst
.reg_offset
!= 0) {
1307 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1308 inst
->dst
.reg_offset
- 1);
1309 inst
->dst
.reg_offset
= 0;
1311 for (int i
= 0; i
< 3; i
++) {
1312 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1313 inst
->src
[i
].reg_offset
!= 0) {
1314 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1315 inst
->src
[i
].reg_offset
- 1);
1316 inst
->src
[i
].reg_offset
= 0;
1320 invalidate_live_intervals();
1324 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1326 dump_instruction(be_inst
, stderr
);
1330 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1332 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1334 if (inst
->predicate
) {
1335 fprintf(file
, "(%cf0.%d%s) ",
1336 inst
->predicate_inverse
? '-' : '+',
1338 pred_ctrl_align16
[inst
->predicate
]);
1341 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1343 fprintf(file
, ".sat");
1344 if (inst
->conditional_mod
) {
1345 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1346 if (!inst
->predicate
&&
1347 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1348 inst
->opcode
!= BRW_OPCODE_IF
&&
1349 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1350 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1355 switch (inst
->dst
.file
) {
1357 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1360 fprintf(file
, "g%d", inst
->dst
.nr
);
1363 fprintf(file
, "m%d", inst
->dst
.nr
);
1366 switch (inst
->dst
.nr
) {
1368 fprintf(file
, "null");
1370 case BRW_ARF_ADDRESS
:
1371 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1373 case BRW_ARF_ACCUMULATOR
:
1374 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1377 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1380 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1383 if (inst
->dst
.subnr
)
1384 fprintf(file
, "+%d", inst
->dst
.subnr
);
1387 fprintf(file
, "(null)");
1392 unreachable("not reached");
1394 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1396 if (inst
->dst
.writemask
& 1)
1398 if (inst
->dst
.writemask
& 2)
1400 if (inst
->dst
.writemask
& 4)
1402 if (inst
->dst
.writemask
& 8)
1405 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1407 if (inst
->src
[0].file
!= BAD_FILE
)
1408 fprintf(file
, ", ");
1410 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1411 if (inst
->src
[i
].negate
)
1413 if (inst
->src
[i
].abs
)
1415 switch (inst
->src
[i
].file
) {
1417 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1420 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1423 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1426 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1429 switch (inst
->src
[i
].type
) {
1430 case BRW_REGISTER_TYPE_F
:
1431 fprintf(file
, "%fF", inst
->src
[i
].f
);
1433 case BRW_REGISTER_TYPE_D
:
1434 fprintf(file
, "%dD", inst
->src
[i
].d
);
1436 case BRW_REGISTER_TYPE_UD
:
1437 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1439 case BRW_REGISTER_TYPE_VF
:
1440 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1441 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1442 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1443 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1444 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1447 fprintf(file
, "???");
1452 switch (inst
->src
[i
].nr
) {
1454 fprintf(file
, "null");
1456 case BRW_ARF_ADDRESS
:
1457 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1459 case BRW_ARF_ACCUMULATOR
:
1460 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1463 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1466 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1469 if (inst
->src
[i
].subnr
)
1470 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1473 fprintf(file
, "(null)");
1476 unreachable("not reached");
1479 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1480 if (inst
->src
[i
].reg_offset
!= 0 &&
1481 inst
->src
[i
].file
== VGRF
&&
1482 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1483 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1485 if (inst
->src
[i
].file
!= IMM
) {
1486 static const char *chans
[4] = {"x", "y", "z", "w"};
1488 for (int c
= 0; c
< 4; c
++) {
1489 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1493 if (inst
->src
[i
].abs
)
1496 if (inst
->src
[i
].file
!= IMM
) {
1497 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1500 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1501 fprintf(file
, ", ");
1504 if (inst
->force_writemask_all
)
1505 fprintf(file
, " NoMask");
1507 fprintf(file
, "\n");
1511 static inline struct brw_reg
1512 attribute_to_hw_reg(int attr
, bool interleaved
)
1515 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1517 return brw_vec8_grf(attr
, 0);
1522 * Replace each register of type ATTR in this->instructions with a reference
1523 * to a fixed HW register.
1525 * If interleaved is true, then each attribute takes up half a register, with
1526 * register N containing attribute 2*N in its first half and attribute 2*N+1
1527 * in its second half (this corresponds to the payload setup used by geometry
1528 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1529 * false, then each attribute takes up a whole register, with register N
1530 * containing attribute N (this corresponds to the payload setup used by
1531 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1534 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1537 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1538 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1539 if (inst
->dst
.file
== ATTR
) {
1540 int grf
= attribute_map
[inst
->dst
.nr
+ inst
->dst
.reg_offset
];
1542 /* All attributes used in the shader need to have been assigned a
1543 * hardware register by the caller
1547 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1548 reg
.type
= inst
->dst
.type
;
1549 reg
.writemask
= inst
->dst
.writemask
;
1554 for (int i
= 0; i
< 3; i
++) {
1555 if (inst
->src
[i
].file
!= ATTR
)
1558 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1560 /* All attributes used in the shader need to have been assigned a
1561 * hardware register by the caller
1565 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1566 reg
.swizzle
= inst
->src
[i
].swizzle
;
1567 reg
.type
= inst
->src
[i
].type
;
1568 if (inst
->src
[i
].abs
)
1570 if (inst
->src
[i
].negate
)
1579 vec4_vs_visitor::setup_attributes(int payload_reg
)
1582 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1583 memset(attribute_map
, 0, sizeof(attribute_map
));
1586 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1587 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1588 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1593 /* VertexID is stored by the VF as the last vertex element, but we
1594 * don't represent it with a flag in inputs_read, so we call it
1597 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1598 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1601 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1603 return payload_reg
+ vs_prog_data
->nr_attributes
;
1607 vec4_visitor::setup_uniforms(int reg
)
1609 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1611 /* The pre-gen6 VS requires that some push constants get loaded no
1612 * matter what, or the GPU would hang.
1614 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1615 assert(this->uniforms
< this->uniform_array_size
);
1617 stage_prog_data
->param
=
1618 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1619 for (unsigned int i
= 0; i
< 4; i
++) {
1620 unsigned int slot
= this->uniforms
* 4 + i
;
1621 static gl_constant_value zero
= { 0.0 };
1622 stage_prog_data
->param
[slot
] = &zero
;
1628 reg
+= ALIGN(uniforms
, 2) / 2;
1631 stage_prog_data
->nr_params
= this->uniforms
* 4;
1633 prog_data
->base
.curb_read_length
=
1634 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1640 vec4_vs_visitor::setup_payload(void)
1644 /* The payload always contains important data in g0, which contains
1645 * the URB handles that are passed on to the URB write at the end
1646 * of the thread. So, we always start push constants at g1.
1650 reg
= setup_uniforms(reg
);
1652 reg
= setup_attributes(reg
);
1654 this->first_non_payload_grf
= reg
;
1658 vec4_visitor::get_timestamp()
1660 assert(devinfo
->gen
>= 7);
1662 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1667 BRW_REGISTER_TYPE_UD
,
1668 BRW_VERTICAL_STRIDE_0
,
1670 BRW_HORIZONTAL_STRIDE_4
,
1674 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1676 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1677 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1678 * even if it's not enabled in the dispatch.
1680 mov
->force_writemask_all
= true;
1682 return src_reg(dst
);
1686 vec4_visitor::emit_shader_time_begin()
1688 current_annotation
= "shader time start";
1689 shader_start_time
= get_timestamp();
1693 vec4_visitor::emit_shader_time_end()
1695 current_annotation
= "shader time end";
1696 src_reg shader_end_time
= get_timestamp();
1699 /* Check that there weren't any timestamp reset events (assuming these
1700 * were the only two timestamp reads that happened).
1702 src_reg reset_end
= shader_end_time
;
1703 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1704 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1705 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1707 emit(IF(BRW_PREDICATE_NORMAL
));
1709 /* Take the current timestamp and get the delta. */
1710 shader_start_time
.negate
= true;
1711 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1712 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1714 /* If there were no instructions between the two timestamp gets, the diff
1715 * is 2 cycles. Remove that overhead, so I can forget about that when
1716 * trying to determine the time taken for single instructions.
1718 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1720 emit_shader_time_write(0, src_reg(diff
));
1721 emit_shader_time_write(1, src_reg(1u));
1722 emit(BRW_OPCODE_ELSE
);
1723 emit_shader_time_write(2, src_reg(1u));
1724 emit(BRW_OPCODE_ENDIF
);
1728 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1731 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1733 dst_reg offset
= dst
;
1737 offset
.type
= BRW_REGISTER_TYPE_UD
;
1738 int index
= shader_time_index
* 3 + shader_time_subindex
;
1739 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1741 time
.type
= BRW_REGISTER_TYPE_UD
;
1742 emit(MOV(time
, value
));
1744 vec4_instruction
*inst
=
1745 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1750 vec4_visitor::convert_to_hw_regs()
1752 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1753 for (int i
= 0; i
< 3; i
++) {
1754 struct src_reg
&src
= inst
->src
[i
];
1758 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1759 reg
.type
= src
.type
;
1760 reg
.swizzle
= src
.swizzle
;
1762 reg
.negate
= src
.negate
;
1766 reg
= brw_imm_reg(src
.type
);
1771 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1772 (src
.nr
+ src
.reg_offset
) / 2,
1773 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1775 reg
.type
= src
.type
;
1776 reg
.swizzle
= src
.swizzle
;
1778 reg
.negate
= src
.negate
;
1780 /* This should have been moved to pull constants. */
1781 assert(!src
.reladdr
);
1789 /* Probably unused. */
1790 reg
= brw_null_reg();
1795 unreachable("not reached");
1800 dst_reg
&dst
= inst
->dst
;
1803 switch (inst
->dst
.file
) {
1805 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1806 reg
.type
= dst
.type
;
1807 reg
.writemask
= dst
.writemask
;
1811 assert(((dst
.nr
+ dst
.reg_offset
) & ~(1 << 7)) < BRW_MAX_MRF(devinfo
->gen
));
1812 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1813 reg
.type
= dst
.type
;
1814 reg
.writemask
= dst
.writemask
;
1823 reg
= brw_null_reg();
1829 unreachable("not reached");
1839 if (shader_time_index
>= 0)
1840 emit_shader_time_begin();
1853 /* Before any optimization, push array accesses out to scratch
1854 * space where we need them to be. This pass may allocate new
1855 * virtual GRFs, so we want to do it early. It also makes sure
1856 * that we have reladdr computations available for CSE, since we'll
1857 * often do repeated subexpressions for those.
1859 move_grf_array_access_to_scratch();
1860 move_uniform_array_access_to_pull_constants();
1862 pack_uniform_registers();
1863 move_push_constants_to_pull_constants();
1864 split_virtual_grfs();
1866 #define OPT(pass, args...) ({ \
1868 bool this_progress = pass(args); \
1870 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1871 char filename[64]; \
1872 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1873 stage_abbrev, nir->info.name, iteration, pass_num); \
1875 backend_shader::dump_instructions(filename); \
1878 progress = progress || this_progress; \
1883 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1885 snprintf(filename
, 64, "%s-%s-00-start",
1886 stage_abbrev
, nir
->info
.name
);
1888 backend_shader::dump_instructions(filename
);
1899 OPT(opt_predicated_break
, this);
1900 OPT(opt_reduce_swizzle
);
1901 OPT(dead_code_eliminate
);
1902 OPT(dead_control_flow_eliminate
, this);
1903 OPT(opt_copy_propagation
);
1904 OPT(opt_cmod_propagation
);
1907 OPT(opt_register_coalesce
);
1908 OPT(eliminate_find_live_channel
);
1913 if (OPT(opt_vector_float
)) {
1915 OPT(opt_copy_propagation
, false);
1916 OPT(opt_copy_propagation
, true);
1917 OPT(dead_code_eliminate
);
1925 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1926 /* Debug of register spilling: Go spill everything. */
1927 const int grf_count
= alloc
.count
;
1928 float spill_costs
[alloc
.count
];
1929 bool no_spill
[alloc
.count
];
1930 evaluate_spill_costs(spill_costs
, no_spill
);
1931 for (int i
= 0; i
< grf_count
; i
++) {
1938 bool allocated_without_spills
= reg_allocate();
1940 if (!allocated_without_spills
) {
1941 compiler
->shader_perf_log(log_data
,
1942 "%s shader triggered register spilling. "
1943 "Try reducing the number of live vec4 values "
1944 "to improve performance.\n",
1947 while (!reg_allocate()) {
1953 opt_schedule_instructions();
1955 opt_set_dependency_control();
1957 convert_to_hw_regs();
1959 if (last_scratch
> 0) {
1960 prog_data
->base
.total_scratch
=
1961 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1967 } /* namespace brw */
1972 * Compile a vertex shader.
1974 * Returns the final assembly and the program's size.
1977 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1979 const struct brw_vs_prog_key
*key
,
1980 struct brw_vs_prog_data
*prog_data
,
1981 const nir_shader
*shader
,
1982 gl_clip_plane
*clip_planes
,
1983 bool use_legacy_snorm_formula
,
1984 int shader_time_index
,
1985 unsigned *final_assembly_size
,
1988 const unsigned *assembly
= NULL
;
1990 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
1992 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
1993 * incoming vertex attribute. So, add an extra slot.
1995 if (shader
->info
.system_values_read
&
1996 (BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
1997 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2001 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2002 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2003 * vec4 mode, the hardware appears to wedge unless we read something.
2005 if (compiler
->scalar_vs
)
2006 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
2008 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
2010 prog_data
->nr_attributes
= nr_attributes
;
2012 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2013 * (overwriting the original contents), we need to make sure the size is
2014 * the larger of the two.
2016 const unsigned vue_entries
=
2017 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2019 if (compiler
->devinfo
->gen
== 6)
2020 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2022 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2024 if (compiler
->scalar_vs
) {
2025 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2027 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2028 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2029 shader
, 8, shader_time_index
);
2030 if (!v
.run_vs(clip_planes
)) {
2032 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2037 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2038 &prog_data
->base
.base
, v
.promoted_constants
,
2039 v
.runtime_check_aads_emit
, "VS");
2040 if (INTEL_DEBUG
& DEBUG_VS
) {
2041 const char *debug_name
=
2042 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2043 shader
->info
.label
? shader
->info
.label
: "unnamed",
2046 g
.enable_debug(debug_name
);
2048 g
.generate_code(v
.cfg
, 8);
2049 assembly
= g
.get_assembly(final_assembly_size
);
2053 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2055 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2056 shader
, clip_planes
, mem_ctx
,
2057 shader_time_index
, use_legacy_snorm_formula
);
2060 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2065 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2066 shader
, &prog_data
->base
, v
.cfg
,
2067 final_assembly_size
);