2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(float f
)
79 this->type
= BRW_REGISTER_TYPE_F
;
80 this->fixed_hw_reg
.dw1
.f
= f
;
83 src_reg::src_reg(uint32_t u
)
88 this->type
= BRW_REGISTER_TYPE_UD
;
89 this->fixed_hw_reg
.dw1
.ud
= u
;
92 src_reg::src_reg(int32_t i
)
97 this->type
= BRW_REGISTER_TYPE_D
;
98 this->fixed_hw_reg
.dw1
.d
= i
;
101 src_reg::src_reg(uint8_t vf
[4])
106 this->type
= BRW_REGISTER_TYPE_VF
;
107 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
110 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
115 this->type
= BRW_REGISTER_TYPE_VF
;
116 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
122 src_reg::src_reg(struct brw_reg reg
)
127 this->fixed_hw_reg
= reg
;
128 this->type
= reg
.type
;
131 src_reg::src_reg(const dst_reg
®
)
135 this->file
= reg
.file
;
137 this->reg_offset
= reg
.reg_offset
;
138 this->type
= reg
.type
;
139 this->reladdr
= reg
.reladdr
;
140 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
141 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(register_file file
, int reg
, brw_reg_type type
,
184 this->writemask
= writemask
;
187 dst_reg::dst_reg(struct brw_reg reg
)
192 this->fixed_hw_reg
= reg
;
193 this->type
= reg
.type
;
196 dst_reg::dst_reg(const src_reg
®
)
200 this->file
= reg
.file
;
202 this->reg_offset
= reg
.reg_offset
;
203 this->type
= reg
.type
;
204 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
205 this->reladdr
= reg
.reladdr
;
206 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
210 dst_reg::equals(const dst_reg
&r
) const
212 return (file
== r
.file
&&
214 reg_offset
== r
.reg_offset
&&
216 negate
== r
.negate
&&
218 writemask
== r
.writemask
&&
219 (reladdr
== r
.reladdr
||
220 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
221 ((file
!= HW_REG
&& file
!= IMM
) ||
222 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
223 sizeof(fixed_hw_reg
)) == 0));
227 vec4_instruction::is_send_from_grf()
230 case SHADER_OPCODE_SHADER_TIME_ADD
:
231 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
232 case SHADER_OPCODE_UNTYPED_ATOMIC
:
233 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
234 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
235 case SHADER_OPCODE_TYPED_ATOMIC
:
236 case SHADER_OPCODE_TYPED_SURFACE_READ
:
237 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
245 vec4_instruction::regs_read(unsigned arg
) const
247 if (src
[arg
].file
== BAD_FILE
)
251 case SHADER_OPCODE_SHADER_TIME_ADD
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 return arg
== 0 ? mlen
: 1;
260 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
261 return arg
== 1 ? mlen
: 1;
269 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
271 if (devinfo
->gen
== 6 && is_math())
274 if (is_send_from_grf())
277 if (!backend_instruction::can_do_source_mods())
284 vec4_instruction::can_change_types() const
286 return dst
.type
== src
[0].type
&&
287 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
288 (opcode
== BRW_OPCODE_MOV
||
289 (opcode
== BRW_OPCODE_SEL
&&
290 dst
.type
== src
[1].type
&&
291 predicate
!= BRW_PREDICATE_NONE
&&
292 !src
[1].abs
&& !src
[1].negate
));
296 * Returns how many MRFs an opcode will write over.
298 * Note that this is not the 0 or 1 implied writes in an actual gen
299 * instruction -- the generate_* functions generate additional MOVs
303 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
305 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
308 switch (inst
->opcode
) {
309 case SHADER_OPCODE_RCP
:
310 case SHADER_OPCODE_RSQ
:
311 case SHADER_OPCODE_SQRT
:
312 case SHADER_OPCODE_EXP2
:
313 case SHADER_OPCODE_LOG2
:
314 case SHADER_OPCODE_SIN
:
315 case SHADER_OPCODE_COS
:
317 case SHADER_OPCODE_INT_QUOTIENT
:
318 case SHADER_OPCODE_INT_REMAINDER
:
319 case SHADER_OPCODE_POW
:
321 case VS_OPCODE_URB_WRITE
:
323 case VS_OPCODE_PULL_CONSTANT_LOAD
:
325 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
327 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
329 case GS_OPCODE_URB_WRITE
:
330 case GS_OPCODE_URB_WRITE_ALLOCATE
:
331 case GS_OPCODE_THREAD_END
:
333 case GS_OPCODE_FF_SYNC
:
335 case SHADER_OPCODE_SHADER_TIME_ADD
:
337 case SHADER_OPCODE_TEX
:
338 case SHADER_OPCODE_TXL
:
339 case SHADER_OPCODE_TXD
:
340 case SHADER_OPCODE_TXF
:
341 case SHADER_OPCODE_TXF_CMS
:
342 case SHADER_OPCODE_TXF_CMS_W
:
343 case SHADER_OPCODE_TXF_MCS
:
344 case SHADER_OPCODE_TXS
:
345 case SHADER_OPCODE_TG4
:
346 case SHADER_OPCODE_TG4_OFFSET
:
347 case SHADER_OPCODE_SAMPLEINFO
:
348 case VS_OPCODE_GET_BUFFER_SIZE
:
349 return inst
->header_size
;
351 unreachable("not reached");
356 src_reg::equals(const src_reg
&r
) const
358 return (file
== r
.file
&&
360 reg_offset
== r
.reg_offset
&&
362 negate
== r
.negate
&&
364 swizzle
== r
.swizzle
&&
365 !reladdr
&& !r
.reladdr
&&
366 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
367 sizeof(fixed_hw_reg
)) == 0);
371 vec4_visitor::opt_vector_float()
373 bool progress
= false;
375 int last_reg
= -1, last_reg_offset
= -1;
376 enum register_file last_reg_file
= BAD_FILE
;
378 int remaining_channels
= 0;
381 vec4_instruction
*imm_inst
[4];
383 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
384 if (last_reg
!= inst
->dst
.reg
||
385 last_reg_offset
!= inst
->dst
.reg_offset
||
386 last_reg_file
!= inst
->dst
.file
) {
387 last_reg
= inst
->dst
.reg
;
388 last_reg_offset
= inst
->dst
.reg_offset
;
389 last_reg_file
= inst
->dst
.file
;
390 remaining_channels
= WRITEMASK_XYZW
;
395 if (inst
->opcode
!= BRW_OPCODE_MOV
||
396 inst
->dst
.writemask
== WRITEMASK_XYZW
||
397 inst
->src
[0].file
!= IMM
)
400 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
404 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
406 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
408 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
410 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
413 imm_inst
[inst_count
++] = inst
;
415 remaining_channels
&= ~inst
->dst
.writemask
;
416 if (remaining_channels
== 0) {
417 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
418 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
419 mov
->dst
.writemask
= WRITEMASK_XYZW
;
420 inst
->insert_after(block
, mov
);
423 for (int i
= 0; i
< inst_count
; i
++) {
424 imm_inst
[i
]->remove(block
);
431 invalidate_live_intervals();
436 /* Replaces unused channels of a swizzle with channels that are used.
438 * For instance, this pass transforms
440 * mov vgrf4.yz, vgrf5.wxzy
444 * mov vgrf4.yz, vgrf5.xxzx
446 * This eliminates false uses of some channels, letting dead code elimination
447 * remove the instructions that wrote them.
450 vec4_visitor::opt_reduce_swizzle()
452 bool progress
= false;
454 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
455 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
456 inst
->is_send_from_grf())
461 /* Determine which channels of the sources are read. */
462 switch (inst
->opcode
) {
463 case VEC4_OPCODE_PACK_BYTES
:
465 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
466 * but all four of src1.
468 swizzle
= brw_swizzle_for_size(4);
471 swizzle
= brw_swizzle_for_size(3);
474 swizzle
= brw_swizzle_for_size(2);
477 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
481 /* Update sources' swizzles. */
482 for (int i
= 0; i
< 3; i
++) {
483 if (inst
->src
[i
].file
!= GRF
&&
484 inst
->src
[i
].file
!= ATTR
&&
485 inst
->src
[i
].file
!= UNIFORM
)
488 const unsigned new_swizzle
=
489 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
490 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
491 inst
->src
[i
].swizzle
= new_swizzle
;
498 invalidate_live_intervals();
504 vec4_visitor::split_uniform_registers()
506 /* Prior to this, uniforms have been in an array sized according to
507 * the number of vector uniforms present, sparsely filled (so an
508 * aggregate results in reg indices being skipped over). Now we're
509 * going to cut those aggregates up so each .reg index is one
510 * vector. The goal is to make elimination of unused uniform
511 * components easier later.
513 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
514 for (int i
= 0 ; i
< 3; i
++) {
515 if (inst
->src
[i
].file
!= UNIFORM
)
518 assert(!inst
->src
[i
].reladdr
);
520 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
521 inst
->src
[i
].reg_offset
= 0;
525 /* Update that everything is now vector-sized. */
526 for (int i
= 0; i
< this->uniforms
; i
++) {
527 this->uniform_size
[i
] = 1;
532 vec4_visitor::pack_uniform_registers()
534 uint8_t chans_used
[this->uniforms
];
535 int new_loc
[this->uniforms
];
536 int new_chan
[this->uniforms
];
538 memset(chans_used
, 0, sizeof(chans_used
));
539 memset(new_loc
, 0, sizeof(new_loc
));
540 memset(new_chan
, 0, sizeof(new_chan
));
542 /* Find which uniform vectors are actually used by the program. We
543 * expect unused vector elements when we've moved array access out
544 * to pull constants, and from some GLSL code generators like wine.
546 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
548 switch (inst
->opcode
) {
549 case VEC4_OPCODE_PACK_BYTES
:
561 readmask
= inst
->dst
.writemask
;
565 for (int i
= 0 ; i
< 3; i
++) {
566 if (inst
->src
[i
].file
!= UNIFORM
)
569 int reg
= inst
->src
[i
].reg
;
570 for (int c
= 0; c
< 4; c
++) {
571 if (!(readmask
& (1 << c
)))
574 chans_used
[reg
] = MAX2(chans_used
[reg
],
575 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
580 int new_uniform_count
= 0;
582 /* Now, figure out a packing of the live uniform vectors into our
585 for (int src
= 0; src
< uniforms
; src
++) {
586 assert(src
< uniform_array_size
);
587 int size
= chans_used
[src
];
593 /* Find the lowest place we can slot this uniform in. */
594 for (dst
= 0; dst
< src
; dst
++) {
595 if (chans_used
[dst
] + size
<= 4)
604 new_chan
[src
] = chans_used
[dst
];
606 /* Move the references to the data */
607 for (int j
= 0; j
< size
; j
++) {
608 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
609 stage_prog_data
->param
[src
* 4 + j
];
612 chans_used
[dst
] += size
;
616 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
619 this->uniforms
= new_uniform_count
;
621 /* Now, update the instructions for our repacked uniforms. */
622 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
623 for (int i
= 0 ; i
< 3; i
++) {
624 int src
= inst
->src
[i
].reg
;
626 if (inst
->src
[i
].file
!= UNIFORM
)
629 inst
->src
[i
].reg
= new_loc
[src
];
630 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
631 new_chan
[src
], new_chan
[src
]);
637 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
639 * While GLSL IR also performs this optimization, we end up with it in
640 * our instruction stream for a couple of reasons. One is that we
641 * sometimes generate silly instructions, for example in array access
642 * where we'll generate "ADD offset, index, base" even if base is 0.
643 * The other is that GLSL IR's constant propagation doesn't track the
644 * components of aggregates, so some VS patterns (initialize matrix to
645 * 0, accumulate in vertex blending factors) end up breaking down to
646 * instructions involving 0.
649 vec4_visitor::opt_algebraic()
651 bool progress
= false;
653 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
654 switch (inst
->opcode
) {
656 if (inst
->src
[0].file
!= IMM
)
659 if (inst
->saturate
) {
660 if (inst
->dst
.type
!= inst
->src
[0].type
)
661 assert(!"unimplemented: saturate mixed types");
663 if (brw_saturate_immediate(inst
->dst
.type
,
664 &inst
->src
[0].fixed_hw_reg
)) {
665 inst
->saturate
= false;
671 case VEC4_OPCODE_UNPACK_UNIFORM
:
672 if (inst
->src
[0].file
!= UNIFORM
) {
673 inst
->opcode
= BRW_OPCODE_MOV
;
679 if (inst
->src
[1].is_zero()) {
680 inst
->opcode
= BRW_OPCODE_MOV
;
681 inst
->src
[1] = src_reg();
687 if (inst
->src
[1].is_zero()) {
688 inst
->opcode
= BRW_OPCODE_MOV
;
689 switch (inst
->src
[0].type
) {
690 case BRW_REGISTER_TYPE_F
:
691 inst
->src
[0] = src_reg(0.0f
);
693 case BRW_REGISTER_TYPE_D
:
694 inst
->src
[0] = src_reg(0);
696 case BRW_REGISTER_TYPE_UD
:
697 inst
->src
[0] = src_reg(0u);
700 unreachable("not reached");
702 inst
->src
[1] = src_reg();
704 } else if (inst
->src
[1].is_one()) {
705 inst
->opcode
= BRW_OPCODE_MOV
;
706 inst
->src
[1] = src_reg();
708 } else if (inst
->src
[1].is_negative_one()) {
709 inst
->opcode
= BRW_OPCODE_MOV
;
710 inst
->src
[0].negate
= !inst
->src
[0].negate
;
711 inst
->src
[1] = src_reg();
716 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
718 inst
->src
[0].negate
&&
719 inst
->src
[1].is_zero()) {
720 inst
->src
[0].abs
= false;
721 inst
->src
[0].negate
= false;
722 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
727 case SHADER_OPCODE_RCP
: {
728 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
729 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
730 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
731 inst
->opcode
= SHADER_OPCODE_RSQ
;
732 inst
->src
[0] = prev
->src
[0];
738 case SHADER_OPCODE_BROADCAST
:
739 if (is_uniform(inst
->src
[0]) ||
740 inst
->src
[1].is_zero()) {
741 inst
->opcode
= BRW_OPCODE_MOV
;
742 inst
->src
[1] = src_reg();
743 inst
->force_writemask_all
= true;
754 invalidate_live_intervals();
760 * Only a limited number of hardware registers may be used for push
761 * constants, so this turns access to the overflowed constants into
765 vec4_visitor::move_push_constants_to_pull_constants()
767 int pull_constant_loc
[this->uniforms
];
769 /* Only allow 32 registers (256 uniform components) as push constants,
770 * which is the limit on gen6.
772 * If changing this value, note the limitation about total_regs in
775 int max_uniform_components
= 32 * 8;
776 if (this->uniforms
* 4 <= max_uniform_components
)
779 /* Make some sort of choice as to which uniforms get sent to pull
780 * constants. We could potentially do something clever here like
781 * look for the most infrequently used uniform vec4s, but leave
784 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
785 pull_constant_loc
[i
/ 4] = -1;
787 if (i
>= max_uniform_components
) {
788 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
790 /* Try to find an existing copy of this uniform in the pull
791 * constants if it was part of an array access already.
793 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
796 for (matches
= 0; matches
< 4; matches
++) {
797 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
802 pull_constant_loc
[i
/ 4] = j
/ 4;
807 if (pull_constant_loc
[i
/ 4] == -1) {
808 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
809 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
811 for (int j
= 0; j
< 4; j
++) {
812 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
819 /* Now actually rewrite usage of the things we've moved to pull
822 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
823 for (int i
= 0 ; i
< 3; i
++) {
824 if (inst
->src
[i
].file
!= UNIFORM
||
825 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
828 int uniform
= inst
->src
[i
].reg
;
830 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
832 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
833 pull_constant_loc
[uniform
]);
835 inst
->src
[i
].file
= temp
.file
;
836 inst
->src
[i
].reg
= temp
.reg
;
837 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
838 inst
->src
[i
].reladdr
= NULL
;
842 /* Repack push constants to remove the now-unused ones. */
843 pack_uniform_registers();
846 /* Conditions for which we want to avoid setting the dependency control bits */
848 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
850 #define IS_DWORD(reg) \
851 (reg.type == BRW_REGISTER_TYPE_UD || \
852 reg.type == BRW_REGISTER_TYPE_D)
854 /* "When source or destination datatype is 64b or operation is integer DWord
855 * multiply, DepCtrl must not be used."
856 * May apply to future SoCs as well.
858 if (devinfo
->is_cherryview
) {
859 if (inst
->opcode
== BRW_OPCODE_MUL
&&
860 IS_DWORD(inst
->src
[0]) &&
861 IS_DWORD(inst
->src
[1]))
866 if (devinfo
->gen
>= 8) {
867 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
873 * In the presence of send messages, totally interrupt dependency
874 * control. They're long enough that the chance of dependency
875 * control around them just doesn't matter.
878 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
879 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
880 * completes the scoreboard clear must have a non-zero execution mask. This
881 * means, if any kind of predication can change the execution mask or channel
882 * enable of the last instruction, the optimization must be avoided. This is
883 * to avoid instructions being shot down the pipeline when no writes are
887 * Dependency control does not work well over math instructions.
888 * NB: Discovered empirically
890 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
894 * Sets the dependency control fields on instructions after register
895 * allocation and before the generator is run.
897 * When you have a sequence of instructions like:
899 * DP4 temp.x vertex uniform[0]
900 * DP4 temp.y vertex uniform[0]
901 * DP4 temp.z vertex uniform[0]
902 * DP4 temp.w vertex uniform[0]
904 * The hardware doesn't know that it can actually run the later instructions
905 * while the previous ones are in flight, producing stalls. However, we have
906 * manual fields we can set in the instructions that let it do so.
909 vec4_visitor::opt_set_dependency_control()
911 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
912 uint8_t grf_channels_written
[BRW_MAX_GRF
];
913 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
914 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
916 assert(prog_data
->total_grf
||
917 !"Must be called after register allocation");
919 foreach_block (block
, cfg
) {
920 memset(last_grf_write
, 0, sizeof(last_grf_write
));
921 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
923 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
924 /* If we read from a register that we were doing dependency control
925 * on, don't do dependency control across the read.
927 for (int i
= 0; i
< 3; i
++) {
928 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
929 if (inst
->src
[i
].file
== GRF
) {
930 last_grf_write
[reg
] = NULL
;
931 } else if (inst
->src
[i
].file
== HW_REG
) {
932 memset(last_grf_write
, 0, sizeof(last_grf_write
));
935 assert(inst
->src
[i
].file
!= MRF
);
938 if (is_dep_ctrl_unsafe(inst
)) {
939 memset(last_grf_write
, 0, sizeof(last_grf_write
));
940 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
944 /* Now, see if we can do dependency control for this instruction
945 * against a previous one writing to its destination.
947 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
948 if (inst
->dst
.file
== GRF
) {
949 if (last_grf_write
[reg
] &&
950 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
951 last_grf_write
[reg
]->no_dd_clear
= true;
952 inst
->no_dd_check
= true;
954 grf_channels_written
[reg
] = 0;
957 last_grf_write
[reg
] = inst
;
958 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
959 } else if (inst
->dst
.file
== MRF
) {
960 if (last_mrf_write
[reg
] &&
961 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
962 last_mrf_write
[reg
]->no_dd_clear
= true;
963 inst
->no_dd_check
= true;
965 mrf_channels_written
[reg
] = 0;
968 last_mrf_write
[reg
] = inst
;
969 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
970 } else if (inst
->dst
.reg
== HW_REG
) {
971 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
972 memset(last_grf_write
, 0, sizeof(last_grf_write
));
973 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
974 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
981 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
986 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
987 * or writemasking are not allowed.
989 if (devinfo
->gen
== 6 && is_math() &&
990 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
993 /* If this instruction sets anything not referenced by swizzle, then we'd
994 * totally break it when we reswizzle.
996 if (dst
.writemask
& ~swizzle_mask
)
1002 /* We can't use swizzles on the accumulator and that's really the only
1003 * HW_REG we would care to reswizzle so just disallow them all.
1005 for (int i
= 0; i
< 3; i
++) {
1006 if (src
[i
].file
== HW_REG
)
1014 * For any channels in the swizzle's source that were populated by this
1015 * instruction, rewrite the instruction to put the appropriate result directly
1016 * in those channels.
1018 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1021 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1023 /* Destination write mask doesn't correspond to source swizzle for the dot
1024 * product and pack_bytes instructions.
1026 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1027 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1028 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1029 for (int i
= 0; i
< 3; i
++) {
1030 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1033 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1037 /* Apply the specified swizzle and writemask to the original mask of
1038 * written components.
1040 dst
.writemask
= dst_writemask
&
1041 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1045 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1046 * just written and then MOVed into another reg and making the original write
1047 * of the GRF write directly to the final destination instead.
1050 vec4_visitor::opt_register_coalesce()
1052 bool progress
= false;
1055 calculate_live_intervals();
1057 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1061 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1062 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1064 inst
->src
[0].file
!= GRF
||
1065 inst
->dst
.type
!= inst
->src
[0].type
||
1066 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1069 /* Remove no-op MOVs */
1070 if (inst
->dst
.file
== inst
->src
[0].file
&&
1071 inst
->dst
.reg
== inst
->src
[0].reg
&&
1072 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1073 bool is_nop_mov
= true;
1075 for (unsigned c
= 0; c
< 4; c
++) {
1076 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1079 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1086 inst
->remove(block
);
1091 bool to_mrf
= (inst
->dst
.file
== MRF
);
1093 /* Can't coalesce this GRF if someone else was going to
1096 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1099 /* We need to check interference with the final destination between this
1100 * instruction and the earliest instruction involved in writing the GRF
1101 * we're eliminating. To do that, keep track of which of our source
1102 * channels we've seen initialized.
1104 const unsigned chans_needed
=
1105 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1106 inst
->dst
.writemask
);
1107 unsigned chans_remaining
= chans_needed
;
1109 /* Now walk up the instruction stream trying to see if we can rewrite
1110 * everything writing to the temporary to write into the destination
1113 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1114 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1116 _scan_inst
= scan_inst
;
1118 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1119 /* Found something writing to the reg we want to coalesce away. */
1121 /* SEND instructions can't have MRF as a destination. */
1122 if (scan_inst
->mlen
)
1125 if (devinfo
->gen
== 6) {
1126 /* gen6 math instructions must have the destination be
1127 * GRF, so no compute-to-MRF for them.
1129 if (scan_inst
->is_math()) {
1135 /* This doesn't handle saturation on the instruction we
1136 * want to coalesce away if the register types do not match.
1137 * But if scan_inst is a non type-converting 'mov', we can fix
1140 if (inst
->saturate
&&
1141 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1142 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1143 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1146 /* If we can't handle the swizzle, bail. */
1147 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1148 inst
->src
[0].swizzle
,
1153 /* This doesn't handle coalescing of multiple registers. */
1154 if (scan_inst
->regs_written
> 1)
1157 /* Mark which channels we found unconditional writes for. */
1158 if (!scan_inst
->predicate
)
1159 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1161 if (chans_remaining
== 0)
1165 /* You can't read from an MRF, so if someone else reads our MRF's
1166 * source GRF that we wanted to rewrite, that stops us. If it's a
1167 * GRF we're trying to coalesce to, we don't actually handle
1168 * rewriting sources so bail in that case as well.
1170 bool interfered
= false;
1171 for (int i
= 0; i
< 3; i
++) {
1172 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1173 scan_inst
->regs_read(i
)))
1179 /* If somebody else writes the same channels of our destination here,
1180 * we can't coalesce before that.
1182 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1183 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1187 /* Check for reads of the register we're trying to coalesce into. We
1188 * can't go rewriting instructions above that to put some other value
1189 * in the register instead.
1191 if (to_mrf
&& scan_inst
->mlen
> 0) {
1192 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1193 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1197 for (int i
= 0; i
< 3; i
++) {
1198 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1199 scan_inst
->regs_read(i
)))
1207 if (chans_remaining
== 0) {
1208 /* If we've made it here, we have an MOV we want to coalesce out, and
1209 * a scan_inst pointing to the earliest instruction involved in
1210 * computing the value. Now go rewrite the instruction stream
1213 vec4_instruction
*scan_inst
= _scan_inst
;
1214 while (scan_inst
!= inst
) {
1215 if (scan_inst
->dst
.file
== GRF
&&
1216 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1217 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1218 scan_inst
->reswizzle(inst
->dst
.writemask
,
1219 inst
->src
[0].swizzle
);
1220 scan_inst
->dst
.file
= inst
->dst
.file
;
1221 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1222 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1223 if (inst
->saturate
&&
1224 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1225 /* If we have reached this point, scan_inst is a non
1226 * type-converting 'mov' and we can modify its register types
1227 * to match the ones in inst. Otherwise, we could have an
1228 * incorrect saturation result.
1230 scan_inst
->dst
.type
= inst
->dst
.type
;
1231 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1233 scan_inst
->saturate
|= inst
->saturate
;
1235 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1237 inst
->remove(block
);
1243 invalidate_live_intervals();
1249 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1250 * flow. We could probably do better here with some form of divergence
1254 vec4_visitor::eliminate_find_live_channel()
1256 bool progress
= false;
1259 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1260 switch (inst
->opcode
) {
1266 case BRW_OPCODE_ENDIF
:
1267 case BRW_OPCODE_WHILE
:
1271 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1273 inst
->opcode
= BRW_OPCODE_MOV
;
1274 inst
->src
[0] = src_reg(0);
1275 inst
->force_writemask_all
= true;
1289 * Splits virtual GRFs requesting more than one contiguous physical register.
1291 * We initially create large virtual GRFs for temporary structures, arrays,
1292 * and matrices, so that the dereference visitor functions can add reg_offsets
1293 * to work their way down to the actual member being accessed. But when it
1294 * comes to optimization, we'd like to treat each register as individual
1295 * storage if possible.
1297 * So far, the only thing that might prevent splitting is a send message from
1301 vec4_visitor::split_virtual_grfs()
1303 int num_vars
= this->alloc
.count
;
1304 int new_virtual_grf
[num_vars
];
1305 bool split_grf
[num_vars
];
1307 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1309 /* Try to split anything > 0 sized. */
1310 for (int i
= 0; i
< num_vars
; i
++) {
1311 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1314 /* Check that the instructions are compatible with the registers we're trying
1317 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1318 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1319 split_grf
[inst
->dst
.reg
] = false;
1321 for (int i
= 0; i
< 3; i
++) {
1322 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1323 split_grf
[inst
->src
[i
].reg
] = false;
1327 /* Allocate new space for split regs. Note that the virtual
1328 * numbers will be contiguous.
1330 for (int i
= 0; i
< num_vars
; i
++) {
1334 new_virtual_grf
[i
] = alloc
.allocate(1);
1335 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1336 unsigned reg
= alloc
.allocate(1);
1337 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1340 this->alloc
.sizes
[i
] = 1;
1343 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1344 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1345 inst
->dst
.reg_offset
!= 0) {
1346 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1347 inst
->dst
.reg_offset
- 1);
1348 inst
->dst
.reg_offset
= 0;
1350 for (int i
= 0; i
< 3; i
++) {
1351 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1352 inst
->src
[i
].reg_offset
!= 0) {
1353 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1354 inst
->src
[i
].reg_offset
- 1);
1355 inst
->src
[i
].reg_offset
= 0;
1359 invalidate_live_intervals();
1363 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1365 dump_instruction(be_inst
, stderr
);
1369 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1371 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1373 if (inst
->predicate
) {
1374 fprintf(file
, "(%cf0.%d%s) ",
1375 inst
->predicate_inverse
? '-' : '+',
1377 pred_ctrl_align16
[inst
->predicate
]);
1380 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1382 fprintf(file
, ".sat");
1383 if (inst
->conditional_mod
) {
1384 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1385 if (!inst
->predicate
&&
1386 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1387 inst
->opcode
!= BRW_OPCODE_IF
&&
1388 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1389 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1394 switch (inst
->dst
.file
) {
1396 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1399 fprintf(file
, "m%d", inst
->dst
.reg
);
1402 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1403 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1405 fprintf(file
, "null");
1407 case BRW_ARF_ADDRESS
:
1408 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1410 case BRW_ARF_ACCUMULATOR
:
1411 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1414 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1415 inst
->dst
.fixed_hw_reg
.subnr
);
1418 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1419 inst
->dst
.fixed_hw_reg
.subnr
);
1423 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1425 if (inst
->dst
.fixed_hw_reg
.subnr
)
1426 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1429 fprintf(file
, "(null)");
1434 unreachable("not reached");
1436 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1438 if (inst
->dst
.writemask
& 1)
1440 if (inst
->dst
.writemask
& 2)
1442 if (inst
->dst
.writemask
& 4)
1444 if (inst
->dst
.writemask
& 8)
1447 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1449 if (inst
->src
[0].file
!= BAD_FILE
)
1450 fprintf(file
, ", ");
1452 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1453 if (inst
->src
[i
].negate
)
1455 if (inst
->src
[i
].abs
)
1457 switch (inst
->src
[i
].file
) {
1459 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1462 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1465 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1468 switch (inst
->src
[i
].type
) {
1469 case BRW_REGISTER_TYPE_F
:
1470 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1472 case BRW_REGISTER_TYPE_D
:
1473 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1475 case BRW_REGISTER_TYPE_UD
:
1476 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1478 case BRW_REGISTER_TYPE_VF
:
1479 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1480 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1481 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1482 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1483 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1486 fprintf(file
, "???");
1491 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1493 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1495 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1496 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1498 fprintf(file
, "null");
1500 case BRW_ARF_ADDRESS
:
1501 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1503 case BRW_ARF_ACCUMULATOR
:
1504 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1507 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1508 inst
->src
[i
].fixed_hw_reg
.subnr
);
1511 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1512 inst
->src
[i
].fixed_hw_reg
.subnr
);
1516 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1518 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1519 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1520 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1524 fprintf(file
, "(null)");
1527 unreachable("not reached");
1530 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1531 if (inst
->src
[i
].reg_offset
!= 0 &&
1532 inst
->src
[i
].file
== GRF
&&
1533 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1534 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1536 if (inst
->src
[i
].file
!= IMM
) {
1537 static const char *chans
[4] = {"x", "y", "z", "w"};
1539 for (int c
= 0; c
< 4; c
++) {
1540 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1544 if (inst
->src
[i
].abs
)
1547 if (inst
->src
[i
].file
!= IMM
) {
1548 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1551 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1552 fprintf(file
, ", ");
1555 fprintf(file
, "\n");
1559 static inline struct brw_reg
1560 attribute_to_hw_reg(int attr
, bool interleaved
)
1563 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1565 return brw_vec8_grf(attr
, 0);
1570 * Replace each register of type ATTR in this->instructions with a reference
1571 * to a fixed HW register.
1573 * If interleaved is true, then each attribute takes up half a register, with
1574 * register N containing attribute 2*N in its first half and attribute 2*N+1
1575 * in its second half (this corresponds to the payload setup used by geometry
1576 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1577 * false, then each attribute takes up a whole register, with register N
1578 * containing attribute N (this corresponds to the payload setup used by
1579 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1582 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1585 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1586 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1587 if (inst
->dst
.file
== ATTR
) {
1588 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1590 /* All attributes used in the shader need to have been assigned a
1591 * hardware register by the caller
1595 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1596 reg
.type
= inst
->dst
.type
;
1597 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1599 inst
->dst
.file
= HW_REG
;
1600 inst
->dst
.fixed_hw_reg
= reg
;
1603 for (int i
= 0; i
< 3; i
++) {
1604 if (inst
->src
[i
].file
!= ATTR
)
1607 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1609 /* All attributes used in the shader need to have been assigned a
1610 * hardware register by the caller
1614 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1615 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1616 reg
.type
= inst
->src
[i
].type
;
1617 if (inst
->src
[i
].abs
)
1619 if (inst
->src
[i
].negate
)
1622 inst
->src
[i
].file
= HW_REG
;
1623 inst
->src
[i
].fixed_hw_reg
= reg
;
1629 vec4_vs_visitor::setup_attributes(int payload_reg
)
1632 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1633 memset(attribute_map
, 0, sizeof(attribute_map
));
1636 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1637 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1638 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1643 /* VertexID is stored by the VF as the last vertex element, but we
1644 * don't represent it with a flag in inputs_read, so we call it
1647 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1648 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1651 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1653 return payload_reg
+ vs_prog_data
->nr_attributes
;
1657 vec4_visitor::setup_uniforms(int reg
)
1659 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1661 /* The pre-gen6 VS requires that some push constants get loaded no
1662 * matter what, or the GPU would hang.
1664 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1665 assert(this->uniforms
< this->uniform_array_size
);
1667 stage_prog_data
->param
=
1668 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1669 for (unsigned int i
= 0; i
< 4; i
++) {
1670 unsigned int slot
= this->uniforms
* 4 + i
;
1671 static gl_constant_value zero
= { 0.0 };
1672 stage_prog_data
->param
[slot
] = &zero
;
1678 reg
+= ALIGN(uniforms
, 2) / 2;
1681 stage_prog_data
->nr_params
= this->uniforms
* 4;
1683 prog_data
->base
.curb_read_length
=
1684 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1690 vec4_vs_visitor::setup_payload(void)
1694 /* The payload always contains important data in g0, which contains
1695 * the URB handles that are passed on to the URB write at the end
1696 * of the thread. So, we always start push constants at g1.
1700 reg
= setup_uniforms(reg
);
1702 reg
= setup_attributes(reg
);
1704 this->first_non_payload_grf
= reg
;
1708 vec4_visitor::get_timestamp()
1710 assert(devinfo
->gen
>= 7);
1712 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1717 BRW_REGISTER_TYPE_UD
,
1718 BRW_VERTICAL_STRIDE_0
,
1720 BRW_HORIZONTAL_STRIDE_4
,
1724 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1726 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1727 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1728 * even if it's not enabled in the dispatch.
1730 mov
->force_writemask_all
= true;
1732 return src_reg(dst
);
1736 vec4_visitor::emit_shader_time_begin()
1738 current_annotation
= "shader time start";
1739 shader_start_time
= get_timestamp();
1743 vec4_visitor::emit_shader_time_end()
1745 current_annotation
= "shader time end";
1746 src_reg shader_end_time
= get_timestamp();
1749 /* Check that there weren't any timestamp reset events (assuming these
1750 * were the only two timestamp reads that happened).
1752 src_reg reset_end
= shader_end_time
;
1753 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1754 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1755 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1757 emit(IF(BRW_PREDICATE_NORMAL
));
1759 /* Take the current timestamp and get the delta. */
1760 shader_start_time
.negate
= true;
1761 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1762 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1764 /* If there were no instructions between the two timestamp gets, the diff
1765 * is 2 cycles. Remove that overhead, so I can forget about that when
1766 * trying to determine the time taken for single instructions.
1768 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1770 emit_shader_time_write(0, src_reg(diff
));
1771 emit_shader_time_write(1, src_reg(1u));
1772 emit(BRW_OPCODE_ELSE
);
1773 emit_shader_time_write(2, src_reg(1u));
1774 emit(BRW_OPCODE_ENDIF
);
1778 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1781 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1783 dst_reg offset
= dst
;
1787 offset
.type
= BRW_REGISTER_TYPE_UD
;
1788 int index
= shader_time_index
* 3 + shader_time_subindex
;
1789 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1791 time
.type
= BRW_REGISTER_TYPE_UD
;
1792 emit(MOV(time
, value
));
1794 vec4_instruction
*inst
=
1795 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1800 vec4_visitor::convert_to_hw_regs()
1802 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1803 for (int i
= 0; i
< 3; i
++) {
1804 struct src_reg
&src
= inst
->src
[i
];
1808 reg
= brw_vec8_grf(src
.reg
+ src
.reg_offset
, 0);
1809 reg
.type
= src
.type
;
1810 reg
.dw1
.bits
.swizzle
= src
.swizzle
;
1812 reg
.negate
= src
.negate
;
1816 reg
= brw_imm_reg(src
.type
);
1817 reg
.dw1
.ud
= src
.fixed_hw_reg
.dw1
.ud
;
1821 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1822 (src
.reg
+ src
.reg_offset
) / 2,
1823 ((src
.reg
+ src
.reg_offset
) % 2) * 4),
1825 reg
.type
= src
.type
;
1826 reg
.dw1
.bits
.swizzle
= src
.swizzle
;
1828 reg
.negate
= src
.negate
;
1830 /* This should have been moved to pull constants. */
1831 assert(!src
.reladdr
);
1835 assert(src
.type
== src
.fixed_hw_reg
.type
);
1839 /* Probably unused. */
1840 reg
= brw_null_reg();
1845 unreachable("not reached");
1847 src
.fixed_hw_reg
= reg
;
1850 dst_reg
&dst
= inst
->dst
;
1853 switch (inst
->dst
.file
) {
1855 reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
1856 reg
.type
= dst
.type
;
1857 reg
.dw1
.bits
.writemask
= dst
.writemask
;
1861 assert(((dst
.reg
+ dst
.reg_offset
) & ~(1 << 7)) < BRW_MAX_MRF(devinfo
->gen
));
1862 reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
1863 reg
.type
= dst
.type
;
1864 reg
.dw1
.bits
.writemask
= dst
.writemask
;
1868 assert(dst
.type
== dst
.fixed_hw_reg
.type
);
1869 reg
= dst
.fixed_hw_reg
;
1873 reg
= brw_null_reg();
1879 unreachable("not reached");
1882 dst
.fixed_hw_reg
= reg
;
1889 if (shader_time_index
>= 0)
1890 emit_shader_time_begin();
1903 /* Before any optimization, push array accesses out to scratch
1904 * space where we need them to be. This pass may allocate new
1905 * virtual GRFs, so we want to do it early. It also makes sure
1906 * that we have reladdr computations available for CSE, since we'll
1907 * often do repeated subexpressions for those.
1909 move_grf_array_access_to_scratch();
1910 move_uniform_array_access_to_pull_constants();
1912 pack_uniform_registers();
1913 move_push_constants_to_pull_constants();
1914 split_virtual_grfs();
1916 #define OPT(pass, args...) ({ \
1918 bool this_progress = pass(args); \
1920 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1921 char filename[64]; \
1922 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1923 stage_abbrev, nir->info.name, iteration, pass_num); \
1925 backend_shader::dump_instructions(filename); \
1928 progress = progress || this_progress; \
1933 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1935 snprintf(filename
, 64, "%s-%s-00-start",
1936 stage_abbrev
, nir
->info
.name
);
1938 backend_shader::dump_instructions(filename
);
1949 OPT(opt_predicated_break
, this);
1950 OPT(opt_reduce_swizzle
);
1951 OPT(dead_code_eliminate
);
1952 OPT(dead_control_flow_eliminate
, this);
1953 OPT(opt_copy_propagation
);
1954 OPT(opt_cmod_propagation
);
1957 OPT(opt_register_coalesce
);
1958 OPT(eliminate_find_live_channel
);
1963 if (OPT(opt_vector_float
)) {
1965 OPT(opt_copy_propagation
, false);
1966 OPT(opt_copy_propagation
, true);
1967 OPT(dead_code_eliminate
);
1975 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1976 /* Debug of register spilling: Go spill everything. */
1977 const int grf_count
= alloc
.count
;
1978 float spill_costs
[alloc
.count
];
1979 bool no_spill
[alloc
.count
];
1980 evaluate_spill_costs(spill_costs
, no_spill
);
1981 for (int i
= 0; i
< grf_count
; i
++) {
1988 bool allocated_without_spills
= reg_allocate();
1990 if (!allocated_without_spills
) {
1991 compiler
->shader_perf_log(log_data
,
1992 "%s shader triggered register spilling. "
1993 "Try reducing the number of live vec4 values "
1994 "to improve performance.\n",
1997 while (!reg_allocate()) {
2003 opt_schedule_instructions();
2005 opt_set_dependency_control();
2007 convert_to_hw_regs();
2009 if (last_scratch
> 0) {
2010 prog_data
->base
.total_scratch
=
2011 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2017 } /* namespace brw */
2022 * Compile a vertex shader.
2024 * Returns the final assembly and the program's size.
2027 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2029 const struct brw_vs_prog_key
*key
,
2030 struct brw_vs_prog_data
*prog_data
,
2031 const nir_shader
*shader
,
2032 gl_clip_plane
*clip_planes
,
2033 bool use_legacy_snorm_formula
,
2034 int shader_time_index
,
2035 unsigned *final_assembly_size
,
2038 const unsigned *assembly
= NULL
;
2040 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
2042 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2043 * incoming vertex attribute. So, add an extra slot.
2045 if (shader
->info
.system_values_read
&
2046 (BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2047 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2051 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2052 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2053 * vec4 mode, the hardware appears to wedge unless we read something.
2055 if (compiler
->scalar_vs
)
2056 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
2058 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
2060 prog_data
->nr_attributes
= nr_attributes
;
2062 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2063 * (overwriting the original contents), we need to make sure the size is
2064 * the larger of the two.
2066 const unsigned vue_entries
=
2067 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2069 if (compiler
->devinfo
->gen
== 6)
2070 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2072 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2074 if (compiler
->scalar_vs
) {
2075 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2077 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2078 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2079 shader
, 8, shader_time_index
);
2080 if (!v
.run_vs(clip_planes
)) {
2082 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2087 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2088 &prog_data
->base
.base
, v
.promoted_constants
,
2089 v
.runtime_check_aads_emit
, "VS");
2090 if (INTEL_DEBUG
& DEBUG_VS
) {
2091 const char *debug_name
=
2092 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2093 shader
->info
.label
? shader
->info
.label
: "unnamed",
2096 g
.enable_debug(debug_name
);
2098 g
.generate_code(v
.cfg
, 8);
2099 assembly
= g
.get_assembly(final_assembly_size
);
2103 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2105 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2106 shader
, clip_planes
, mem_ctx
,
2107 shader_time_index
, use_legacy_snorm_formula
);
2110 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2115 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2116 shader
, &prog_data
->base
, v
.cfg
,
2117 final_assembly_size
);