2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_dead_control_flow.h"
31 #include "main/macros.h"
32 #include "main/shaderobj.h"
33 #include "program/prog_print.h"
34 #include "program/prog_parameter.h"
37 #define MAX_INSTRUCTION (1 << 30)
46 memset(this, 0, sizeof(*this));
48 this->file
= BAD_FILE
;
51 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
57 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
58 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
60 this->swizzle
= BRW_SWIZZLE_XYZW
;
63 /** Generic unset register constructor. */
69 src_reg::src_reg(float f
)
74 this->type
= BRW_REGISTER_TYPE_F
;
75 this->fixed_hw_reg
.dw1
.f
= f
;
78 src_reg::src_reg(uint32_t u
)
83 this->type
= BRW_REGISTER_TYPE_UD
;
84 this->fixed_hw_reg
.dw1
.ud
= u
;
87 src_reg::src_reg(int32_t i
)
92 this->type
= BRW_REGISTER_TYPE_D
;
93 this->fixed_hw_reg
.dw1
.d
= i
;
96 src_reg::src_reg(uint8_t vf
[4])
101 this->type
= BRW_REGISTER_TYPE_VF
;
102 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
105 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
110 this->type
= BRW_REGISTER_TYPE_VF
;
111 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
117 src_reg::src_reg(struct brw_reg reg
)
122 this->fixed_hw_reg
= reg
;
123 this->type
= reg
.type
;
126 src_reg::src_reg(const dst_reg
®
)
130 this->file
= reg
.file
;
132 this->reg_offset
= reg
.reg_offset
;
133 this->type
= reg
.type
;
134 this->reladdr
= reg
.reladdr
;
135 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
136 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
142 memset(this, 0, sizeof(*this));
143 this->file
= BAD_FILE
;
144 this->writemask
= WRITEMASK_XYZW
;
152 dst_reg::dst_reg(register_file file
, int reg
)
160 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
167 this->type
= brw_type_for_base_type(type
);
168 this->writemask
= writemask
;
171 dst_reg::dst_reg(struct brw_reg reg
)
176 this->fixed_hw_reg
= reg
;
177 this->type
= reg
.type
;
180 dst_reg::dst_reg(const src_reg
®
)
184 this->file
= reg
.file
;
186 this->reg_offset
= reg
.reg_offset
;
187 this->type
= reg
.type
;
188 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
189 this->reladdr
= reg
.reladdr
;
190 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
194 dst_reg::equals(const dst_reg
&r
) const
196 return (file
== r
.file
&&
198 reg_offset
== r
.reg_offset
&&
200 negate
== r
.negate
&&
202 writemask
== r
.writemask
&&
203 (reladdr
== r
.reladdr
||
204 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
205 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
206 sizeof(fixed_hw_reg
)) == 0);
210 vec4_instruction::is_send_from_grf()
213 case SHADER_OPCODE_SHADER_TIME_ADD
:
214 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
222 vec4_instruction::regs_read(unsigned arg
) const
224 if (src
[arg
].file
== BAD_FILE
)
228 case SHADER_OPCODE_SHADER_TIME_ADD
:
229 return arg
== 0 ? mlen
: 1;
231 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
232 return arg
== 1 ? mlen
: 1;
240 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
242 if (brw
->gen
== 6 && is_math())
245 if (is_send_from_grf())
248 if (!backend_instruction::can_do_source_mods())
255 * Returns how many MRFs an opcode will write over.
257 * Note that this is not the 0 or 1 implied writes in an actual gen
258 * instruction -- the generate_* functions generate additional MOVs
262 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
264 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
267 switch (inst
->opcode
) {
268 case SHADER_OPCODE_RCP
:
269 case SHADER_OPCODE_RSQ
:
270 case SHADER_OPCODE_SQRT
:
271 case SHADER_OPCODE_EXP2
:
272 case SHADER_OPCODE_LOG2
:
273 case SHADER_OPCODE_SIN
:
274 case SHADER_OPCODE_COS
:
276 case SHADER_OPCODE_INT_QUOTIENT
:
277 case SHADER_OPCODE_INT_REMAINDER
:
278 case SHADER_OPCODE_POW
:
280 case VS_OPCODE_URB_WRITE
:
282 case VS_OPCODE_PULL_CONSTANT_LOAD
:
284 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
286 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
288 case GS_OPCODE_URB_WRITE
:
289 case GS_OPCODE_URB_WRITE_ALLOCATE
:
290 case GS_OPCODE_THREAD_END
:
292 case GS_OPCODE_FF_SYNC
:
294 case SHADER_OPCODE_SHADER_TIME_ADD
:
296 case SHADER_OPCODE_TEX
:
297 case SHADER_OPCODE_TXL
:
298 case SHADER_OPCODE_TXD
:
299 case SHADER_OPCODE_TXF
:
300 case SHADER_OPCODE_TXF_CMS
:
301 case SHADER_OPCODE_TXF_MCS
:
302 case SHADER_OPCODE_TXS
:
303 case SHADER_OPCODE_TG4
:
304 case SHADER_OPCODE_TG4_OFFSET
:
305 return inst
->header_present
? 1 : 0;
306 case SHADER_OPCODE_UNTYPED_ATOMIC
:
307 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
310 unreachable("not reached");
315 src_reg::equals(const src_reg
&r
) const
317 return (file
== r
.file
&&
319 reg_offset
== r
.reg_offset
&&
321 negate
== r
.negate
&&
323 swizzle
== r
.swizzle
&&
324 !reladdr
&& !r
.reladdr
&&
325 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
326 sizeof(fixed_hw_reg
)) == 0);
330 vec4_visitor::opt_vector_float()
332 bool progress
= false;
334 int last_reg
= -1, last_reg_offset
= -1;
335 enum register_file last_reg_file
= BAD_FILE
;
337 int remaining_channels
= 0;
340 vec4_instruction
*imm_inst
[4];
342 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
343 if (last_reg
!= inst
->dst
.reg
||
344 last_reg_offset
!= inst
->dst
.reg_offset
||
345 last_reg_file
!= inst
->dst
.file
) {
346 last_reg
= inst
->dst
.reg
;
347 last_reg_offset
= inst
->dst
.reg_offset
;
348 last_reg_file
= inst
->dst
.file
;
349 remaining_channels
= WRITEMASK_XYZW
;
354 if (inst
->opcode
!= BRW_OPCODE_MOV
||
355 inst
->dst
.writemask
== WRITEMASK_XYZW
||
356 inst
->src
[0].file
!= IMM
)
359 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
363 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
365 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
367 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
369 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
372 imm_inst
[inst_count
++] = inst
;
374 remaining_channels
&= ~inst
->dst
.writemask
;
375 if (remaining_channels
== 0) {
376 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
377 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
378 mov
->dst
.writemask
= WRITEMASK_XYZW
;
379 inst
->insert_after(block
, mov
);
382 for (int i
= 0; i
< inst_count
; i
++) {
383 imm_inst
[i
]->remove(block
);
390 invalidate_live_intervals();
395 /* Replaces unused channels of a swizzle with channels that are used.
397 * For instance, this pass transforms
399 * mov vgrf4.yz, vgrf5.wxzy
403 * mov vgrf4.yz, vgrf5.xxzx
405 * This eliminates false uses of some channels, letting dead code elimination
406 * remove the instructions that wrote them.
409 vec4_visitor::opt_reduce_swizzle()
411 bool progress
= false;
413 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
414 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
415 inst
->is_send_from_grf())
420 /* Determine which channels of the sources are read. */
421 switch (inst
->opcode
) {
422 case VEC4_OPCODE_PACK_BYTES
:
424 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
425 * but all four of src1.
427 swizzle
= brw_swizzle_for_size(4);
430 swizzle
= brw_swizzle_for_size(3);
433 swizzle
= brw_swizzle_for_size(2);
436 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
440 /* Update sources' swizzles. */
441 for (int i
= 0; i
< 3; i
++) {
442 if (inst
->src
[i
].file
!= GRF
&&
443 inst
->src
[i
].file
!= ATTR
&&
444 inst
->src
[i
].file
!= UNIFORM
)
447 const unsigned new_swizzle
=
448 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
449 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
450 inst
->src
[i
].swizzle
= new_swizzle
;
457 invalidate_live_intervals();
463 vec4_visitor::split_uniform_registers()
465 /* Prior to this, uniforms have been in an array sized according to
466 * the number of vector uniforms present, sparsely filled (so an
467 * aggregate results in reg indices being skipped over). Now we're
468 * going to cut those aggregates up so each .reg index is one
469 * vector. The goal is to make elimination of unused uniform
470 * components easier later.
472 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
473 for (int i
= 0 ; i
< 3; i
++) {
474 if (inst
->src
[i
].file
!= UNIFORM
)
477 assert(!inst
->src
[i
].reladdr
);
479 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
480 inst
->src
[i
].reg_offset
= 0;
484 /* Update that everything is now vector-sized. */
485 for (int i
= 0; i
< this->uniforms
; i
++) {
486 this->uniform_size
[i
] = 1;
491 vec4_visitor::pack_uniform_registers()
493 bool uniform_used
[this->uniforms
];
494 int new_loc
[this->uniforms
];
495 int new_chan
[this->uniforms
];
497 memset(uniform_used
, 0, sizeof(uniform_used
));
498 memset(new_loc
, 0, sizeof(new_loc
));
499 memset(new_chan
, 0, sizeof(new_chan
));
501 /* Find which uniform vectors are actually used by the program. We
502 * expect unused vector elements when we've moved array access out
503 * to pull constants, and from some GLSL code generators like wine.
505 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
506 for (int i
= 0 ; i
< 3; i
++) {
507 if (inst
->src
[i
].file
!= UNIFORM
)
510 uniform_used
[inst
->src
[i
].reg
] = true;
514 int new_uniform_count
= 0;
516 /* Now, figure out a packing of the live uniform vectors into our
519 for (int src
= 0; src
< uniforms
; src
++) {
520 assert(src
< uniform_array_size
);
521 int size
= this->uniform_vector_size
[src
];
523 if (!uniform_used
[src
]) {
524 this->uniform_vector_size
[src
] = 0;
529 /* Find the lowest place we can slot this uniform in. */
530 for (dst
= 0; dst
< src
; dst
++) {
531 if (this->uniform_vector_size
[dst
] + size
<= 4)
540 new_chan
[src
] = this->uniform_vector_size
[dst
];
542 /* Move the references to the data */
543 for (int j
= 0; j
< size
; j
++) {
544 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
545 stage_prog_data
->param
[src
* 4 + j
];
548 this->uniform_vector_size
[dst
] += size
;
549 this->uniform_vector_size
[src
] = 0;
552 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
555 this->uniforms
= new_uniform_count
;
557 /* Now, update the instructions for our repacked uniforms. */
558 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
559 for (int i
= 0 ; i
< 3; i
++) {
560 int src
= inst
->src
[i
].reg
;
562 if (inst
->src
[i
].file
!= UNIFORM
)
565 inst
->src
[i
].reg
= new_loc
[src
];
566 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
567 new_chan
[src
], new_chan
[src
]);
573 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
575 * While GLSL IR also performs this optimization, we end up with it in
576 * our instruction stream for a couple of reasons. One is that we
577 * sometimes generate silly instructions, for example in array access
578 * where we'll generate "ADD offset, index, base" even if base is 0.
579 * The other is that GLSL IR's constant propagation doesn't track the
580 * components of aggregates, so some VS patterns (initialize matrix to
581 * 0, accumulate in vertex blending factors) end up breaking down to
582 * instructions involving 0.
585 vec4_visitor::opt_algebraic()
587 bool progress
= false;
589 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
590 switch (inst
->opcode
) {
592 if (inst
->src
[0].file
!= IMM
)
595 if (inst
->saturate
) {
596 if (inst
->dst
.type
!= inst
->src
[0].type
)
597 assert(!"unimplemented: saturate mixed types");
599 if (brw_saturate_immediate(inst
->dst
.type
,
600 &inst
->src
[0].fixed_hw_reg
)) {
601 inst
->saturate
= false;
607 case VEC4_OPCODE_UNPACK_UNIFORM
:
608 if (inst
->src
[0].file
!= UNIFORM
) {
609 inst
->opcode
= BRW_OPCODE_MOV
;
615 if (inst
->src
[1].is_zero()) {
616 inst
->opcode
= BRW_OPCODE_MOV
;
617 inst
->src
[1] = src_reg();
623 if (inst
->src
[1].is_zero()) {
624 inst
->opcode
= BRW_OPCODE_MOV
;
625 switch (inst
->src
[0].type
) {
626 case BRW_REGISTER_TYPE_F
:
627 inst
->src
[0] = src_reg(0.0f
);
629 case BRW_REGISTER_TYPE_D
:
630 inst
->src
[0] = src_reg(0);
632 case BRW_REGISTER_TYPE_UD
:
633 inst
->src
[0] = src_reg(0u);
636 unreachable("not reached");
638 inst
->src
[1] = src_reg();
640 } else if (inst
->src
[1].is_one()) {
641 inst
->opcode
= BRW_OPCODE_MOV
;
642 inst
->src
[1] = src_reg();
644 } else if (inst
->src
[1].is_negative_one()) {
645 inst
->opcode
= BRW_OPCODE_MOV
;
646 inst
->src
[0].negate
= !inst
->src
[0].negate
;
647 inst
->src
[1] = src_reg();
652 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
654 inst
->src
[0].negate
&&
655 inst
->src
[1].is_zero()) {
656 inst
->src
[0].abs
= false;
657 inst
->src
[0].negate
= false;
658 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
663 case SHADER_OPCODE_RCP
: {
664 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
665 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
666 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
667 inst
->opcode
= SHADER_OPCODE_RSQ
;
668 inst
->src
[0] = prev
->src
[0];
680 invalidate_live_intervals();
686 * Only a limited number of hardware registers may be used for push
687 * constants, so this turns access to the overflowed constants into
691 vec4_visitor::move_push_constants_to_pull_constants()
693 int pull_constant_loc
[this->uniforms
];
695 /* Only allow 32 registers (256 uniform components) as push constants,
696 * which is the limit on gen6.
698 * If changing this value, note the limitation about total_regs in
701 int max_uniform_components
= 32 * 8;
702 if (this->uniforms
* 4 <= max_uniform_components
)
705 /* Make some sort of choice as to which uniforms get sent to pull
706 * constants. We could potentially do something clever here like
707 * look for the most infrequently used uniform vec4s, but leave
710 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
711 pull_constant_loc
[i
/ 4] = -1;
713 if (i
>= max_uniform_components
) {
714 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
716 /* Try to find an existing copy of this uniform in the pull
717 * constants if it was part of an array access already.
719 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
722 for (matches
= 0; matches
< 4; matches
++) {
723 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
728 pull_constant_loc
[i
/ 4] = j
/ 4;
733 if (pull_constant_loc
[i
/ 4] == -1) {
734 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
735 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
737 for (int j
= 0; j
< 4; j
++) {
738 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
745 /* Now actually rewrite usage of the things we've moved to pull
748 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
749 for (int i
= 0 ; i
< 3; i
++) {
750 if (inst
->src
[i
].file
!= UNIFORM
||
751 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
754 int uniform
= inst
->src
[i
].reg
;
756 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
758 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
759 pull_constant_loc
[uniform
]);
761 inst
->src
[i
].file
= temp
.file
;
762 inst
->src
[i
].reg
= temp
.reg
;
763 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
764 inst
->src
[i
].reladdr
= NULL
;
768 /* Repack push constants to remove the now-unused ones. */
769 pack_uniform_registers();
772 /* Conditions for which we want to avoid setting the dependency control bits */
774 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
776 #define IS_DWORD(reg) \
777 (reg.type == BRW_REGISTER_TYPE_UD || \
778 reg.type == BRW_REGISTER_TYPE_D)
780 /* "When source or destination datatype is 64b or operation is integer DWord
781 * multiply, DepCtrl must not be used."
782 * May apply to future SoCs as well.
784 if (brw
->is_cherryview
) {
785 if (inst
->opcode
== BRW_OPCODE_MUL
&&
786 IS_DWORD(inst
->src
[0]) &&
787 IS_DWORD(inst
->src
[1]))
793 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
799 * In the presence of send messages, totally interrupt dependency
800 * control. They're long enough that the chance of dependency
801 * control around them just doesn't matter.
804 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
805 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
806 * completes the scoreboard clear must have a non-zero execution mask. This
807 * means, if any kind of predication can change the execution mask or channel
808 * enable of the last instruction, the optimization must be avoided. This is
809 * to avoid instructions being shot down the pipeline when no writes are
813 * Dependency control does not work well over math instructions.
814 * NB: Discovered empirically
816 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
820 * Sets the dependency control fields on instructions after register
821 * allocation and before the generator is run.
823 * When you have a sequence of instructions like:
825 * DP4 temp.x vertex uniform[0]
826 * DP4 temp.y vertex uniform[0]
827 * DP4 temp.z vertex uniform[0]
828 * DP4 temp.w vertex uniform[0]
830 * The hardware doesn't know that it can actually run the later instructions
831 * while the previous ones are in flight, producing stalls. However, we have
832 * manual fields we can set in the instructions that let it do so.
835 vec4_visitor::opt_set_dependency_control()
837 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
838 uint8_t grf_channels_written
[BRW_MAX_GRF
];
839 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
840 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
842 assert(prog_data
->total_grf
||
843 !"Must be called after register allocation");
845 foreach_block (block
, cfg
) {
846 memset(last_grf_write
, 0, sizeof(last_grf_write
));
847 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
849 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
850 /* If we read from a register that we were doing dependency control
851 * on, don't do dependency control across the read.
853 for (int i
= 0; i
< 3; i
++) {
854 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
855 if (inst
->src
[i
].file
== GRF
) {
856 last_grf_write
[reg
] = NULL
;
857 } else if (inst
->src
[i
].file
== HW_REG
) {
858 memset(last_grf_write
, 0, sizeof(last_grf_write
));
861 assert(inst
->src
[i
].file
!= MRF
);
864 if (is_dep_ctrl_unsafe(inst
)) {
865 memset(last_grf_write
, 0, sizeof(last_grf_write
));
866 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
870 /* Now, see if we can do dependency control for this instruction
871 * against a previous one writing to its destination.
873 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
874 if (inst
->dst
.file
== GRF
) {
875 if (last_grf_write
[reg
] &&
876 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
877 last_grf_write
[reg
]->no_dd_clear
= true;
878 inst
->no_dd_check
= true;
880 grf_channels_written
[reg
] = 0;
883 last_grf_write
[reg
] = inst
;
884 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
885 } else if (inst
->dst
.file
== MRF
) {
886 if (last_mrf_write
[reg
] &&
887 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
888 last_mrf_write
[reg
]->no_dd_clear
= true;
889 inst
->no_dd_check
= true;
891 mrf_channels_written
[reg
] = 0;
894 last_mrf_write
[reg
] = inst
;
895 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
896 } else if (inst
->dst
.reg
== HW_REG
) {
897 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
898 memset(last_grf_write
, 0, sizeof(last_grf_write
));
899 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
900 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
907 vec4_instruction::can_reswizzle(int dst_writemask
,
911 /* If this instruction sets anything not referenced by swizzle, then we'd
912 * totally break it when we reswizzle.
914 if (dst
.writemask
& ~swizzle_mask
)
924 * For any channels in the swizzle's source that were populated by this
925 * instruction, rewrite the instruction to put the appropriate result directly
928 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
931 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
933 /* Destination write mask doesn't correspond to source swizzle for the dot
934 * product and pack_bytes instructions.
936 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
937 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
938 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
939 for (int i
= 0; i
< 3; i
++) {
940 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
943 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
947 /* Apply the specified swizzle and writemask to the original mask of
948 * written components.
950 dst
.writemask
= dst_writemask
&
951 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
955 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
956 * just written and then MOVed into another reg and making the original write
957 * of the GRF write directly to the final destination instead.
960 vec4_visitor::opt_register_coalesce()
962 bool progress
= false;
965 calculate_live_intervals();
967 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
971 if (inst
->opcode
!= BRW_OPCODE_MOV
||
972 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
974 inst
->src
[0].file
!= GRF
||
975 inst
->dst
.type
!= inst
->src
[0].type
||
976 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
979 bool to_mrf
= (inst
->dst
.file
== MRF
);
981 /* Can't coalesce this GRF if someone else was going to
984 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
985 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
986 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
987 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
990 /* We need to check interference with the final destination between this
991 * instruction and the earliest instruction involved in writing the GRF
992 * we're eliminating. To do that, keep track of which of our source
993 * channels we've seen initialized.
995 const unsigned chans_needed
=
996 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
997 inst
->dst
.writemask
);
998 unsigned chans_remaining
= chans_needed
;
1000 /* Now walk up the instruction stream trying to see if we can rewrite
1001 * everything writing to the temporary to write into the destination
1004 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1005 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1007 _scan_inst
= scan_inst
;
1009 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1010 /* Found something writing to the reg we want to coalesce away. */
1012 /* SEND instructions can't have MRF as a destination. */
1013 if (scan_inst
->mlen
)
1016 if (brw
->gen
== 6) {
1017 /* gen6 math instructions must have the destination be
1018 * GRF, so no compute-to-MRF for them.
1020 if (scan_inst
->is_math()) {
1026 /* If we can't handle the swizzle, bail. */
1027 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1028 inst
->src
[0].swizzle
,
1033 /* This doesn't handle coalescing of multiple registers. */
1034 if (scan_inst
->regs_written
> 1)
1037 /* Mark which channels we found unconditional writes for. */
1038 if (!scan_inst
->predicate
)
1039 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1041 if (chans_remaining
== 0)
1045 /* You can't read from an MRF, so if someone else reads our MRF's
1046 * source GRF that we wanted to rewrite, that stops us. If it's a
1047 * GRF we're trying to coalesce to, we don't actually handle
1048 * rewriting sources so bail in that case as well.
1050 bool interfered
= false;
1051 for (int i
= 0; i
< 3; i
++) {
1052 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1053 scan_inst
->regs_read(i
)))
1059 /* If somebody else writes our destination here, we can't coalesce
1062 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
))
1065 /* Check for reads of the register we're trying to coalesce into. We
1066 * can't go rewriting instructions above that to put some other value
1067 * in the register instead.
1069 if (to_mrf
&& scan_inst
->mlen
> 0) {
1070 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1071 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1075 for (int i
= 0; i
< 3; i
++) {
1076 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1077 scan_inst
->regs_read(i
)))
1085 if (chans_remaining
== 0) {
1086 /* If we've made it here, we have an MOV we want to coalesce out, and
1087 * a scan_inst pointing to the earliest instruction involved in
1088 * computing the value. Now go rewrite the instruction stream
1091 vec4_instruction
*scan_inst
= _scan_inst
;
1092 while (scan_inst
!= inst
) {
1093 if (scan_inst
->dst
.file
== GRF
&&
1094 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1095 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1096 scan_inst
->reswizzle(inst
->dst
.writemask
,
1097 inst
->src
[0].swizzle
);
1098 scan_inst
->dst
.file
= inst
->dst
.file
;
1099 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1100 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1101 scan_inst
->saturate
|= inst
->saturate
;
1103 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1105 inst
->remove(block
);
1111 invalidate_live_intervals();
1117 * Splits virtual GRFs requesting more than one contiguous physical register.
1119 * We initially create large virtual GRFs for temporary structures, arrays,
1120 * and matrices, so that the dereference visitor functions can add reg_offsets
1121 * to work their way down to the actual member being accessed. But when it
1122 * comes to optimization, we'd like to treat each register as individual
1123 * storage if possible.
1125 * So far, the only thing that might prevent splitting is a send message from
1129 vec4_visitor::split_virtual_grfs()
1131 int num_vars
= this->alloc
.count
;
1132 int new_virtual_grf
[num_vars
];
1133 bool split_grf
[num_vars
];
1135 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1137 /* Try to split anything > 0 sized. */
1138 for (int i
= 0; i
< num_vars
; i
++) {
1139 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1142 /* Check that the instructions are compatible with the registers we're trying
1145 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1146 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1147 split_grf
[inst
->dst
.reg
] = false;
1149 for (int i
= 0; i
< 3; i
++) {
1150 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1151 split_grf
[inst
->src
[i
].reg
] = false;
1155 /* Allocate new space for split regs. Note that the virtual
1156 * numbers will be contiguous.
1158 for (int i
= 0; i
< num_vars
; i
++) {
1162 new_virtual_grf
[i
] = alloc
.allocate(1);
1163 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1164 unsigned reg
= alloc
.allocate(1);
1165 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1168 this->alloc
.sizes
[i
] = 1;
1171 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1172 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1173 inst
->dst
.reg_offset
!= 0) {
1174 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1175 inst
->dst
.reg_offset
- 1);
1176 inst
->dst
.reg_offset
= 0;
1178 for (int i
= 0; i
< 3; i
++) {
1179 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1180 inst
->src
[i
].reg_offset
!= 0) {
1181 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1182 inst
->src
[i
].reg_offset
- 1);
1183 inst
->src
[i
].reg_offset
= 0;
1187 invalidate_live_intervals();
1191 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1193 dump_instruction(be_inst
, stderr
);
1197 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1199 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1201 if (inst
->predicate
) {
1202 fprintf(file
, "(%cf0.%d) ",
1203 inst
->predicate_inverse
? '-' : '+',
1207 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1209 fprintf(file
, ".sat");
1210 if (inst
->conditional_mod
) {
1211 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1212 if (!inst
->predicate
&&
1213 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1214 inst
->opcode
!= BRW_OPCODE_IF
&&
1215 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1216 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1221 switch (inst
->dst
.file
) {
1223 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1226 fprintf(file
, "m%d", inst
->dst
.reg
);
1229 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1230 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1232 fprintf(file
, "null");
1234 case BRW_ARF_ADDRESS
:
1235 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1237 case BRW_ARF_ACCUMULATOR
:
1238 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1241 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1242 inst
->dst
.fixed_hw_reg
.subnr
);
1245 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1246 inst
->dst
.fixed_hw_reg
.subnr
);
1250 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1252 if (inst
->dst
.fixed_hw_reg
.subnr
)
1253 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1256 fprintf(file
, "(null)");
1259 fprintf(file
, "???");
1262 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1264 if (inst
->dst
.writemask
& 1)
1266 if (inst
->dst
.writemask
& 2)
1268 if (inst
->dst
.writemask
& 4)
1270 if (inst
->dst
.writemask
& 8)
1273 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1275 if (inst
->src
[0].file
!= BAD_FILE
)
1276 fprintf(file
, ", ");
1278 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1279 if (inst
->src
[i
].negate
)
1281 if (inst
->src
[i
].abs
)
1283 switch (inst
->src
[i
].file
) {
1285 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1288 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1291 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1294 switch (inst
->src
[i
].type
) {
1295 case BRW_REGISTER_TYPE_F
:
1296 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1298 case BRW_REGISTER_TYPE_D
:
1299 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1301 case BRW_REGISTER_TYPE_UD
:
1302 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1304 case BRW_REGISTER_TYPE_VF
:
1305 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1306 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1307 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1308 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1309 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1312 fprintf(file
, "???");
1317 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1319 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1321 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1322 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1324 fprintf(file
, "null");
1326 case BRW_ARF_ADDRESS
:
1327 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1329 case BRW_ARF_ACCUMULATOR
:
1330 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1333 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1334 inst
->src
[i
].fixed_hw_reg
.subnr
);
1337 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1338 inst
->src
[i
].fixed_hw_reg
.subnr
);
1342 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1344 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1345 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1346 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1350 fprintf(file
, "(null)");
1353 fprintf(file
, "???");
1357 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1358 if (inst
->src
[i
].reg_offset
!= 0 &&
1359 inst
->src
[i
].file
== GRF
&&
1360 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1361 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1363 if (inst
->src
[i
].file
!= IMM
) {
1364 static const char *chans
[4] = {"x", "y", "z", "w"};
1366 for (int c
= 0; c
< 4; c
++) {
1367 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1371 if (inst
->src
[i
].abs
)
1374 if (inst
->src
[i
].file
!= IMM
) {
1375 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1378 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1379 fprintf(file
, ", ");
1382 fprintf(file
, "\n");
1386 static inline struct brw_reg
1387 attribute_to_hw_reg(int attr
, bool interleaved
)
1390 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1392 return brw_vec8_grf(attr
, 0);
1397 * Replace each register of type ATTR in this->instructions with a reference
1398 * to a fixed HW register.
1400 * If interleaved is true, then each attribute takes up half a register, with
1401 * register N containing attribute 2*N in its first half and attribute 2*N+1
1402 * in its second half (this corresponds to the payload setup used by geometry
1403 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1404 * false, then each attribute takes up a whole register, with register N
1405 * containing attribute N (this corresponds to the payload setup used by
1406 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1409 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1412 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1413 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1414 if (inst
->dst
.file
== ATTR
) {
1415 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1417 /* All attributes used in the shader need to have been assigned a
1418 * hardware register by the caller
1422 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1423 reg
.type
= inst
->dst
.type
;
1424 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1426 inst
->dst
.file
= HW_REG
;
1427 inst
->dst
.fixed_hw_reg
= reg
;
1430 for (int i
= 0; i
< 3; i
++) {
1431 if (inst
->src
[i
].file
!= ATTR
)
1434 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1436 /* All attributes used in the shader need to have been assigned a
1437 * hardware register by the caller
1441 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1442 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1443 reg
.type
= inst
->src
[i
].type
;
1444 if (inst
->src
[i
].abs
)
1446 if (inst
->src
[i
].negate
)
1449 inst
->src
[i
].file
= HW_REG
;
1450 inst
->src
[i
].fixed_hw_reg
= reg
;
1456 vec4_vs_visitor::setup_attributes(int payload_reg
)
1459 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1460 memset(attribute_map
, 0, sizeof(attribute_map
));
1463 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1464 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1465 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1470 /* VertexID is stored by the VF as the last vertex element, but we
1471 * don't represent it with a flag in inputs_read, so we call it
1474 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1475 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1479 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1481 /* The BSpec says we always have to read at least one thing from
1482 * the VF, and it appears that the hardware wedges otherwise.
1484 if (nr_attributes
== 0)
1487 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1489 unsigned vue_entries
=
1490 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1493 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1495 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1497 return payload_reg
+ nr_attributes
;
1501 vec4_visitor::setup_uniforms(int reg
)
1503 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1505 /* The pre-gen6 VS requires that some push constants get loaded no
1506 * matter what, or the GPU would hang.
1508 if (brw
->gen
< 6 && this->uniforms
== 0) {
1509 assert(this->uniforms
< this->uniform_array_size
);
1510 this->uniform_vector_size
[this->uniforms
] = 1;
1512 stage_prog_data
->param
=
1513 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1514 for (unsigned int i
= 0; i
< 4; i
++) {
1515 unsigned int slot
= this->uniforms
* 4 + i
;
1516 static gl_constant_value zero
= { 0.0 };
1517 stage_prog_data
->param
[slot
] = &zero
;
1523 reg
+= ALIGN(uniforms
, 2) / 2;
1526 stage_prog_data
->nr_params
= this->uniforms
* 4;
1528 prog_data
->base
.curb_read_length
=
1529 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1535 vec4_vs_visitor::setup_payload(void)
1539 /* The payload always contains important data in g0, which contains
1540 * the URB handles that are passed on to the URB write at the end
1541 * of the thread. So, we always start push constants at g1.
1545 reg
= setup_uniforms(reg
);
1547 reg
= setup_attributes(reg
);
1549 this->first_non_payload_grf
= reg
;
1553 vec4_visitor::assign_binding_table_offsets()
1555 assign_common_binding_table_offsets(0);
1559 vec4_visitor::get_timestamp()
1561 assert(brw
->gen
>= 7);
1563 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1568 BRW_REGISTER_TYPE_UD
,
1569 BRW_VERTICAL_STRIDE_0
,
1571 BRW_HORIZONTAL_STRIDE_4
,
1575 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1577 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1578 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1579 * even if it's not enabled in the dispatch.
1581 mov
->force_writemask_all
= true;
1583 return src_reg(dst
);
1587 vec4_visitor::emit_shader_time_begin()
1589 current_annotation
= "shader time start";
1590 shader_start_time
= get_timestamp();
1594 vec4_visitor::emit_shader_time_end()
1596 current_annotation
= "shader time end";
1597 src_reg shader_end_time
= get_timestamp();
1600 /* Check that there weren't any timestamp reset events (assuming these
1601 * were the only two timestamp reads that happened).
1603 src_reg reset_end
= shader_end_time
;
1604 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1605 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1606 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1608 emit(IF(BRW_PREDICATE_NORMAL
));
1610 /* Take the current timestamp and get the delta. */
1611 shader_start_time
.negate
= true;
1612 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1613 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1615 /* If there were no instructions between the two timestamp gets, the diff
1616 * is 2 cycles. Remove that overhead, so I can forget about that when
1617 * trying to determine the time taken for single instructions.
1619 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1621 emit_shader_time_write(st_base
, src_reg(diff
));
1622 emit_shader_time_write(st_written
, src_reg(1u));
1623 emit(BRW_OPCODE_ELSE
);
1624 emit_shader_time_write(st_reset
, src_reg(1u));
1625 emit(BRW_OPCODE_ENDIF
);
1629 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1632 int shader_time_index
=
1633 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1636 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1638 dst_reg offset
= dst
;
1642 offset
.type
= BRW_REGISTER_TYPE_UD
;
1643 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1645 time
.type
= BRW_REGISTER_TYPE_UD
;
1646 emit(MOV(time
, src_reg(value
)));
1648 vec4_instruction
*inst
=
1649 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1656 sanity_param_count
= prog
->Parameters
->NumParameters
;
1658 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1659 emit_shader_time_begin();
1661 assign_binding_table_offsets();
1665 /* Generate VS IR for main(). (the visitor only descends into
1666 * functions called "main").
1669 visit_instructions(shader
->base
.ir
);
1671 emit_program_code();
1675 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1676 setup_uniform_clipplane_values();
1682 /* Before any optimization, push array accesses out to scratch
1683 * space where we need them to be. This pass may allocate new
1684 * virtual GRFs, so we want to do it early. It also makes sure
1685 * that we have reladdr computations available for CSE, since we'll
1686 * often do repeated subexpressions for those.
1689 move_grf_array_access_to_scratch();
1690 move_uniform_array_access_to_pull_constants();
1692 /* The ARB_vertex_program frontend emits pull constant loads directly
1693 * rather than using reladdr, so we don't need to walk through all the
1694 * instructions looking for things to move. There isn't anything.
1696 * We do still need to split things to vec4 size.
1698 split_uniform_registers();
1700 pack_uniform_registers();
1701 move_push_constants_to_pull_constants();
1702 split_virtual_grfs();
1704 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1706 #define OPT(pass, args...) ({ \
1708 bool this_progress = pass(args); \
1710 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1711 char filename[64]; \
1712 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1713 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1715 backend_visitor::dump_instructions(filename); \
1718 progress = progress || this_progress; \
1723 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1725 snprintf(filename
, 64, "%s-%04d-00-start",
1726 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1728 backend_visitor::dump_instructions(filename
);
1739 OPT(opt_reduce_swizzle
);
1740 OPT(dead_code_eliminate
);
1741 OPT(dead_control_flow_eliminate
, this);
1742 OPT(opt_copy_propagation
);
1745 OPT(opt_register_coalesce
);
1750 if (OPT(opt_vector_float
)) {
1752 OPT(opt_copy_propagation
, false);
1753 OPT(opt_copy_propagation
, true);
1754 OPT(dead_code_eliminate
);
1763 /* Debug of register spilling: Go spill everything. */
1764 const int grf_count
= alloc
.count
;
1765 float spill_costs
[alloc
.count
];
1766 bool no_spill
[alloc
.count
];
1767 evaluate_spill_costs(spill_costs
, no_spill
);
1768 for (int i
= 0; i
< grf_count
; i
++) {
1775 while (!reg_allocate()) {
1780 opt_schedule_instructions();
1782 opt_set_dependency_control();
1784 /* If any state parameters were appended, then ParameterValues could have
1785 * been realloced, in which case the driver uniform storage set up by
1786 * _mesa_associate_uniform_storage() would point to freed memory. Make
1787 * sure that didn't happen.
1789 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1794 } /* namespace brw */
1799 * Compile a vertex shader.
1801 * Returns the final assembly and the program's size.
1804 brw_vs_emit(struct brw_context
*brw
,
1805 struct gl_shader_program
*prog
,
1806 struct brw_vs_compile
*c
,
1807 struct brw_vs_prog_data
*prog_data
,
1809 unsigned *final_assembly_size
)
1811 bool start_busy
= false;
1812 double start_time
= 0;
1813 const unsigned *assembly
= NULL
;
1815 if (unlikely(brw
->perf_debug
)) {
1816 start_busy
= (brw
->batch
.last_bo
&&
1817 drm_intel_bo_busy(brw
->batch
.last_bo
));
1818 start_time
= get_time();
1821 struct brw_shader
*shader
= NULL
;
1823 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1825 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1826 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1828 if (prog
&& brw
->gen
>= 8 && brw
->scalar_vs
) {
1829 fs_visitor
v(brw
, mem_ctx
, &c
->key
, prog_data
, prog
, &c
->vp
->program
, 8);
1832 prog
->LinkStatus
= false;
1833 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1836 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1842 fs_generator
g(brw
, mem_ctx
, (void *) &c
->key
, &prog_data
->base
.base
,
1843 &c
->vp
->program
.Base
, v
.promoted_constants
,
1844 v
.runtime_check_aads_emit
, "VS");
1845 if (INTEL_DEBUG
& DEBUG_VS
) {
1846 char *name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1847 prog
->Label
? prog
->Label
: "unnamed",
1849 g
.enable_debug(name
);
1851 g
.generate_code(v
.cfg
, 8);
1852 assembly
= g
.get_assembly(final_assembly_size
);
1855 prog_data
->base
.simd8
= true;
1856 c
->base
.last_scratch
= v
.last_scratch
;
1860 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1863 prog
->LinkStatus
= false;
1864 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1867 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1873 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1874 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
1875 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1878 if (unlikely(brw
->perf_debug
) && shader
) {
1879 if (shader
->compiled_once
) {
1880 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1882 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1883 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1884 (get_time() - start_time
) * 1000);
1886 shader
->compiled_once
= true;
1894 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1895 struct brw_vue_prog_key
*key
,
1896 GLuint id
, struct gl_program
*prog
)
1898 struct brw_context
*brw
= brw_context(ctx
);
1899 key
->program_string_id
= id
;
1901 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
1902 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1903 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1904 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
1905 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1906 key
->tex
.swizzles
[i
] =
1907 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1909 /* Color sampler: assume no swizzling. */
1910 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;