2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(float f
)
79 this->type
= BRW_REGISTER_TYPE_F
;
80 this->fixed_hw_reg
.dw1
.f
= f
;
83 src_reg::src_reg(uint32_t u
)
88 this->type
= BRW_REGISTER_TYPE_UD
;
89 this->fixed_hw_reg
.dw1
.ud
= u
;
92 src_reg::src_reg(int32_t i
)
97 this->type
= BRW_REGISTER_TYPE_D
;
98 this->fixed_hw_reg
.dw1
.d
= i
;
101 src_reg::src_reg(uint8_t vf
[4])
106 this->type
= BRW_REGISTER_TYPE_VF
;
107 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
110 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
115 this->type
= BRW_REGISTER_TYPE_VF
;
116 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
122 src_reg::src_reg(struct brw_reg reg
)
127 this->fixed_hw_reg
= reg
;
128 this->type
= reg
.type
;
131 src_reg::src_reg(const dst_reg
®
)
135 this->file
= reg
.file
;
137 this->reg_offset
= reg
.reg_offset
;
138 this->type
= reg
.type
;
139 this->reladdr
= reg
.reladdr
;
140 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
141 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(register_file file
, int reg
, brw_reg_type type
,
184 this->writemask
= writemask
;
187 dst_reg::dst_reg(struct brw_reg reg
)
192 this->fixed_hw_reg
= reg
;
193 this->type
= reg
.type
;
196 dst_reg::dst_reg(const src_reg
®
)
200 this->file
= reg
.file
;
202 this->reg_offset
= reg
.reg_offset
;
203 this->type
= reg
.type
;
204 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
205 this->reladdr
= reg
.reladdr
;
206 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
210 dst_reg::equals(const dst_reg
&r
) const
212 return (file
== r
.file
&&
214 reg_offset
== r
.reg_offset
&&
216 negate
== r
.negate
&&
218 writemask
== r
.writemask
&&
219 (reladdr
== r
.reladdr
||
220 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
221 ((file
!= HW_REG
&& file
!= IMM
) ||
222 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
223 sizeof(fixed_hw_reg
)) == 0));
227 vec4_instruction::is_send_from_grf()
230 case SHADER_OPCODE_SHADER_TIME_ADD
:
231 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
232 case SHADER_OPCODE_UNTYPED_ATOMIC
:
233 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
234 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
235 case SHADER_OPCODE_TYPED_ATOMIC
:
236 case SHADER_OPCODE_TYPED_SURFACE_READ
:
237 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
245 vec4_instruction::regs_read(unsigned arg
) const
247 if (src
[arg
].file
== BAD_FILE
)
251 case SHADER_OPCODE_SHADER_TIME_ADD
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 return arg
== 0 ? mlen
: 1;
260 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
261 return arg
== 1 ? mlen
: 1;
269 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
271 if (devinfo
->gen
== 6 && is_math())
274 if (is_send_from_grf())
277 if (!backend_instruction::can_do_source_mods())
284 * Returns how many MRFs an opcode will write over.
286 * Note that this is not the 0 or 1 implied writes in an actual gen
287 * instruction -- the generate_* functions generate additional MOVs
291 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
293 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
296 switch (inst
->opcode
) {
297 case SHADER_OPCODE_RCP
:
298 case SHADER_OPCODE_RSQ
:
299 case SHADER_OPCODE_SQRT
:
300 case SHADER_OPCODE_EXP2
:
301 case SHADER_OPCODE_LOG2
:
302 case SHADER_OPCODE_SIN
:
303 case SHADER_OPCODE_COS
:
305 case SHADER_OPCODE_INT_QUOTIENT
:
306 case SHADER_OPCODE_INT_REMAINDER
:
307 case SHADER_OPCODE_POW
:
309 case VS_OPCODE_URB_WRITE
:
311 case VS_OPCODE_PULL_CONSTANT_LOAD
:
313 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
315 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
317 case GS_OPCODE_URB_WRITE
:
318 case GS_OPCODE_URB_WRITE_ALLOCATE
:
319 case GS_OPCODE_THREAD_END
:
321 case GS_OPCODE_FF_SYNC
:
323 case SHADER_OPCODE_SHADER_TIME_ADD
:
325 case SHADER_OPCODE_TEX
:
326 case SHADER_OPCODE_TXL
:
327 case SHADER_OPCODE_TXD
:
328 case SHADER_OPCODE_TXF
:
329 case SHADER_OPCODE_TXF_CMS
:
330 case SHADER_OPCODE_TXF_MCS
:
331 case SHADER_OPCODE_TXS
:
332 case SHADER_OPCODE_TG4
:
333 case SHADER_OPCODE_TG4_OFFSET
:
334 case SHADER_OPCODE_SAMPLEINFO
:
335 case VS_OPCODE_GET_BUFFER_SIZE
:
336 return inst
->header_size
;
338 unreachable("not reached");
343 src_reg::equals(const src_reg
&r
) const
345 return (file
== r
.file
&&
347 reg_offset
== r
.reg_offset
&&
349 negate
== r
.negate
&&
351 swizzle
== r
.swizzle
&&
352 !reladdr
&& !r
.reladdr
&&
353 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
354 sizeof(fixed_hw_reg
)) == 0);
358 vec4_visitor::opt_vector_float()
360 bool progress
= false;
362 int last_reg
= -1, last_reg_offset
= -1;
363 enum register_file last_reg_file
= BAD_FILE
;
365 int remaining_channels
= 0;
368 vec4_instruction
*imm_inst
[4];
370 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
371 if (last_reg
!= inst
->dst
.reg
||
372 last_reg_offset
!= inst
->dst
.reg_offset
||
373 last_reg_file
!= inst
->dst
.file
) {
374 last_reg
= inst
->dst
.reg
;
375 last_reg_offset
= inst
->dst
.reg_offset
;
376 last_reg_file
= inst
->dst
.file
;
377 remaining_channels
= WRITEMASK_XYZW
;
382 if (inst
->opcode
!= BRW_OPCODE_MOV
||
383 inst
->dst
.writemask
== WRITEMASK_XYZW
||
384 inst
->src
[0].file
!= IMM
)
387 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
391 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
393 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
395 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
397 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
400 imm_inst
[inst_count
++] = inst
;
402 remaining_channels
&= ~inst
->dst
.writemask
;
403 if (remaining_channels
== 0) {
404 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
405 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
406 mov
->dst
.writemask
= WRITEMASK_XYZW
;
407 inst
->insert_after(block
, mov
);
410 for (int i
= 0; i
< inst_count
; i
++) {
411 imm_inst
[i
]->remove(block
);
418 invalidate_live_intervals();
423 /* Replaces unused channels of a swizzle with channels that are used.
425 * For instance, this pass transforms
427 * mov vgrf4.yz, vgrf5.wxzy
431 * mov vgrf4.yz, vgrf5.xxzx
433 * This eliminates false uses of some channels, letting dead code elimination
434 * remove the instructions that wrote them.
437 vec4_visitor::opt_reduce_swizzle()
439 bool progress
= false;
441 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
442 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
443 inst
->is_send_from_grf())
448 /* Determine which channels of the sources are read. */
449 switch (inst
->opcode
) {
450 case VEC4_OPCODE_PACK_BYTES
:
452 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
453 * but all four of src1.
455 swizzle
= brw_swizzle_for_size(4);
458 swizzle
= brw_swizzle_for_size(3);
461 swizzle
= brw_swizzle_for_size(2);
464 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
468 /* Update sources' swizzles. */
469 for (int i
= 0; i
< 3; i
++) {
470 if (inst
->src
[i
].file
!= GRF
&&
471 inst
->src
[i
].file
!= ATTR
&&
472 inst
->src
[i
].file
!= UNIFORM
)
475 const unsigned new_swizzle
=
476 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
477 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
478 inst
->src
[i
].swizzle
= new_swizzle
;
485 invalidate_live_intervals();
491 vec4_visitor::split_uniform_registers()
493 /* Prior to this, uniforms have been in an array sized according to
494 * the number of vector uniforms present, sparsely filled (so an
495 * aggregate results in reg indices being skipped over). Now we're
496 * going to cut those aggregates up so each .reg index is one
497 * vector. The goal is to make elimination of unused uniform
498 * components easier later.
500 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
501 for (int i
= 0 ; i
< 3; i
++) {
502 if (inst
->src
[i
].file
!= UNIFORM
)
505 assert(!inst
->src
[i
].reladdr
);
507 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
508 inst
->src
[i
].reg_offset
= 0;
512 /* Update that everything is now vector-sized. */
513 for (int i
= 0; i
< this->uniforms
; i
++) {
514 this->uniform_size
[i
] = 1;
519 vec4_visitor::pack_uniform_registers()
521 bool uniform_used
[this->uniforms
];
522 int new_loc
[this->uniforms
];
523 int new_chan
[this->uniforms
];
525 memset(uniform_used
, 0, sizeof(uniform_used
));
526 memset(new_loc
, 0, sizeof(new_loc
));
527 memset(new_chan
, 0, sizeof(new_chan
));
529 /* Find which uniform vectors are actually used by the program. We
530 * expect unused vector elements when we've moved array access out
531 * to pull constants, and from some GLSL code generators like wine.
533 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
534 for (int i
= 0 ; i
< 3; i
++) {
535 if (inst
->src
[i
].file
!= UNIFORM
)
538 uniform_used
[inst
->src
[i
].reg
] = true;
542 int new_uniform_count
= 0;
544 /* Now, figure out a packing of the live uniform vectors into our
547 for (int src
= 0; src
< uniforms
; src
++) {
548 assert(src
< uniform_array_size
);
549 int size
= this->uniform_vector_size
[src
];
551 if (!uniform_used
[src
]) {
552 this->uniform_vector_size
[src
] = 0;
557 /* Find the lowest place we can slot this uniform in. */
558 for (dst
= 0; dst
< src
; dst
++) {
559 if (this->uniform_vector_size
[dst
] + size
<= 4)
568 new_chan
[src
] = this->uniform_vector_size
[dst
];
570 /* Move the references to the data */
571 for (int j
= 0; j
< size
; j
++) {
572 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
573 stage_prog_data
->param
[src
* 4 + j
];
576 this->uniform_vector_size
[dst
] += size
;
577 this->uniform_vector_size
[src
] = 0;
580 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
583 this->uniforms
= new_uniform_count
;
585 /* Now, update the instructions for our repacked uniforms. */
586 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
587 for (int i
= 0 ; i
< 3; i
++) {
588 int src
= inst
->src
[i
].reg
;
590 if (inst
->src
[i
].file
!= UNIFORM
)
593 inst
->src
[i
].reg
= new_loc
[src
];
594 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
595 new_chan
[src
], new_chan
[src
]);
601 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
603 * While GLSL IR also performs this optimization, we end up with it in
604 * our instruction stream for a couple of reasons. One is that we
605 * sometimes generate silly instructions, for example in array access
606 * where we'll generate "ADD offset, index, base" even if base is 0.
607 * The other is that GLSL IR's constant propagation doesn't track the
608 * components of aggregates, so some VS patterns (initialize matrix to
609 * 0, accumulate in vertex blending factors) end up breaking down to
610 * instructions involving 0.
613 vec4_visitor::opt_algebraic()
615 bool progress
= false;
617 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
618 switch (inst
->opcode
) {
620 if (inst
->src
[0].file
!= IMM
)
623 if (inst
->saturate
) {
624 if (inst
->dst
.type
!= inst
->src
[0].type
)
625 assert(!"unimplemented: saturate mixed types");
627 if (brw_saturate_immediate(inst
->dst
.type
,
628 &inst
->src
[0].fixed_hw_reg
)) {
629 inst
->saturate
= false;
635 case VEC4_OPCODE_UNPACK_UNIFORM
:
636 if (inst
->src
[0].file
!= UNIFORM
) {
637 inst
->opcode
= BRW_OPCODE_MOV
;
643 if (inst
->src
[1].is_zero()) {
644 inst
->opcode
= BRW_OPCODE_MOV
;
645 inst
->src
[1] = src_reg();
651 if (inst
->src
[1].is_zero()) {
652 inst
->opcode
= BRW_OPCODE_MOV
;
653 switch (inst
->src
[0].type
) {
654 case BRW_REGISTER_TYPE_F
:
655 inst
->src
[0] = src_reg(0.0f
);
657 case BRW_REGISTER_TYPE_D
:
658 inst
->src
[0] = src_reg(0);
660 case BRW_REGISTER_TYPE_UD
:
661 inst
->src
[0] = src_reg(0u);
664 unreachable("not reached");
666 inst
->src
[1] = src_reg();
668 } else if (inst
->src
[1].is_one()) {
669 inst
->opcode
= BRW_OPCODE_MOV
;
670 inst
->src
[1] = src_reg();
672 } else if (inst
->src
[1].is_negative_one()) {
673 inst
->opcode
= BRW_OPCODE_MOV
;
674 inst
->src
[0].negate
= !inst
->src
[0].negate
;
675 inst
->src
[1] = src_reg();
680 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
682 inst
->src
[0].negate
&&
683 inst
->src
[1].is_zero()) {
684 inst
->src
[0].abs
= false;
685 inst
->src
[0].negate
= false;
686 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
691 case SHADER_OPCODE_RCP
: {
692 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
693 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
694 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
695 inst
->opcode
= SHADER_OPCODE_RSQ
;
696 inst
->src
[0] = prev
->src
[0];
702 case SHADER_OPCODE_BROADCAST
:
703 if (is_uniform(inst
->src
[0]) ||
704 inst
->src
[1].is_zero()) {
705 inst
->opcode
= BRW_OPCODE_MOV
;
706 inst
->src
[1] = src_reg();
707 inst
->force_writemask_all
= true;
718 invalidate_live_intervals();
724 * Only a limited number of hardware registers may be used for push
725 * constants, so this turns access to the overflowed constants into
729 vec4_visitor::move_push_constants_to_pull_constants()
731 int pull_constant_loc
[this->uniforms
];
733 /* Only allow 32 registers (256 uniform components) as push constants,
734 * which is the limit on gen6.
736 * If changing this value, note the limitation about total_regs in
739 int max_uniform_components
= 32 * 8;
740 if (this->uniforms
* 4 <= max_uniform_components
)
743 /* Make some sort of choice as to which uniforms get sent to pull
744 * constants. We could potentially do something clever here like
745 * look for the most infrequently used uniform vec4s, but leave
748 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
749 pull_constant_loc
[i
/ 4] = -1;
751 if (i
>= max_uniform_components
) {
752 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
754 /* Try to find an existing copy of this uniform in the pull
755 * constants if it was part of an array access already.
757 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
760 for (matches
= 0; matches
< 4; matches
++) {
761 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
766 pull_constant_loc
[i
/ 4] = j
/ 4;
771 if (pull_constant_loc
[i
/ 4] == -1) {
772 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
773 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
775 for (int j
= 0; j
< 4; j
++) {
776 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
783 /* Now actually rewrite usage of the things we've moved to pull
786 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
787 for (int i
= 0 ; i
< 3; i
++) {
788 if (inst
->src
[i
].file
!= UNIFORM
||
789 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
792 int uniform
= inst
->src
[i
].reg
;
794 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
796 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
797 pull_constant_loc
[uniform
]);
799 inst
->src
[i
].file
= temp
.file
;
800 inst
->src
[i
].reg
= temp
.reg
;
801 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
802 inst
->src
[i
].reladdr
= NULL
;
806 /* Repack push constants to remove the now-unused ones. */
807 pack_uniform_registers();
810 /* Conditions for which we want to avoid setting the dependency control bits */
812 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
814 #define IS_DWORD(reg) \
815 (reg.type == BRW_REGISTER_TYPE_UD || \
816 reg.type == BRW_REGISTER_TYPE_D)
818 /* "When source or destination datatype is 64b or operation is integer DWord
819 * multiply, DepCtrl must not be used."
820 * May apply to future SoCs as well.
822 if (devinfo
->is_cherryview
) {
823 if (inst
->opcode
== BRW_OPCODE_MUL
&&
824 IS_DWORD(inst
->src
[0]) &&
825 IS_DWORD(inst
->src
[1]))
830 if (devinfo
->gen
>= 8) {
831 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
837 * In the presence of send messages, totally interrupt dependency
838 * control. They're long enough that the chance of dependency
839 * control around them just doesn't matter.
842 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
843 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
844 * completes the scoreboard clear must have a non-zero execution mask. This
845 * means, if any kind of predication can change the execution mask or channel
846 * enable of the last instruction, the optimization must be avoided. This is
847 * to avoid instructions being shot down the pipeline when no writes are
851 * Dependency control does not work well over math instructions.
852 * NB: Discovered empirically
854 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
858 * Sets the dependency control fields on instructions after register
859 * allocation and before the generator is run.
861 * When you have a sequence of instructions like:
863 * DP4 temp.x vertex uniform[0]
864 * DP4 temp.y vertex uniform[0]
865 * DP4 temp.z vertex uniform[0]
866 * DP4 temp.w vertex uniform[0]
868 * The hardware doesn't know that it can actually run the later instructions
869 * while the previous ones are in flight, producing stalls. However, we have
870 * manual fields we can set in the instructions that let it do so.
873 vec4_visitor::opt_set_dependency_control()
875 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
876 uint8_t grf_channels_written
[BRW_MAX_GRF
];
877 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
878 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
880 assert(prog_data
->total_grf
||
881 !"Must be called after register allocation");
883 foreach_block (block
, cfg
) {
884 memset(last_grf_write
, 0, sizeof(last_grf_write
));
885 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
887 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
888 /* If we read from a register that we were doing dependency control
889 * on, don't do dependency control across the read.
891 for (int i
= 0; i
< 3; i
++) {
892 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
893 if (inst
->src
[i
].file
== GRF
) {
894 last_grf_write
[reg
] = NULL
;
895 } else if (inst
->src
[i
].file
== HW_REG
) {
896 memset(last_grf_write
, 0, sizeof(last_grf_write
));
899 assert(inst
->src
[i
].file
!= MRF
);
902 if (is_dep_ctrl_unsafe(inst
)) {
903 memset(last_grf_write
, 0, sizeof(last_grf_write
));
904 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
908 /* Now, see if we can do dependency control for this instruction
909 * against a previous one writing to its destination.
911 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
912 if (inst
->dst
.file
== GRF
) {
913 if (last_grf_write
[reg
] &&
914 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
915 last_grf_write
[reg
]->no_dd_clear
= true;
916 inst
->no_dd_check
= true;
918 grf_channels_written
[reg
] = 0;
921 last_grf_write
[reg
] = inst
;
922 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
923 } else if (inst
->dst
.file
== MRF
) {
924 if (last_mrf_write
[reg
] &&
925 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
926 last_mrf_write
[reg
]->no_dd_clear
= true;
927 inst
->no_dd_check
= true;
929 mrf_channels_written
[reg
] = 0;
932 last_mrf_write
[reg
] = inst
;
933 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
934 } else if (inst
->dst
.reg
== HW_REG
) {
935 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
936 memset(last_grf_write
, 0, sizeof(last_grf_write
));
937 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
938 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
945 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
950 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
951 * or writemasking are not allowed.
953 if (devinfo
->gen
== 6 && is_math() &&
954 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
957 /* If this instruction sets anything not referenced by swizzle, then we'd
958 * totally break it when we reswizzle.
960 if (dst
.writemask
& ~swizzle_mask
)
966 /* We can't use swizzles on the accumulator and that's really the only
967 * HW_REG we would care to reswizzle so just disallow them all.
969 for (int i
= 0; i
< 3; i
++) {
970 if (src
[i
].file
== HW_REG
)
978 * For any channels in the swizzle's source that were populated by this
979 * instruction, rewrite the instruction to put the appropriate result directly
982 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
985 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
987 /* Destination write mask doesn't correspond to source swizzle for the dot
988 * product and pack_bytes instructions.
990 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
991 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
992 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
993 for (int i
= 0; i
< 3; i
++) {
994 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
997 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1001 /* Apply the specified swizzle and writemask to the original mask of
1002 * written components.
1004 dst
.writemask
= dst_writemask
&
1005 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1009 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1010 * just written and then MOVed into another reg and making the original write
1011 * of the GRF write directly to the final destination instead.
1014 vec4_visitor::opt_register_coalesce()
1016 bool progress
= false;
1019 calculate_live_intervals();
1021 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1025 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1026 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1028 inst
->src
[0].file
!= GRF
||
1029 inst
->dst
.type
!= inst
->src
[0].type
||
1030 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1033 /* Remove no-op MOVs */
1034 if (inst
->dst
.file
== inst
->src
[0].file
&&
1035 inst
->dst
.reg
== inst
->src
[0].reg
&&
1036 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1037 bool is_nop_mov
= true;
1039 for (unsigned c
= 0; c
< 4; c
++) {
1040 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1043 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1050 inst
->remove(block
);
1055 bool to_mrf
= (inst
->dst
.file
== MRF
);
1057 /* Can't coalesce this GRF if someone else was going to
1060 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1063 /* We need to check interference with the final destination between this
1064 * instruction and the earliest instruction involved in writing the GRF
1065 * we're eliminating. To do that, keep track of which of our source
1066 * channels we've seen initialized.
1068 const unsigned chans_needed
=
1069 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1070 inst
->dst
.writemask
);
1071 unsigned chans_remaining
= chans_needed
;
1073 /* Now walk up the instruction stream trying to see if we can rewrite
1074 * everything writing to the temporary to write into the destination
1077 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1078 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1080 _scan_inst
= scan_inst
;
1082 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1083 /* Found something writing to the reg we want to coalesce away. */
1085 /* SEND instructions can't have MRF as a destination. */
1086 if (scan_inst
->mlen
)
1089 if (devinfo
->gen
== 6) {
1090 /* gen6 math instructions must have the destination be
1091 * GRF, so no compute-to-MRF for them.
1093 if (scan_inst
->is_math()) {
1099 /* This doesn't handle saturation on the instruction we
1100 * want to coalesce away if the register types do not match.
1101 * But if scan_inst is a non type-converting 'mov', we can fix
1104 if (inst
->saturate
&&
1105 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1106 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1107 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1110 /* If we can't handle the swizzle, bail. */
1111 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1112 inst
->src
[0].swizzle
,
1117 /* This doesn't handle coalescing of multiple registers. */
1118 if (scan_inst
->regs_written
> 1)
1121 /* Mark which channels we found unconditional writes for. */
1122 if (!scan_inst
->predicate
)
1123 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1125 if (chans_remaining
== 0)
1129 /* You can't read from an MRF, so if someone else reads our MRF's
1130 * source GRF that we wanted to rewrite, that stops us. If it's a
1131 * GRF we're trying to coalesce to, we don't actually handle
1132 * rewriting sources so bail in that case as well.
1134 bool interfered
= false;
1135 for (int i
= 0; i
< 3; i
++) {
1136 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1137 scan_inst
->regs_read(i
)))
1143 /* If somebody else writes the same channels of our destination here,
1144 * we can't coalesce before that.
1146 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1147 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1151 /* Check for reads of the register we're trying to coalesce into. We
1152 * can't go rewriting instructions above that to put some other value
1153 * in the register instead.
1155 if (to_mrf
&& scan_inst
->mlen
> 0) {
1156 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1157 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1161 for (int i
= 0; i
< 3; i
++) {
1162 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1163 scan_inst
->regs_read(i
)))
1171 if (chans_remaining
== 0) {
1172 /* If we've made it here, we have an MOV we want to coalesce out, and
1173 * a scan_inst pointing to the earliest instruction involved in
1174 * computing the value. Now go rewrite the instruction stream
1177 vec4_instruction
*scan_inst
= _scan_inst
;
1178 while (scan_inst
!= inst
) {
1179 if (scan_inst
->dst
.file
== GRF
&&
1180 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1181 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1182 scan_inst
->reswizzle(inst
->dst
.writemask
,
1183 inst
->src
[0].swizzle
);
1184 scan_inst
->dst
.file
= inst
->dst
.file
;
1185 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1186 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1187 if (inst
->saturate
&&
1188 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1189 /* If we have reached this point, scan_inst is a non
1190 * type-converting 'mov' and we can modify its register types
1191 * to match the ones in inst. Otherwise, we could have an
1192 * incorrect saturation result.
1194 scan_inst
->dst
.type
= inst
->dst
.type
;
1195 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1197 scan_inst
->saturate
|= inst
->saturate
;
1199 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1201 inst
->remove(block
);
1207 invalidate_live_intervals();
1213 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1214 * flow. We could probably do better here with some form of divergence
1218 vec4_visitor::eliminate_find_live_channel()
1220 bool progress
= false;
1223 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1224 switch (inst
->opcode
) {
1230 case BRW_OPCODE_ENDIF
:
1231 case BRW_OPCODE_WHILE
:
1235 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1237 inst
->opcode
= BRW_OPCODE_MOV
;
1238 inst
->src
[0] = src_reg(0);
1239 inst
->force_writemask_all
= true;
1253 * Splits virtual GRFs requesting more than one contiguous physical register.
1255 * We initially create large virtual GRFs for temporary structures, arrays,
1256 * and matrices, so that the dereference visitor functions can add reg_offsets
1257 * to work their way down to the actual member being accessed. But when it
1258 * comes to optimization, we'd like to treat each register as individual
1259 * storage if possible.
1261 * So far, the only thing that might prevent splitting is a send message from
1265 vec4_visitor::split_virtual_grfs()
1267 int num_vars
= this->alloc
.count
;
1268 int new_virtual_grf
[num_vars
];
1269 bool split_grf
[num_vars
];
1271 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1273 /* Try to split anything > 0 sized. */
1274 for (int i
= 0; i
< num_vars
; i
++) {
1275 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1278 /* Check that the instructions are compatible with the registers we're trying
1281 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1282 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1283 split_grf
[inst
->dst
.reg
] = false;
1285 for (int i
= 0; i
< 3; i
++) {
1286 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1287 split_grf
[inst
->src
[i
].reg
] = false;
1291 /* Allocate new space for split regs. Note that the virtual
1292 * numbers will be contiguous.
1294 for (int i
= 0; i
< num_vars
; i
++) {
1298 new_virtual_grf
[i
] = alloc
.allocate(1);
1299 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1300 unsigned reg
= alloc
.allocate(1);
1301 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1304 this->alloc
.sizes
[i
] = 1;
1307 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1308 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1309 inst
->dst
.reg_offset
!= 0) {
1310 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1311 inst
->dst
.reg_offset
- 1);
1312 inst
->dst
.reg_offset
= 0;
1314 for (int i
= 0; i
< 3; i
++) {
1315 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1316 inst
->src
[i
].reg_offset
!= 0) {
1317 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1318 inst
->src
[i
].reg_offset
- 1);
1319 inst
->src
[i
].reg_offset
= 0;
1323 invalidate_live_intervals();
1327 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1329 dump_instruction(be_inst
, stderr
);
1333 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1335 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1337 if (inst
->predicate
) {
1338 fprintf(file
, "(%cf0.%d) ",
1339 inst
->predicate_inverse
? '-' : '+',
1343 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1345 fprintf(file
, ".sat");
1346 if (inst
->conditional_mod
) {
1347 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1348 if (!inst
->predicate
&&
1349 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1350 inst
->opcode
!= BRW_OPCODE_IF
&&
1351 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1352 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1357 switch (inst
->dst
.file
) {
1359 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1362 fprintf(file
, "m%d", inst
->dst
.reg
);
1365 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1366 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1368 fprintf(file
, "null");
1370 case BRW_ARF_ADDRESS
:
1371 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1373 case BRW_ARF_ACCUMULATOR
:
1374 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1377 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1378 inst
->dst
.fixed_hw_reg
.subnr
);
1381 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1382 inst
->dst
.fixed_hw_reg
.subnr
);
1386 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1388 if (inst
->dst
.fixed_hw_reg
.subnr
)
1389 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1392 fprintf(file
, "(null)");
1395 fprintf(file
, "???");
1398 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1400 if (inst
->dst
.writemask
& 1)
1402 if (inst
->dst
.writemask
& 2)
1404 if (inst
->dst
.writemask
& 4)
1406 if (inst
->dst
.writemask
& 8)
1409 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1411 if (inst
->src
[0].file
!= BAD_FILE
)
1412 fprintf(file
, ", ");
1414 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1415 if (inst
->src
[i
].negate
)
1417 if (inst
->src
[i
].abs
)
1419 switch (inst
->src
[i
].file
) {
1421 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1424 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1427 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1430 switch (inst
->src
[i
].type
) {
1431 case BRW_REGISTER_TYPE_F
:
1432 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1434 case BRW_REGISTER_TYPE_D
:
1435 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1437 case BRW_REGISTER_TYPE_UD
:
1438 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1440 case BRW_REGISTER_TYPE_VF
:
1441 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1442 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1443 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1444 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1445 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1448 fprintf(file
, "???");
1453 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1455 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1457 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1458 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1460 fprintf(file
, "null");
1462 case BRW_ARF_ADDRESS
:
1463 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1465 case BRW_ARF_ACCUMULATOR
:
1466 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1469 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1470 inst
->src
[i
].fixed_hw_reg
.subnr
);
1473 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1474 inst
->src
[i
].fixed_hw_reg
.subnr
);
1478 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1480 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1481 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1482 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1486 fprintf(file
, "(null)");
1489 fprintf(file
, "???");
1493 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1494 if (inst
->src
[i
].reg_offset
!= 0 &&
1495 inst
->src
[i
].file
== GRF
&&
1496 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1497 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1499 if (inst
->src
[i
].file
!= IMM
) {
1500 static const char *chans
[4] = {"x", "y", "z", "w"};
1502 for (int c
= 0; c
< 4; c
++) {
1503 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1507 if (inst
->src
[i
].abs
)
1510 if (inst
->src
[i
].file
!= IMM
) {
1511 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1514 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1515 fprintf(file
, ", ");
1518 fprintf(file
, "\n");
1522 static inline struct brw_reg
1523 attribute_to_hw_reg(int attr
, bool interleaved
)
1526 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1528 return brw_vec8_grf(attr
, 0);
1533 * Replace each register of type ATTR in this->instructions with a reference
1534 * to a fixed HW register.
1536 * If interleaved is true, then each attribute takes up half a register, with
1537 * register N containing attribute 2*N in its first half and attribute 2*N+1
1538 * in its second half (this corresponds to the payload setup used by geometry
1539 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1540 * false, then each attribute takes up a whole register, with register N
1541 * containing attribute N (this corresponds to the payload setup used by
1542 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1545 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1548 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1549 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1550 if (inst
->dst
.file
== ATTR
) {
1551 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1553 /* All attributes used in the shader need to have been assigned a
1554 * hardware register by the caller
1558 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1559 reg
.type
= inst
->dst
.type
;
1560 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1562 inst
->dst
.file
= HW_REG
;
1563 inst
->dst
.fixed_hw_reg
= reg
;
1566 for (int i
= 0; i
< 3; i
++) {
1567 if (inst
->src
[i
].file
!= ATTR
)
1570 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1572 /* All attributes used in the shader need to have been assigned a
1573 * hardware register by the caller
1577 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1578 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1579 reg
.type
= inst
->src
[i
].type
;
1580 if (inst
->src
[i
].abs
)
1582 if (inst
->src
[i
].negate
)
1585 inst
->src
[i
].file
= HW_REG
;
1586 inst
->src
[i
].fixed_hw_reg
= reg
;
1592 vec4_vs_visitor::setup_attributes(int payload_reg
)
1595 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1596 memset(attribute_map
, 0, sizeof(attribute_map
));
1599 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1600 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1601 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1606 /* VertexID is stored by the VF as the last vertex element, but we
1607 * don't represent it with a flag in inputs_read, so we call it
1610 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1611 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1615 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1617 /* The BSpec says we always have to read at least one thing from
1618 * the VF, and it appears that the hardware wedges otherwise.
1620 if (nr_attributes
== 0)
1623 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1625 unsigned vue_entries
=
1626 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1628 if (devinfo
->gen
== 6)
1629 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1631 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1633 return payload_reg
+ nr_attributes
;
1637 vec4_visitor::setup_uniforms(int reg
)
1639 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1641 /* The pre-gen6 VS requires that some push constants get loaded no
1642 * matter what, or the GPU would hang.
1644 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1645 assert(this->uniforms
< this->uniform_array_size
);
1646 this->uniform_vector_size
[this->uniforms
] = 1;
1648 stage_prog_data
->param
=
1649 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1650 for (unsigned int i
= 0; i
< 4; i
++) {
1651 unsigned int slot
= this->uniforms
* 4 + i
;
1652 static gl_constant_value zero
= { 0.0 };
1653 stage_prog_data
->param
[slot
] = &zero
;
1659 reg
+= ALIGN(uniforms
, 2) / 2;
1662 stage_prog_data
->nr_params
= this->uniforms
* 4;
1664 prog_data
->base
.curb_read_length
=
1665 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1671 vec4_vs_visitor::setup_payload(void)
1675 /* The payload always contains important data in g0, which contains
1676 * the URB handles that are passed on to the URB write at the end
1677 * of the thread. So, we always start push constants at g1.
1681 reg
= setup_uniforms(reg
);
1683 reg
= setup_attributes(reg
);
1685 this->first_non_payload_grf
= reg
;
1689 vec4_visitor::assign_binding_table_offsets()
1691 assign_common_binding_table_offsets(0);
1695 vec4_visitor::get_timestamp()
1697 assert(devinfo
->gen
>= 7);
1699 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1704 BRW_REGISTER_TYPE_UD
,
1705 BRW_VERTICAL_STRIDE_0
,
1707 BRW_HORIZONTAL_STRIDE_4
,
1711 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1713 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1714 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1715 * even if it's not enabled in the dispatch.
1717 mov
->force_writemask_all
= true;
1719 return src_reg(dst
);
1723 vec4_visitor::emit_shader_time_begin()
1725 current_annotation
= "shader time start";
1726 shader_start_time
= get_timestamp();
1730 vec4_visitor::emit_shader_time_end()
1732 current_annotation
= "shader time end";
1733 src_reg shader_end_time
= get_timestamp();
1736 /* Check that there weren't any timestamp reset events (assuming these
1737 * were the only two timestamp reads that happened).
1739 src_reg reset_end
= shader_end_time
;
1740 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1741 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1742 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1744 emit(IF(BRW_PREDICATE_NORMAL
));
1746 /* Take the current timestamp and get the delta. */
1747 shader_start_time
.negate
= true;
1748 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1749 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1751 /* If there were no instructions between the two timestamp gets, the diff
1752 * is 2 cycles. Remove that overhead, so I can forget about that when
1753 * trying to determine the time taken for single instructions.
1755 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1757 emit_shader_time_write(0, src_reg(diff
));
1758 emit_shader_time_write(1, src_reg(1u));
1759 emit(BRW_OPCODE_ELSE
);
1760 emit_shader_time_write(2, src_reg(1u));
1761 emit(BRW_OPCODE_ENDIF
);
1765 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1768 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1770 dst_reg offset
= dst
;
1774 offset
.type
= BRW_REGISTER_TYPE_UD
;
1775 int index
= shader_time_index
* 3 + shader_time_subindex
;
1776 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1778 time
.type
= BRW_REGISTER_TYPE_UD
;
1779 emit(MOV(time
, src_reg(value
)));
1781 vec4_instruction
*inst
=
1782 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1790 compiler
->glsl_compiler_options
[stage
].NirOptions
!= NULL
;
1792 sanity_param_count
= prog
->Parameters
->NumParameters
;
1794 if (shader_time_index
>= 0)
1795 emit_shader_time_begin();
1797 assign_binding_table_offsets();
1802 assert(prog
->nir
!= NULL
);
1806 } else if (shader
) {
1807 /* Generate VS IR for main(). (the visitor only descends into
1808 * functions called "main").
1810 visit_instructions(shader
->base
.ir
);
1812 emit_program_code();
1820 /* Before any optimization, push array accesses out to scratch
1821 * space where we need them to be. This pass may allocate new
1822 * virtual GRFs, so we want to do it early. It also makes sure
1823 * that we have reladdr computations available for CSE, since we'll
1824 * often do repeated subexpressions for those.
1826 if (shader
|| use_vec4_nir
) {
1827 move_grf_array_access_to_scratch();
1828 move_uniform_array_access_to_pull_constants();
1830 /* The ARB_vertex_program frontend emits pull constant loads directly
1831 * rather than using reladdr, so we don't need to walk through all the
1832 * instructions looking for things to move. There isn't anything.
1834 * We do still need to split things to vec4 size.
1836 split_uniform_registers();
1838 pack_uniform_registers();
1839 move_push_constants_to_pull_constants();
1840 split_virtual_grfs();
1842 #define OPT(pass, args...) ({ \
1844 bool this_progress = pass(args); \
1846 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1847 char filename[64]; \
1848 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1849 stage_abbrev, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1851 backend_shader::dump_instructions(filename); \
1854 progress = progress || this_progress; \
1859 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1861 snprintf(filename
, 64, "%s-%04d-00-start",
1862 stage_abbrev
, shader_prog
? shader_prog
->Name
: 0);
1864 backend_shader::dump_instructions(filename
);
1875 OPT(opt_reduce_swizzle
);
1876 OPT(dead_code_eliminate
);
1877 OPT(dead_control_flow_eliminate
, this);
1878 OPT(opt_copy_propagation
);
1881 OPT(opt_register_coalesce
);
1882 OPT(eliminate_find_live_channel
);
1887 if (OPT(opt_vector_float
)) {
1889 OPT(opt_copy_propagation
, false);
1890 OPT(opt_copy_propagation
, true);
1891 OPT(dead_code_eliminate
);
1899 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1900 /* Debug of register spilling: Go spill everything. */
1901 const int grf_count
= alloc
.count
;
1902 float spill_costs
[alloc
.count
];
1903 bool no_spill
[alloc
.count
];
1904 evaluate_spill_costs(spill_costs
, no_spill
);
1905 for (int i
= 0; i
< grf_count
; i
++) {
1912 bool allocated_without_spills
= reg_allocate();
1914 if (!allocated_without_spills
) {
1915 compiler
->shader_perf_log(log_data
,
1916 "%s shader triggered register spilling. "
1917 "Try reducing the number of live vec4 values "
1918 "to improve performance.\n",
1921 while (!reg_allocate()) {
1927 opt_schedule_instructions();
1929 opt_set_dependency_control();
1931 if (last_scratch
> 0) {
1932 prog_data
->base
.total_scratch
=
1933 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1936 /* If any state parameters were appended, then ParameterValues could have
1937 * been realloced, in which case the driver uniform storage set up by
1938 * _mesa_associate_uniform_storage() would point to freed memory. Make
1939 * sure that didn't happen.
1941 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1946 } /* namespace brw */
1951 * Compile a vertex shader.
1953 * Returns the final assembly and the program's size.
1956 brw_vs_emit(struct brw_context
*brw
,
1958 const struct brw_vs_prog_key
*key
,
1959 struct brw_vs_prog_data
*prog_data
,
1960 struct gl_vertex_program
*vp
,
1961 struct gl_shader_program
*prog
,
1962 unsigned *final_assembly_size
)
1964 const unsigned *assembly
= NULL
;
1966 struct brw_shader
*shader
= NULL
;
1968 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1971 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1972 st_index
= brw_get_shader_time_index(brw
, prog
, &vp
->Base
, ST_VS
);
1974 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1975 brw_dump_ir("vertex", prog
, &shader
->base
, &vp
->Base
);
1977 if (!vp
->Base
.nir
&&
1978 (brw
->intelScreen
->compiler
->scalar_vs
||
1979 brw
->intelScreen
->compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].NirOptions
!= NULL
)) {
1980 /* Normally we generate NIR in LinkShader() or
1981 * ProgramStringNotify(), but Mesa's fixed-function vertex program
1982 * handling doesn't notify the driver at all. Just do it here, at
1983 * the last minute, even though it's lame.
1985 assert(vp
->Base
.Id
== 0 && prog
== NULL
);
1987 brw_create_nir(brw
, NULL
, &vp
->Base
, MESA_SHADER_VERTEX
,
1988 brw
->intelScreen
->compiler
->scalar_vs
);
1991 if (brw
->intelScreen
->compiler
->scalar_vs
) {
1992 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1994 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
1995 mem_ctx
, MESA_SHADER_VERTEX
, key
,
1996 &prog_data
->base
.base
, prog
, &vp
->Base
,
1998 if (!v
.run_vs(brw_select_clip_planes(&brw
->ctx
))) {
2000 prog
->LinkStatus
= false;
2001 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
2004 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
2010 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
2011 mem_ctx
, (void *) key
, &prog_data
->base
.base
,
2012 &vp
->Base
, v
.promoted_constants
,
2013 v
.runtime_check_aads_emit
, "VS");
2014 if (INTEL_DEBUG
& DEBUG_VS
) {
2017 name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
2018 prog
->Label
? prog
->Label
: "unnamed",
2021 name
= ralloc_asprintf(mem_ctx
, "vertex program %d",
2024 g
.enable_debug(name
);
2026 g
.generate_code(v
.cfg
, 8);
2027 assembly
= g
.get_assembly(final_assembly_size
);
2031 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2033 vec4_vs_visitor
v(brw
->intelScreen
->compiler
, brw
, key
, prog_data
,
2034 vp
, prog
, brw_select_clip_planes(&brw
->ctx
),
2036 !_mesa_is_gles3(&brw
->ctx
));
2039 prog
->LinkStatus
= false;
2040 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
2043 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
2049 vec4_generator
g(brw
->intelScreen
->compiler
, brw
,
2050 prog
, &vp
->Base
, &prog_data
->base
,
2051 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
2052 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);