2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
31 #include "program/prog_parameter.h"
33 #define MAX_INSTRUCTION (1 << 30)
42 memset(this, 0, sizeof(*this));
44 this->file
= BAD_FILE
;
47 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
53 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
54 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
56 this->swizzle
= BRW_SWIZZLE_XYZW
;
58 this->type
= brw_type_for_base_type(type
);
61 /** Generic unset register constructor. */
67 src_reg::src_reg(struct ::brw_reg reg
) :
74 src_reg::src_reg(const dst_reg
®
) :
77 this->reladdr
= reg
.reladdr
;
78 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
84 memset(this, 0, sizeof(*this));
85 this->file
= BAD_FILE
;
86 this->writemask
= WRITEMASK_XYZW
;
94 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
102 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
109 this->type
= brw_type_for_base_type(type
);
110 this->writemask
= writemask
;
113 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
121 this->writemask
= writemask
;
124 dst_reg::dst_reg(struct ::brw_reg reg
) :
127 this->reg_offset
= 0;
128 this->reladdr
= NULL
;
131 dst_reg::dst_reg(const src_reg
®
) :
134 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
135 this->reladdr
= reg
.reladdr
;
139 dst_reg::equals(const dst_reg
&r
) const
141 return (this->backend_reg::equals(r
) &&
142 (reladdr
== r
.reladdr
||
143 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
147 vec4_instruction::is_send_from_grf()
150 case SHADER_OPCODE_SHADER_TIME_ADD
:
151 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
152 case SHADER_OPCODE_UNTYPED_ATOMIC
:
153 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
154 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
155 case SHADER_OPCODE_TYPED_ATOMIC
:
156 case SHADER_OPCODE_TYPED_SURFACE_READ
:
157 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
158 case VEC4_OPCODE_URB_READ
:
159 case TCS_OPCODE_URB_WRITE
:
160 case TCS_OPCODE_RELEASE_INPUT
:
161 case SHADER_OPCODE_BARRIER
:
169 * Returns true if this instruction's sources and destinations cannot
170 * safely be the same register.
172 * In most cases, a register can be written over safely by the same
173 * instruction that is its last use. For a single instruction, the
174 * sources are dereferenced before writing of the destination starts
177 * However, there are a few cases where this can be problematic:
179 * - Virtual opcodes that translate to multiple instructions in the
180 * code generator: if src == dst and one instruction writes the
181 * destination before a later instruction reads the source, then
182 * src will have been clobbered.
184 * The register allocator uses this information to set up conflicts between
185 * GRF sources and the destination.
188 vec4_instruction::has_source_and_destination_hazard() const
191 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
192 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
193 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
201 vec4_instruction::regs_read(unsigned arg
) const
203 if (src
[arg
].file
== BAD_FILE
)
207 case SHADER_OPCODE_SHADER_TIME_ADD
:
208 case SHADER_OPCODE_UNTYPED_ATOMIC
:
209 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
210 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
211 case SHADER_OPCODE_TYPED_ATOMIC
:
212 case SHADER_OPCODE_TYPED_SURFACE_READ
:
213 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
214 case TCS_OPCODE_URB_WRITE
:
215 return arg
== 0 ? mlen
: 1;
217 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
218 return arg
== 1 ? mlen
: 1;
226 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
228 if (devinfo
->gen
== 6 && is_math())
231 if (is_send_from_grf())
234 if (!backend_instruction::can_do_source_mods())
241 vec4_instruction::can_change_types() const
243 return dst
.type
== src
[0].type
&&
244 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
245 (opcode
== BRW_OPCODE_MOV
||
246 (opcode
== BRW_OPCODE_SEL
&&
247 dst
.type
== src
[1].type
&&
248 predicate
!= BRW_PREDICATE_NONE
&&
249 !src
[1].abs
&& !src
[1].negate
));
253 * Returns how many MRFs an opcode will write over.
255 * Note that this is not the 0 or 1 implied writes in an actual gen
256 * instruction -- the generate_* functions generate additional MOVs
260 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
262 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
265 switch (inst
->opcode
) {
266 case SHADER_OPCODE_RCP
:
267 case SHADER_OPCODE_RSQ
:
268 case SHADER_OPCODE_SQRT
:
269 case SHADER_OPCODE_EXP2
:
270 case SHADER_OPCODE_LOG2
:
271 case SHADER_OPCODE_SIN
:
272 case SHADER_OPCODE_COS
:
274 case SHADER_OPCODE_INT_QUOTIENT
:
275 case SHADER_OPCODE_INT_REMAINDER
:
276 case SHADER_OPCODE_POW
:
278 case VS_OPCODE_URB_WRITE
:
279 case TCS_OPCODE_THREAD_END
:
281 case VS_OPCODE_PULL_CONSTANT_LOAD
:
283 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
285 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
287 case GS_OPCODE_URB_WRITE
:
288 case GS_OPCODE_URB_WRITE_ALLOCATE
:
289 case GS_OPCODE_THREAD_END
:
291 case GS_OPCODE_FF_SYNC
:
293 case TCS_OPCODE_URB_WRITE
:
295 case SHADER_OPCODE_SHADER_TIME_ADD
:
297 case SHADER_OPCODE_TEX
:
298 case SHADER_OPCODE_TXL
:
299 case SHADER_OPCODE_TXD
:
300 case SHADER_OPCODE_TXF
:
301 case SHADER_OPCODE_TXF_CMS
:
302 case SHADER_OPCODE_TXF_CMS_W
:
303 case SHADER_OPCODE_TXF_MCS
:
304 case SHADER_OPCODE_TXS
:
305 case SHADER_OPCODE_TG4
:
306 case SHADER_OPCODE_TG4_OFFSET
:
307 case SHADER_OPCODE_SAMPLEINFO
:
308 case VS_OPCODE_GET_BUFFER_SIZE
:
309 return inst
->header_size
;
311 unreachable("not reached");
316 src_reg::equals(const src_reg
&r
) const
318 return (this->backend_reg::equals(r
) &&
319 !reladdr
&& !r
.reladdr
);
323 vec4_visitor::opt_vector_float()
325 bool progress
= false;
327 int last_reg
= -1, last_reg_offset
= -1;
328 enum brw_reg_file last_reg_file
= BAD_FILE
;
330 int remaining_channels
= 0;
333 vec4_instruction
*imm_inst
[4];
335 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
336 if (last_reg
!= inst
->dst
.nr
||
337 last_reg_offset
!= inst
->dst
.reg_offset
||
338 last_reg_file
!= inst
->dst
.file
) {
339 last_reg
= inst
->dst
.nr
;
340 last_reg_offset
= inst
->dst
.reg_offset
;
341 last_reg_file
= inst
->dst
.file
;
342 remaining_channels
= WRITEMASK_XYZW
;
347 if (inst
->opcode
!= BRW_OPCODE_MOV
||
348 inst
->dst
.writemask
== WRITEMASK_XYZW
||
349 inst
->src
[0].file
!= IMM
)
352 int vf
= brw_float_to_vf(inst
->src
[0].f
);
356 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
358 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
360 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
362 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
365 imm_inst
[inst_count
++] = inst
;
367 remaining_channels
&= ~inst
->dst
.writemask
;
368 if (remaining_channels
== 0) {
370 memcpy(&vf
, imm
, sizeof(vf
));
371 vec4_instruction
*mov
= MOV(inst
->dst
, brw_imm_vf(vf
));
372 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
373 mov
->dst
.writemask
= WRITEMASK_XYZW
;
374 inst
->insert_after(block
, mov
);
377 for (int i
= 0; i
< inst_count
; i
++) {
378 imm_inst
[i
]->remove(block
);
385 invalidate_live_intervals();
390 /* Replaces unused channels of a swizzle with channels that are used.
392 * For instance, this pass transforms
394 * mov vgrf4.yz, vgrf5.wxzy
398 * mov vgrf4.yz, vgrf5.xxzx
400 * This eliminates false uses of some channels, letting dead code elimination
401 * remove the instructions that wrote them.
404 vec4_visitor::opt_reduce_swizzle()
406 bool progress
= false;
408 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
409 if (inst
->dst
.file
== BAD_FILE
||
410 inst
->dst
.file
== ARF
||
411 inst
->dst
.file
== FIXED_GRF
||
412 inst
->is_send_from_grf())
417 /* Determine which channels of the sources are read. */
418 switch (inst
->opcode
) {
419 case VEC4_OPCODE_PACK_BYTES
:
421 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
422 * but all four of src1.
424 swizzle
= brw_swizzle_for_size(4);
427 swizzle
= brw_swizzle_for_size(3);
430 swizzle
= brw_swizzle_for_size(2);
433 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
437 /* Update sources' swizzles. */
438 for (int i
= 0; i
< 3; i
++) {
439 if (inst
->src
[i
].file
!= VGRF
&&
440 inst
->src
[i
].file
!= ATTR
&&
441 inst
->src
[i
].file
!= UNIFORM
)
444 const unsigned new_swizzle
=
445 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
446 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
447 inst
->src
[i
].swizzle
= new_swizzle
;
454 invalidate_live_intervals();
460 vec4_visitor::split_uniform_registers()
462 /* Prior to this, uniforms have been in an array sized according to
463 * the number of vector uniforms present, sparsely filled (so an
464 * aggregate results in reg indices being skipped over). Now we're
465 * going to cut those aggregates up so each .nr index is one
466 * vector. The goal is to make elimination of unused uniform
467 * components easier later.
469 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
470 for (int i
= 0 ; i
< 3; i
++) {
471 if (inst
->src
[i
].file
!= UNIFORM
)
474 assert(!inst
->src
[i
].reladdr
);
476 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
477 inst
->src
[i
].reg_offset
= 0;
483 vec4_visitor::pack_uniform_registers()
485 uint8_t chans_used
[this->uniforms
];
486 int new_loc
[this->uniforms
];
487 int new_chan
[this->uniforms
];
489 memset(chans_used
, 0, sizeof(chans_used
));
490 memset(new_loc
, 0, sizeof(new_loc
));
491 memset(new_chan
, 0, sizeof(new_chan
));
493 /* Find which uniform vectors are actually used by the program. We
494 * expect unused vector elements when we've moved array access out
495 * to pull constants, and from some GLSL code generators like wine.
497 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
499 switch (inst
->opcode
) {
500 case VEC4_OPCODE_PACK_BYTES
:
512 readmask
= inst
->dst
.writemask
;
516 for (int i
= 0 ; i
< 3; i
++) {
517 if (inst
->src
[i
].file
!= UNIFORM
)
520 int reg
= inst
->src
[i
].nr
;
521 for (int c
= 0; c
< 4; c
++) {
522 if (!(readmask
& (1 << c
)))
525 chans_used
[reg
] = MAX2(chans_used
[reg
],
526 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
531 int new_uniform_count
= 0;
533 /* Now, figure out a packing of the live uniform vectors into our
536 for (int src
= 0; src
< uniforms
; src
++) {
537 int size
= chans_used
[src
];
543 /* Find the lowest place we can slot this uniform in. */
544 for (dst
= 0; dst
< src
; dst
++) {
545 if (chans_used
[dst
] + size
<= 4)
554 new_chan
[src
] = chans_used
[dst
];
556 /* Move the references to the data */
557 for (int j
= 0; j
< size
; j
++) {
558 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
559 stage_prog_data
->param
[src
* 4 + j
];
562 chans_used
[dst
] += size
;
566 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
569 this->uniforms
= new_uniform_count
;
571 /* Now, update the instructions for our repacked uniforms. */
572 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
573 for (int i
= 0 ; i
< 3; i
++) {
574 int src
= inst
->src
[i
].nr
;
576 if (inst
->src
[i
].file
!= UNIFORM
)
579 inst
->src
[i
].nr
= new_loc
[src
];
580 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
581 new_chan
[src
], new_chan
[src
]);
587 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
589 * While GLSL IR also performs this optimization, we end up with it in
590 * our instruction stream for a couple of reasons. One is that we
591 * sometimes generate silly instructions, for example in array access
592 * where we'll generate "ADD offset, index, base" even if base is 0.
593 * The other is that GLSL IR's constant propagation doesn't track the
594 * components of aggregates, so some VS patterns (initialize matrix to
595 * 0, accumulate in vertex blending factors) end up breaking down to
596 * instructions involving 0.
599 vec4_visitor::opt_algebraic()
601 bool progress
= false;
603 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
604 switch (inst
->opcode
) {
606 if (inst
->src
[0].file
!= IMM
)
609 if (inst
->saturate
) {
610 if (inst
->dst
.type
!= inst
->src
[0].type
)
611 assert(!"unimplemented: saturate mixed types");
613 if (brw_saturate_immediate(inst
->dst
.type
,
614 &inst
->src
[0].as_brw_reg())) {
615 inst
->saturate
= false;
621 case VEC4_OPCODE_UNPACK_UNIFORM
:
622 if (inst
->src
[0].file
!= UNIFORM
) {
623 inst
->opcode
= BRW_OPCODE_MOV
;
629 if (inst
->src
[1].is_zero()) {
630 inst
->opcode
= BRW_OPCODE_MOV
;
631 inst
->src
[1] = src_reg();
637 if (inst
->src
[1].is_zero()) {
638 inst
->opcode
= BRW_OPCODE_MOV
;
639 switch (inst
->src
[0].type
) {
640 case BRW_REGISTER_TYPE_F
:
641 inst
->src
[0] = brw_imm_f(0.0f
);
643 case BRW_REGISTER_TYPE_D
:
644 inst
->src
[0] = brw_imm_d(0);
646 case BRW_REGISTER_TYPE_UD
:
647 inst
->src
[0] = brw_imm_ud(0u);
650 unreachable("not reached");
652 inst
->src
[1] = src_reg();
654 } else if (inst
->src
[1].is_one()) {
655 inst
->opcode
= BRW_OPCODE_MOV
;
656 inst
->src
[1] = src_reg();
658 } else if (inst
->src
[1].is_negative_one()) {
659 inst
->opcode
= BRW_OPCODE_MOV
;
660 inst
->src
[0].negate
= !inst
->src
[0].negate
;
661 inst
->src
[1] = src_reg();
666 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
668 inst
->src
[0].negate
&&
669 inst
->src
[1].is_zero()) {
670 inst
->src
[0].abs
= false;
671 inst
->src
[0].negate
= false;
672 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
677 case SHADER_OPCODE_RCP
: {
678 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
679 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
680 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
681 inst
->opcode
= SHADER_OPCODE_RSQ
;
682 inst
->src
[0] = prev
->src
[0];
688 case SHADER_OPCODE_BROADCAST
:
689 if (is_uniform(inst
->src
[0]) ||
690 inst
->src
[1].is_zero()) {
691 inst
->opcode
= BRW_OPCODE_MOV
;
692 inst
->src
[1] = src_reg();
693 inst
->force_writemask_all
= true;
704 invalidate_live_intervals();
710 * Only a limited number of hardware registers may be used for push
711 * constants, so this turns access to the overflowed constants into
715 vec4_visitor::move_push_constants_to_pull_constants()
717 int pull_constant_loc
[this->uniforms
];
719 /* Only allow 32 registers (256 uniform components) as push constants,
720 * which is the limit on gen6.
722 * If changing this value, note the limitation about total_regs in
725 int max_uniform_components
= 32 * 8;
726 if (this->uniforms
* 4 <= max_uniform_components
)
729 /* Make some sort of choice as to which uniforms get sent to pull
730 * constants. We could potentially do something clever here like
731 * look for the most infrequently used uniform vec4s, but leave
734 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
735 pull_constant_loc
[i
/ 4] = -1;
737 if (i
>= max_uniform_components
) {
738 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
740 /* Try to find an existing copy of this uniform in the pull
741 * constants if it was part of an array access already.
743 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
746 for (matches
= 0; matches
< 4; matches
++) {
747 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
752 pull_constant_loc
[i
/ 4] = j
/ 4;
757 if (pull_constant_loc
[i
/ 4] == -1) {
758 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
759 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
761 for (int j
= 0; j
< 4; j
++) {
762 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
769 /* Now actually rewrite usage of the things we've moved to pull
772 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
773 for (int i
= 0 ; i
< 3; i
++) {
774 if (inst
->src
[i
].file
!= UNIFORM
||
775 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
778 int uniform
= inst
->src
[i
].nr
;
780 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
782 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
783 pull_constant_loc
[uniform
], src_reg());
785 inst
->src
[i
].file
= temp
.file
;
786 inst
->src
[i
].nr
= temp
.nr
;
787 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
788 inst
->src
[i
].reladdr
= NULL
;
792 /* Repack push constants to remove the now-unused ones. */
793 pack_uniform_registers();
796 /* Conditions for which we want to avoid setting the dependency control bits */
798 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
800 #define IS_DWORD(reg) \
801 (reg.type == BRW_REGISTER_TYPE_UD || \
802 reg.type == BRW_REGISTER_TYPE_D)
804 /* "When source or destination datatype is 64b or operation is integer DWord
805 * multiply, DepCtrl must not be used."
806 * May apply to future SoCs as well.
808 if (devinfo
->is_cherryview
) {
809 if (inst
->opcode
== BRW_OPCODE_MUL
&&
810 IS_DWORD(inst
->src
[0]) &&
811 IS_DWORD(inst
->src
[1]))
816 if (devinfo
->gen
>= 8) {
817 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
823 * In the presence of send messages, totally interrupt dependency
824 * control. They're long enough that the chance of dependency
825 * control around them just doesn't matter.
828 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
829 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
830 * completes the scoreboard clear must have a non-zero execution mask. This
831 * means, if any kind of predication can change the execution mask or channel
832 * enable of the last instruction, the optimization must be avoided. This is
833 * to avoid instructions being shot down the pipeline when no writes are
837 * Dependency control does not work well over math instructions.
838 * NB: Discovered empirically
840 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
844 * Sets the dependency control fields on instructions after register
845 * allocation and before the generator is run.
847 * When you have a sequence of instructions like:
849 * DP4 temp.x vertex uniform[0]
850 * DP4 temp.y vertex uniform[0]
851 * DP4 temp.z vertex uniform[0]
852 * DP4 temp.w vertex uniform[0]
854 * The hardware doesn't know that it can actually run the later instructions
855 * while the previous ones are in flight, producing stalls. However, we have
856 * manual fields we can set in the instructions that let it do so.
859 vec4_visitor::opt_set_dependency_control()
861 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
862 uint8_t grf_channels_written
[BRW_MAX_GRF
];
863 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
864 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
866 assert(prog_data
->total_grf
||
867 !"Must be called after register allocation");
869 foreach_block (block
, cfg
) {
870 memset(last_grf_write
, 0, sizeof(last_grf_write
));
871 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
873 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
874 /* If we read from a register that we were doing dependency control
875 * on, don't do dependency control across the read.
877 for (int i
= 0; i
< 3; i
++) {
878 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
879 if (inst
->src
[i
].file
== VGRF
) {
880 last_grf_write
[reg
] = NULL
;
881 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
882 memset(last_grf_write
, 0, sizeof(last_grf_write
));
885 assert(inst
->src
[i
].file
!= MRF
);
888 if (is_dep_ctrl_unsafe(inst
)) {
889 memset(last_grf_write
, 0, sizeof(last_grf_write
));
890 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
894 /* Now, see if we can do dependency control for this instruction
895 * against a previous one writing to its destination.
897 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
898 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
899 if (last_grf_write
[reg
] &&
900 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
901 last_grf_write
[reg
]->no_dd_clear
= true;
902 inst
->no_dd_check
= true;
904 grf_channels_written
[reg
] = 0;
907 last_grf_write
[reg
] = inst
;
908 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
909 } else if (inst
->dst
.file
== MRF
) {
910 if (last_mrf_write
[reg
] &&
911 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
912 last_mrf_write
[reg
]->no_dd_clear
= true;
913 inst
->no_dd_check
= true;
915 mrf_channels_written
[reg
] = 0;
918 last_mrf_write
[reg
] = inst
;
919 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
926 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
931 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
932 * or writemasking are not allowed.
934 if (devinfo
->gen
== 6 && is_math() &&
935 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
938 /* If this instruction sets anything not referenced by swizzle, then we'd
939 * totally break it when we reswizzle.
941 if (dst
.writemask
& ~swizzle_mask
)
947 for (int i
= 0; i
< 3; i
++) {
948 if (src
[i
].is_accumulator())
956 * For any channels in the swizzle's source that were populated by this
957 * instruction, rewrite the instruction to put the appropriate result directly
960 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
963 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
965 /* Destination write mask doesn't correspond to source swizzle for the dot
966 * product and pack_bytes instructions.
968 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
969 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
970 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
971 for (int i
= 0; i
< 3; i
++) {
972 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
975 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
979 /* Apply the specified swizzle and writemask to the original mask of
980 * written components.
982 dst
.writemask
= dst_writemask
&
983 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
987 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
988 * just written and then MOVed into another reg and making the original write
989 * of the GRF write directly to the final destination instead.
992 vec4_visitor::opt_register_coalesce()
994 bool progress
= false;
997 calculate_live_intervals();
999 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1003 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1004 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1006 inst
->src
[0].file
!= VGRF
||
1007 inst
->dst
.type
!= inst
->src
[0].type
||
1008 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1011 /* Remove no-op MOVs */
1012 if (inst
->dst
.file
== inst
->src
[0].file
&&
1013 inst
->dst
.nr
== inst
->src
[0].nr
&&
1014 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1015 bool is_nop_mov
= true;
1017 for (unsigned c
= 0; c
< 4; c
++) {
1018 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1021 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1028 inst
->remove(block
);
1033 bool to_mrf
= (inst
->dst
.file
== MRF
);
1035 /* Can't coalesce this GRF if someone else was going to
1038 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1041 /* We need to check interference with the final destination between this
1042 * instruction and the earliest instruction involved in writing the GRF
1043 * we're eliminating. To do that, keep track of which of our source
1044 * channels we've seen initialized.
1046 const unsigned chans_needed
=
1047 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1048 inst
->dst
.writemask
);
1049 unsigned chans_remaining
= chans_needed
;
1051 /* Now walk up the instruction stream trying to see if we can rewrite
1052 * everything writing to the temporary to write into the destination
1055 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1056 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1058 _scan_inst
= scan_inst
;
1060 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1061 /* Found something writing to the reg we want to coalesce away. */
1063 /* SEND instructions can't have MRF as a destination. */
1064 if (scan_inst
->mlen
)
1067 if (devinfo
->gen
== 6) {
1068 /* gen6 math instructions must have the destination be
1069 * VGRF, so no compute-to-MRF for them.
1071 if (scan_inst
->is_math()) {
1077 /* This doesn't handle saturation on the instruction we
1078 * want to coalesce away if the register types do not match.
1079 * But if scan_inst is a non type-converting 'mov', we can fix
1082 if (inst
->saturate
&&
1083 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1084 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1085 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1088 /* If we can't handle the swizzle, bail. */
1089 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1090 inst
->src
[0].swizzle
,
1095 /* This doesn't handle coalescing of multiple registers. */
1096 if (scan_inst
->regs_written
> 1)
1099 /* Mark which channels we found unconditional writes for. */
1100 if (!scan_inst
->predicate
)
1101 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1103 if (chans_remaining
== 0)
1107 /* You can't read from an MRF, so if someone else reads our MRF's
1108 * source GRF that we wanted to rewrite, that stops us. If it's a
1109 * GRF we're trying to coalesce to, we don't actually handle
1110 * rewriting sources so bail in that case as well.
1112 bool interfered
= false;
1113 for (int i
= 0; i
< 3; i
++) {
1114 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1115 scan_inst
->regs_read(i
)))
1121 /* If somebody else writes the same channels of our destination here,
1122 * we can't coalesce before that.
1124 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1125 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1129 /* Check for reads of the register we're trying to coalesce into. We
1130 * can't go rewriting instructions above that to put some other value
1131 * in the register instead.
1133 if (to_mrf
&& scan_inst
->mlen
> 0) {
1134 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1135 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1139 for (int i
= 0; i
< 3; i
++) {
1140 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1141 scan_inst
->regs_read(i
)))
1149 if (chans_remaining
== 0) {
1150 /* If we've made it here, we have an MOV we want to coalesce out, and
1151 * a scan_inst pointing to the earliest instruction involved in
1152 * computing the value. Now go rewrite the instruction stream
1155 vec4_instruction
*scan_inst
= _scan_inst
;
1156 while (scan_inst
!= inst
) {
1157 if (scan_inst
->dst
.file
== VGRF
&&
1158 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1159 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1160 scan_inst
->reswizzle(inst
->dst
.writemask
,
1161 inst
->src
[0].swizzle
);
1162 scan_inst
->dst
.file
= inst
->dst
.file
;
1163 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1164 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1165 if (inst
->saturate
&&
1166 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1167 /* If we have reached this point, scan_inst is a non
1168 * type-converting 'mov' and we can modify its register types
1169 * to match the ones in inst. Otherwise, we could have an
1170 * incorrect saturation result.
1172 scan_inst
->dst
.type
= inst
->dst
.type
;
1173 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1175 scan_inst
->saturate
|= inst
->saturate
;
1177 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1179 inst
->remove(block
);
1185 invalidate_live_intervals();
1191 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1192 * flow. We could probably do better here with some form of divergence
1196 vec4_visitor::eliminate_find_live_channel()
1198 bool progress
= false;
1201 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1202 switch (inst
->opcode
) {
1208 case BRW_OPCODE_ENDIF
:
1209 case BRW_OPCODE_WHILE
:
1213 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1215 inst
->opcode
= BRW_OPCODE_MOV
;
1216 inst
->src
[0] = brw_imm_d(0);
1217 inst
->force_writemask_all
= true;
1231 * Splits virtual GRFs requesting more than one contiguous physical register.
1233 * We initially create large virtual GRFs for temporary structures, arrays,
1234 * and matrices, so that the dereference visitor functions can add reg_offsets
1235 * to work their way down to the actual member being accessed. But when it
1236 * comes to optimization, we'd like to treat each register as individual
1237 * storage if possible.
1239 * So far, the only thing that might prevent splitting is a send message from
1243 vec4_visitor::split_virtual_grfs()
1245 int num_vars
= this->alloc
.count
;
1246 int new_virtual_grf
[num_vars
];
1247 bool split_grf
[num_vars
];
1249 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1251 /* Try to split anything > 0 sized. */
1252 for (int i
= 0; i
< num_vars
; i
++) {
1253 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1256 /* Check that the instructions are compatible with the registers we're trying
1259 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1260 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1261 split_grf
[inst
->dst
.nr
] = false;
1263 for (int i
= 0; i
< 3; i
++) {
1264 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1265 split_grf
[inst
->src
[i
].nr
] = false;
1269 /* Allocate new space for split regs. Note that the virtual
1270 * numbers will be contiguous.
1272 for (int i
= 0; i
< num_vars
; i
++) {
1276 new_virtual_grf
[i
] = alloc
.allocate(1);
1277 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1278 unsigned reg
= alloc
.allocate(1);
1279 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1282 this->alloc
.sizes
[i
] = 1;
1285 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1286 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1287 inst
->dst
.reg_offset
!= 0) {
1288 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1289 inst
->dst
.reg_offset
- 1);
1290 inst
->dst
.reg_offset
= 0;
1292 for (int i
= 0; i
< 3; i
++) {
1293 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1294 inst
->src
[i
].reg_offset
!= 0) {
1295 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1296 inst
->src
[i
].reg_offset
- 1);
1297 inst
->src
[i
].reg_offset
= 0;
1301 invalidate_live_intervals();
1305 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1307 dump_instruction(be_inst
, stderr
);
1311 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1313 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1315 if (inst
->predicate
) {
1316 fprintf(file
, "(%cf0.%d%s) ",
1317 inst
->predicate_inverse
? '-' : '+',
1319 pred_ctrl_align16
[inst
->predicate
]);
1322 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1324 fprintf(file
, ".sat");
1325 if (inst
->conditional_mod
) {
1326 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1327 if (!inst
->predicate
&&
1328 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1329 inst
->opcode
!= BRW_OPCODE_IF
&&
1330 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1331 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1336 switch (inst
->dst
.file
) {
1338 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1341 fprintf(file
, "g%d", inst
->dst
.nr
);
1344 fprintf(file
, "m%d", inst
->dst
.nr
);
1347 switch (inst
->dst
.nr
) {
1349 fprintf(file
, "null");
1351 case BRW_ARF_ADDRESS
:
1352 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1354 case BRW_ARF_ACCUMULATOR
:
1355 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1358 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1361 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1364 if (inst
->dst
.subnr
)
1365 fprintf(file
, "+%d", inst
->dst
.subnr
);
1368 fprintf(file
, "(null)");
1373 unreachable("not reached");
1375 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1377 if (inst
->dst
.writemask
& 1)
1379 if (inst
->dst
.writemask
& 2)
1381 if (inst
->dst
.writemask
& 4)
1383 if (inst
->dst
.writemask
& 8)
1386 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1388 if (inst
->src
[0].file
!= BAD_FILE
)
1389 fprintf(file
, ", ");
1391 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1392 if (inst
->src
[i
].negate
)
1394 if (inst
->src
[i
].abs
)
1396 switch (inst
->src
[i
].file
) {
1398 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1401 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1404 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1407 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1410 switch (inst
->src
[i
].type
) {
1411 case BRW_REGISTER_TYPE_F
:
1412 fprintf(file
, "%fF", inst
->src
[i
].f
);
1414 case BRW_REGISTER_TYPE_D
:
1415 fprintf(file
, "%dD", inst
->src
[i
].d
);
1417 case BRW_REGISTER_TYPE_UD
:
1418 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1420 case BRW_REGISTER_TYPE_VF
:
1421 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1422 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1423 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1424 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1425 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1428 fprintf(file
, "???");
1433 switch (inst
->src
[i
].nr
) {
1435 fprintf(file
, "null");
1437 case BRW_ARF_ADDRESS
:
1438 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1440 case BRW_ARF_ACCUMULATOR
:
1441 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1444 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1447 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1450 if (inst
->src
[i
].subnr
)
1451 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1454 fprintf(file
, "(null)");
1457 unreachable("not reached");
1460 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1461 if (inst
->src
[i
].reg_offset
!= 0 &&
1462 inst
->src
[i
].file
== VGRF
&&
1463 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1464 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1466 if (inst
->src
[i
].file
!= IMM
) {
1467 static const char *chans
[4] = {"x", "y", "z", "w"};
1469 for (int c
= 0; c
< 4; c
++) {
1470 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1474 if (inst
->src
[i
].abs
)
1477 if (inst
->src
[i
].file
!= IMM
) {
1478 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1481 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1482 fprintf(file
, ", ");
1485 if (inst
->force_writemask_all
)
1486 fprintf(file
, " NoMask");
1488 fprintf(file
, "\n");
1492 static inline struct brw_reg
1493 attribute_to_hw_reg(int attr
, bool interleaved
)
1496 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1498 return brw_vec8_grf(attr
, 0);
1503 * Replace each register of type ATTR in this->instructions with a reference
1504 * to a fixed HW register.
1506 * If interleaved is true, then each attribute takes up half a register, with
1507 * register N containing attribute 2*N in its first half and attribute 2*N+1
1508 * in its second half (this corresponds to the payload setup used by geometry
1509 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1510 * false, then each attribute takes up a whole register, with register N
1511 * containing attribute N (this corresponds to the payload setup used by
1512 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1515 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1518 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1519 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1520 if (inst
->dst
.file
== ATTR
) {
1521 int grf
= attribute_map
[inst
->dst
.nr
+ inst
->dst
.reg_offset
];
1523 /* All attributes used in the shader need to have been assigned a
1524 * hardware register by the caller
1528 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1529 reg
.type
= inst
->dst
.type
;
1530 reg
.writemask
= inst
->dst
.writemask
;
1535 for (int i
= 0; i
< 3; i
++) {
1536 if (inst
->src
[i
].file
!= ATTR
)
1539 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1541 /* All attributes used in the shader need to have been assigned a
1542 * hardware register by the caller
1546 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1547 reg
.swizzle
= inst
->src
[i
].swizzle
;
1548 reg
.type
= inst
->src
[i
].type
;
1549 if (inst
->src
[i
].abs
)
1551 if (inst
->src
[i
].negate
)
1560 vec4_vs_visitor::setup_attributes(int payload_reg
)
1563 int attribute_map
[VERT_ATTRIB_MAX
+ 2];
1564 memset(attribute_map
, 0, sizeof(attribute_map
));
1567 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1568 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1569 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1574 if (vs_prog_data
->uses_drawid
) {
1575 attribute_map
[VERT_ATTRIB_MAX
+ 1] = payload_reg
+ nr_attributes
;
1579 /* VertexID is stored by the VF as the last vertex element, but we
1580 * don't represent it with a flag in inputs_read, so we call it
1583 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1584 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) {
1585 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1589 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1591 return payload_reg
+ vs_prog_data
->nr_attributes
;
1595 vec4_visitor::setup_uniforms(int reg
)
1597 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1599 /* The pre-gen6 VS requires that some push constants get loaded no
1600 * matter what, or the GPU would hang.
1602 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1603 stage_prog_data
->param
=
1604 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1605 for (unsigned int i
= 0; i
< 4; i
++) {
1606 unsigned int slot
= this->uniforms
* 4 + i
;
1607 static gl_constant_value zero
= { 0.0 };
1608 stage_prog_data
->param
[slot
] = &zero
;
1614 reg
+= ALIGN(uniforms
, 2) / 2;
1617 stage_prog_data
->nr_params
= this->uniforms
* 4;
1619 prog_data
->base
.curb_read_length
=
1620 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1626 vec4_vs_visitor::setup_payload(void)
1630 /* The payload always contains important data in g0, which contains
1631 * the URB handles that are passed on to the URB write at the end
1632 * of the thread. So, we always start push constants at g1.
1636 reg
= setup_uniforms(reg
);
1638 reg
= setup_attributes(reg
);
1640 this->first_non_payload_grf
= reg
;
1644 vec4_visitor::get_timestamp()
1646 assert(devinfo
->gen
>= 7);
1648 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1653 BRW_REGISTER_TYPE_UD
,
1654 BRW_VERTICAL_STRIDE_0
,
1656 BRW_HORIZONTAL_STRIDE_4
,
1660 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1662 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1663 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1664 * even if it's not enabled in the dispatch.
1666 mov
->force_writemask_all
= true;
1668 return src_reg(dst
);
1672 vec4_visitor::emit_shader_time_begin()
1674 current_annotation
= "shader time start";
1675 shader_start_time
= get_timestamp();
1679 vec4_visitor::emit_shader_time_end()
1681 current_annotation
= "shader time end";
1682 src_reg shader_end_time
= get_timestamp();
1685 /* Check that there weren't any timestamp reset events (assuming these
1686 * were the only two timestamp reads that happened).
1688 src_reg reset_end
= shader_end_time
;
1689 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1690 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1691 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1693 emit(IF(BRW_PREDICATE_NORMAL
));
1695 /* Take the current timestamp and get the delta. */
1696 shader_start_time
.negate
= true;
1697 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1698 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1700 /* If there were no instructions between the two timestamp gets, the diff
1701 * is 2 cycles. Remove that overhead, so I can forget about that when
1702 * trying to determine the time taken for single instructions.
1704 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1706 emit_shader_time_write(0, src_reg(diff
));
1707 emit_shader_time_write(1, brw_imm_ud(1u));
1708 emit(BRW_OPCODE_ELSE
);
1709 emit_shader_time_write(2, brw_imm_ud(1u));
1710 emit(BRW_OPCODE_ENDIF
);
1714 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1717 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1719 dst_reg offset
= dst
;
1723 offset
.type
= BRW_REGISTER_TYPE_UD
;
1724 int index
= shader_time_index
* 3 + shader_time_subindex
;
1725 emit(MOV(offset
, brw_imm_d(index
* SHADER_TIME_STRIDE
)));
1727 time
.type
= BRW_REGISTER_TYPE_UD
;
1728 emit(MOV(time
, value
));
1730 vec4_instruction
*inst
=
1731 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1736 vec4_visitor::convert_to_hw_regs()
1738 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1739 for (int i
= 0; i
< 3; i
++) {
1740 struct src_reg
&src
= inst
->src
[i
];
1744 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1745 reg
.type
= src
.type
;
1746 reg
.swizzle
= src
.swizzle
;
1748 reg
.negate
= src
.negate
;
1752 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1753 (src
.nr
+ src
.reg_offset
) / 2,
1754 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1756 reg
.type
= src
.type
;
1757 reg
.swizzle
= src
.swizzle
;
1759 reg
.negate
= src
.negate
;
1761 /* This should have been moved to pull constants. */
1762 assert(!src
.reladdr
);
1771 /* Probably unused. */
1772 reg
= brw_null_reg();
1777 unreachable("not reached");
1783 if (inst
->is_3src()) {
1784 /* 3-src instructions with scalar sources support arbitrary subnr,
1785 * but don't actually use swizzles. Convert swizzle into subnr.
1787 for (int i
= 0; i
< 3; i
++) {
1788 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
) {
1789 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
1790 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
1795 dst_reg
&dst
= inst
->dst
;
1798 switch (inst
->dst
.file
) {
1800 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1801 reg
.type
= dst
.type
;
1802 reg
.writemask
= dst
.writemask
;
1806 assert(((dst
.nr
+ dst
.reg_offset
) & ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
1807 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1808 reg
.type
= dst
.type
;
1809 reg
.writemask
= dst
.writemask
;
1814 reg
= dst
.as_brw_reg();
1818 reg
= brw_null_reg();
1824 unreachable("not reached");
1834 if (shader_time_index
>= 0)
1835 emit_shader_time_begin();
1848 /* Before any optimization, push array accesses out to scratch
1849 * space where we need them to be. This pass may allocate new
1850 * virtual GRFs, so we want to do it early. It also makes sure
1851 * that we have reladdr computations available for CSE, since we'll
1852 * often do repeated subexpressions for those.
1854 move_grf_array_access_to_scratch();
1855 move_uniform_array_access_to_pull_constants();
1857 pack_uniform_registers();
1858 move_push_constants_to_pull_constants();
1859 split_virtual_grfs();
1861 #define OPT(pass, args...) ({ \
1863 bool this_progress = pass(args); \
1865 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1866 char filename[64]; \
1867 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1868 stage_abbrev, nir->info.name, iteration, pass_num); \
1870 backend_shader::dump_instructions(filename); \
1873 progress = progress || this_progress; \
1878 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1880 snprintf(filename
, 64, "%s-%s-00-start",
1881 stage_abbrev
, nir
->info
.name
);
1883 backend_shader::dump_instructions(filename
);
1894 OPT(opt_predicated_break
, this);
1895 OPT(opt_reduce_swizzle
);
1896 OPT(dead_code_eliminate
);
1897 OPT(dead_control_flow_eliminate
, this);
1898 OPT(opt_copy_propagation
);
1899 OPT(opt_cmod_propagation
);
1902 OPT(opt_register_coalesce
);
1903 OPT(eliminate_find_live_channel
);
1908 if (OPT(opt_vector_float
)) {
1910 OPT(opt_copy_propagation
, false);
1911 OPT(opt_copy_propagation
, true);
1912 OPT(dead_code_eliminate
);
1920 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1921 /* Debug of register spilling: Go spill everything. */
1922 const int grf_count
= alloc
.count
;
1923 float spill_costs
[alloc
.count
];
1924 bool no_spill
[alloc
.count
];
1925 evaluate_spill_costs(spill_costs
, no_spill
);
1926 for (int i
= 0; i
< grf_count
; i
++) {
1933 bool allocated_without_spills
= reg_allocate();
1935 if (!allocated_without_spills
) {
1936 compiler
->shader_perf_log(log_data
,
1937 "%s shader triggered register spilling. "
1938 "Try reducing the number of live vec4 values "
1939 "to improve performance.\n",
1942 while (!reg_allocate()) {
1948 opt_schedule_instructions();
1950 opt_set_dependency_control();
1952 convert_to_hw_regs();
1954 if (last_scratch
> 0) {
1955 prog_data
->base
.total_scratch
=
1956 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1962 } /* namespace brw */
1967 * Compile a vertex shader.
1969 * Returns the final assembly and the program's size.
1972 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1974 const struct brw_vs_prog_key
*key
,
1975 struct brw_vs_prog_data
*prog_data
,
1976 const nir_shader
*src_shader
,
1977 gl_clip_plane
*clip_planes
,
1978 bool use_legacy_snorm_formula
,
1979 int shader_time_index
,
1980 unsigned *final_assembly_size
,
1983 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
1984 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
1985 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
1987 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, is_scalar
);
1989 const unsigned *assembly
= NULL
;
1991 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
1993 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
1994 * incoming vertex attribute. So, add an extra slot.
1996 if (shader
->info
.system_values_read
&
1997 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
1998 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
1999 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2000 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2004 /* gl_DrawID has its very own vec4 */
2005 if (shader
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2009 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2010 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2011 * vec4 mode, the hardware appears to wedge unless we read something.
2014 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
2016 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
2018 prog_data
->nr_attributes
= nr_attributes
;
2020 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2021 * (overwriting the original contents), we need to make sure the size is
2022 * the larger of the two.
2024 const unsigned vue_entries
=
2025 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2027 if (compiler
->devinfo
->gen
== 6)
2028 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2030 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2033 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2035 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2036 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2037 shader
, 8, shader_time_index
);
2038 if (!v
.run_vs(clip_planes
)) {
2040 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2045 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2046 &prog_data
->base
.base
, v
.promoted_constants
,
2047 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2048 if (INTEL_DEBUG
& DEBUG_VS
) {
2049 const char *debug_name
=
2050 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2051 shader
->info
.label
? shader
->info
.label
: "unnamed",
2054 g
.enable_debug(debug_name
);
2056 g
.generate_code(v
.cfg
, 8);
2057 assembly
= g
.get_assembly(final_assembly_size
);
2061 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2063 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2064 shader
, clip_planes
, mem_ctx
,
2065 shader_time_index
, use_legacy_snorm_formula
);
2068 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2073 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2074 shader
, &prog_data
->base
, v
.cfg
,
2075 final_assembly_size
);