2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_dead_control_flow.h"
31 #include "main/macros.h"
32 #include "main/shaderobj.h"
33 #include "program/prog_print.h"
34 #include "program/prog_parameter.h"
37 #define MAX_INSTRUCTION (1 << 30)
44 * Common helper for constructing swizzles. When only a subset of
45 * channels of a vec4 are used, we don't want to reference the other
46 * channels, as that will tell optimization passes that those other
50 swizzle_for_size(int size
)
52 static const unsigned size_swizzles
[4] = {
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
56 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
59 assert((size
>= 1) && (size
<= 4));
60 return size_swizzles
[size
- 1];
66 memset(this, 0, sizeof(*this));
68 this->file
= BAD_FILE
;
71 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= BRW_SWIZZLE_XYZW
;
83 /** Generic unset register constructor. */
89 src_reg::src_reg(float f
)
94 this->type
= BRW_REGISTER_TYPE_F
;
95 this->fixed_hw_reg
.dw1
.f
= f
;
98 src_reg::src_reg(uint32_t u
)
103 this->type
= BRW_REGISTER_TYPE_UD
;
104 this->fixed_hw_reg
.dw1
.ud
= u
;
107 src_reg::src_reg(int32_t i
)
112 this->type
= BRW_REGISTER_TYPE_D
;
113 this->fixed_hw_reg
.dw1
.d
= i
;
116 src_reg::src_reg(uint8_t vf
[4])
121 this->type
= BRW_REGISTER_TYPE_VF
;
122 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
125 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
130 this->type
= BRW_REGISTER_TYPE_VF
;
131 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
137 src_reg::src_reg(struct brw_reg reg
)
142 this->fixed_hw_reg
= reg
;
143 this->type
= reg
.type
;
146 src_reg::src_reg(dst_reg reg
)
150 this->file
= reg
.file
;
152 this->reg_offset
= reg
.reg_offset
;
153 this->type
= reg
.type
;
154 this->reladdr
= reg
.reladdr
;
155 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
161 for (int i
= 0; i
< 4; i
++) {
162 if (!(reg
.writemask
& (1 << i
)))
165 swizzles
[next_chan
++] = last
= i
;
168 for (; next_chan
< 4; next_chan
++) {
169 swizzles
[next_chan
] = last
;
172 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
173 swizzles
[2], swizzles
[3]);
179 memset(this, 0, sizeof(*this));
180 this->file
= BAD_FILE
;
181 this->writemask
= WRITEMASK_XYZW
;
189 dst_reg::dst_reg(register_file file
, int reg
)
197 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
204 this->type
= brw_type_for_base_type(type
);
205 this->writemask
= writemask
;
208 dst_reg::dst_reg(struct brw_reg reg
)
213 this->fixed_hw_reg
= reg
;
214 this->type
= reg
.type
;
217 dst_reg::dst_reg(src_reg reg
)
221 this->file
= reg
.file
;
223 this->reg_offset
= reg
.reg_offset
;
224 this->type
= reg
.type
;
225 /* How should we do writemasking when converting from a src_reg? It seems
226 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
227 * what about for src.wx? Just special-case src.xxxx for now.
229 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
230 this->writemask
= WRITEMASK_X
;
232 this->writemask
= WRITEMASK_XYZW
;
233 this->reladdr
= reg
.reladdr
;
234 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
238 dst_reg::equals(const dst_reg
&r
) const
240 return (file
== r
.file
&&
242 reg_offset
== r
.reg_offset
&&
244 negate
== r
.negate
&&
246 writemask
== r
.writemask
&&
247 (reladdr
== r
.reladdr
||
248 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
249 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
250 sizeof(fixed_hw_reg
)) == 0);
254 vec4_instruction::is_send_from_grf()
257 case SHADER_OPCODE_SHADER_TIME_ADD
:
258 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
266 vec4_instruction::regs_read(unsigned arg
) const
268 if (src
[arg
].file
== BAD_FILE
)
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 return arg
== 0 ? mlen
: 1;
275 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
276 return arg
== 1 ? mlen
: 1;
284 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
286 if (brw
->gen
== 6 && is_math())
289 if (is_send_from_grf())
292 if (!backend_instruction::can_do_source_mods())
299 * Returns how many MRFs an opcode will write over.
301 * Note that this is not the 0 or 1 implied writes in an actual gen
302 * instruction -- the generate_* functions generate additional MOVs
306 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
308 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
311 switch (inst
->opcode
) {
312 case SHADER_OPCODE_RCP
:
313 case SHADER_OPCODE_RSQ
:
314 case SHADER_OPCODE_SQRT
:
315 case SHADER_OPCODE_EXP2
:
316 case SHADER_OPCODE_LOG2
:
317 case SHADER_OPCODE_SIN
:
318 case SHADER_OPCODE_COS
:
320 case SHADER_OPCODE_INT_QUOTIENT
:
321 case SHADER_OPCODE_INT_REMAINDER
:
322 case SHADER_OPCODE_POW
:
324 case VS_OPCODE_URB_WRITE
:
326 case VS_OPCODE_PULL_CONSTANT_LOAD
:
328 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
330 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
332 case GS_OPCODE_URB_WRITE
:
333 case GS_OPCODE_URB_WRITE_ALLOCATE
:
334 case GS_OPCODE_THREAD_END
:
336 case GS_OPCODE_FF_SYNC
:
338 case SHADER_OPCODE_SHADER_TIME_ADD
:
340 case SHADER_OPCODE_TEX
:
341 case SHADER_OPCODE_TXL
:
342 case SHADER_OPCODE_TXD
:
343 case SHADER_OPCODE_TXF
:
344 case SHADER_OPCODE_TXF_CMS
:
345 case SHADER_OPCODE_TXF_MCS
:
346 case SHADER_OPCODE_TXS
:
347 case SHADER_OPCODE_TG4
:
348 case SHADER_OPCODE_TG4_OFFSET
:
349 return inst
->header_present
? 1 : 0;
350 case SHADER_OPCODE_UNTYPED_ATOMIC
:
351 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
354 unreachable("not reached");
359 src_reg::equals(const src_reg
&r
) const
361 return (file
== r
.file
&&
363 reg_offset
== r
.reg_offset
&&
365 negate
== r
.negate
&&
367 swizzle
== r
.swizzle
&&
368 !reladdr
&& !r
.reladdr
&&
369 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
370 sizeof(fixed_hw_reg
)) == 0);
374 vec4_visitor::opt_vector_float()
376 bool progress
= false;
378 int last_reg
= -1, last_reg_offset
= -1;
379 enum register_file last_reg_file
= BAD_FILE
;
381 int remaining_channels
= 0;
384 vec4_instruction
*imm_inst
[4];
386 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
387 if (last_reg
!= inst
->dst
.reg
||
388 last_reg_offset
!= inst
->dst
.reg_offset
||
389 last_reg_file
!= inst
->dst
.file
) {
390 last_reg
= inst
->dst
.reg
;
391 last_reg_offset
= inst
->dst
.reg_offset
;
392 last_reg_file
= inst
->dst
.file
;
393 remaining_channels
= WRITEMASK_XYZW
;
398 if (inst
->opcode
!= BRW_OPCODE_MOV
||
399 inst
->dst
.writemask
== WRITEMASK_XYZW
||
400 inst
->src
[0].file
!= IMM
)
403 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
407 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
409 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
411 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
413 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
416 imm_inst
[inst_count
++] = inst
;
418 remaining_channels
&= ~inst
->dst
.writemask
;
419 if (remaining_channels
== 0) {
420 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
421 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
422 mov
->dst
.writemask
= WRITEMASK_XYZW
;
423 inst
->insert_after(block
, mov
);
426 for (int i
= 0; i
< inst_count
; i
++) {
427 imm_inst
[i
]->remove(block
);
434 invalidate_live_intervals();
439 /* Replaces unused channels of a swizzle with channels that are used.
441 * For instance, this pass transforms
443 * mov vgrf4.yz, vgrf5.wxzy
447 * mov vgrf4.yz, vgrf5.xxzx
449 * This eliminates false uses of some channels, letting dead code elimination
450 * remove the instructions that wrote them.
453 vec4_visitor::opt_reduce_swizzle()
455 bool progress
= false;
457 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
458 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
459 inst
->is_send_from_grf())
464 /* Determine which channels of the sources are read. */
465 switch (inst
->opcode
) {
466 case VEC4_OPCODE_PACK_BYTES
:
473 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
474 * but all four of src1.
494 swizzle
[0] = inst
->dst
.writemask
& WRITEMASK_X
? 0 : -1;
495 swizzle
[1] = inst
->dst
.writemask
& WRITEMASK_Y
? 1 : -1;
496 swizzle
[2] = inst
->dst
.writemask
& WRITEMASK_Z
? 2 : -1;
497 swizzle
[3] = inst
->dst
.writemask
& WRITEMASK_W
? 3 : -1;
501 /* Resolve unread channels (-1) by assigning them the swizzle of the
502 * first channel that is used.
504 int first_used_channel
= 0;
505 for (int i
= 0; i
< 4; i
++) {
506 if (swizzle
[i
] != -1) {
507 first_used_channel
= swizzle
[i
];
511 for (int i
= 0; i
< 4; i
++) {
512 if (swizzle
[i
] == -1) {
513 swizzle
[i
] = first_used_channel
;
517 /* Update sources' swizzles. */
518 for (int i
= 0; i
< 3; i
++) {
519 if (inst
->src
[i
].file
!= GRF
&&
520 inst
->src
[i
].file
!= ATTR
&&
521 inst
->src
[i
].file
!= UNIFORM
)
525 for (int j
= 0; j
< 4; j
++) {
526 swiz
[j
] = BRW_GET_SWZ(inst
->src
[i
].swizzle
, swizzle
[j
]);
529 unsigned new_swizzle
= BRW_SWIZZLE4(swiz
[0], swiz
[1], swiz
[2], swiz
[3]);
530 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
531 inst
->src
[i
].swizzle
= new_swizzle
;
538 invalidate_live_intervals();
544 vec4_visitor::split_uniform_registers()
546 /* Prior to this, uniforms have been in an array sized according to
547 * the number of vector uniforms present, sparsely filled (so an
548 * aggregate results in reg indices being skipped over). Now we're
549 * going to cut those aggregates up so each .reg index is one
550 * vector. The goal is to make elimination of unused uniform
551 * components easier later.
553 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
554 for (int i
= 0 ; i
< 3; i
++) {
555 if (inst
->src
[i
].file
!= UNIFORM
)
558 assert(!inst
->src
[i
].reladdr
);
560 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
561 inst
->src
[i
].reg_offset
= 0;
565 /* Update that everything is now vector-sized. */
566 for (int i
= 0; i
< this->uniforms
; i
++) {
567 this->uniform_size
[i
] = 1;
572 vec4_visitor::pack_uniform_registers()
574 bool uniform_used
[this->uniforms
];
575 int new_loc
[this->uniforms
];
576 int new_chan
[this->uniforms
];
578 memset(uniform_used
, 0, sizeof(uniform_used
));
579 memset(new_loc
, 0, sizeof(new_loc
));
580 memset(new_chan
, 0, sizeof(new_chan
));
582 /* Find which uniform vectors are actually used by the program. We
583 * expect unused vector elements when we've moved array access out
584 * to pull constants, and from some GLSL code generators like wine.
586 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
587 for (int i
= 0 ; i
< 3; i
++) {
588 if (inst
->src
[i
].file
!= UNIFORM
)
591 uniform_used
[inst
->src
[i
].reg
] = true;
595 int new_uniform_count
= 0;
597 /* Now, figure out a packing of the live uniform vectors into our
600 for (int src
= 0; src
< uniforms
; src
++) {
601 assert(src
< uniform_array_size
);
602 int size
= this->uniform_vector_size
[src
];
604 if (!uniform_used
[src
]) {
605 this->uniform_vector_size
[src
] = 0;
610 /* Find the lowest place we can slot this uniform in. */
611 for (dst
= 0; dst
< src
; dst
++) {
612 if (this->uniform_vector_size
[dst
] + size
<= 4)
621 new_chan
[src
] = this->uniform_vector_size
[dst
];
623 /* Move the references to the data */
624 for (int j
= 0; j
< size
; j
++) {
625 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
626 stage_prog_data
->param
[src
* 4 + j
];
629 this->uniform_vector_size
[dst
] += size
;
630 this->uniform_vector_size
[src
] = 0;
633 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
636 this->uniforms
= new_uniform_count
;
638 /* Now, update the instructions for our repacked uniforms. */
639 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
640 for (int i
= 0 ; i
< 3; i
++) {
641 int src
= inst
->src
[i
].reg
;
643 if (inst
->src
[i
].file
!= UNIFORM
)
646 inst
->src
[i
].reg
= new_loc
[src
];
648 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
649 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
650 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
651 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
652 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
658 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
660 * While GLSL IR also performs this optimization, we end up with it in
661 * our instruction stream for a couple of reasons. One is that we
662 * sometimes generate silly instructions, for example in array access
663 * where we'll generate "ADD offset, index, base" even if base is 0.
664 * The other is that GLSL IR's constant propagation doesn't track the
665 * components of aggregates, so some VS patterns (initialize matrix to
666 * 0, accumulate in vertex blending factors) end up breaking down to
667 * instructions involving 0.
670 vec4_visitor::opt_algebraic()
672 bool progress
= false;
674 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
675 switch (inst
->opcode
) {
677 if (inst
->src
[0].file
!= IMM
)
680 if (inst
->saturate
) {
681 if (inst
->dst
.type
!= inst
->src
[0].type
)
682 assert(!"unimplemented: saturate mixed types");
684 if (brw_saturate_immediate(inst
->dst
.type
,
685 &inst
->src
[0].fixed_hw_reg
)) {
686 inst
->saturate
= false;
692 case VEC4_OPCODE_UNPACK_UNIFORM
:
693 if (inst
->src
[0].file
!= UNIFORM
) {
694 inst
->opcode
= BRW_OPCODE_MOV
;
700 if (inst
->src
[1].is_zero()) {
701 inst
->opcode
= BRW_OPCODE_MOV
;
702 inst
->src
[1] = src_reg();
708 if (inst
->src
[1].is_zero()) {
709 inst
->opcode
= BRW_OPCODE_MOV
;
710 switch (inst
->src
[0].type
) {
711 case BRW_REGISTER_TYPE_F
:
712 inst
->src
[0] = src_reg(0.0f
);
714 case BRW_REGISTER_TYPE_D
:
715 inst
->src
[0] = src_reg(0);
717 case BRW_REGISTER_TYPE_UD
:
718 inst
->src
[0] = src_reg(0u);
721 unreachable("not reached");
723 inst
->src
[1] = src_reg();
725 } else if (inst
->src
[1].is_one()) {
726 inst
->opcode
= BRW_OPCODE_MOV
;
727 inst
->src
[1] = src_reg();
729 } else if (inst
->src
[1].is_negative_one()) {
730 inst
->opcode
= BRW_OPCODE_MOV
;
731 inst
->src
[0].negate
= !inst
->src
[0].negate
;
732 inst
->src
[1] = src_reg();
737 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
739 inst
->src
[0].negate
&&
740 inst
->src
[1].is_zero()) {
741 inst
->src
[0].abs
= false;
742 inst
->src
[0].negate
= false;
743 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
748 case SHADER_OPCODE_RCP
: {
749 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
750 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
751 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
752 inst
->opcode
= SHADER_OPCODE_RSQ
;
753 inst
->src
[0] = prev
->src
[0];
765 invalidate_live_intervals();
771 * Only a limited number of hardware registers may be used for push
772 * constants, so this turns access to the overflowed constants into
776 vec4_visitor::move_push_constants_to_pull_constants()
778 int pull_constant_loc
[this->uniforms
];
780 /* Only allow 32 registers (256 uniform components) as push constants,
781 * which is the limit on gen6.
783 * If changing this value, note the limitation about total_regs in
786 int max_uniform_components
= 32 * 8;
787 if (this->uniforms
* 4 <= max_uniform_components
)
790 /* Make some sort of choice as to which uniforms get sent to pull
791 * constants. We could potentially do something clever here like
792 * look for the most infrequently used uniform vec4s, but leave
795 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
796 pull_constant_loc
[i
/ 4] = -1;
798 if (i
>= max_uniform_components
) {
799 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
801 /* Try to find an existing copy of this uniform in the pull
802 * constants if it was part of an array access already.
804 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
807 for (matches
= 0; matches
< 4; matches
++) {
808 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
813 pull_constant_loc
[i
/ 4] = j
/ 4;
818 if (pull_constant_loc
[i
/ 4] == -1) {
819 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
820 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
822 for (int j
= 0; j
< 4; j
++) {
823 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
830 /* Now actually rewrite usage of the things we've moved to pull
833 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
834 for (int i
= 0 ; i
< 3; i
++) {
835 if (inst
->src
[i
].file
!= UNIFORM
||
836 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
839 int uniform
= inst
->src
[i
].reg
;
841 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
843 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
844 pull_constant_loc
[uniform
]);
846 inst
->src
[i
].file
= temp
.file
;
847 inst
->src
[i
].reg
= temp
.reg
;
848 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
849 inst
->src
[i
].reladdr
= NULL
;
853 /* Repack push constants to remove the now-unused ones. */
854 pack_uniform_registers();
857 /* Conditions for which we want to avoid setting the dependency control bits */
859 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
861 #define IS_DWORD(reg) \
862 (reg.type == BRW_REGISTER_TYPE_UD || \
863 reg.type == BRW_REGISTER_TYPE_D)
865 /* "When source or destination datatype is 64b or operation is integer DWord
866 * multiply, DepCtrl must not be used."
867 * May apply to future SoCs as well.
869 if (brw
->is_cherryview
) {
870 if (inst
->opcode
== BRW_OPCODE_MUL
&&
871 IS_DWORD(inst
->src
[0]) &&
872 IS_DWORD(inst
->src
[1]))
878 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
884 * In the presence of send messages, totally interrupt dependency
885 * control. They're long enough that the chance of dependency
886 * control around them just doesn't matter.
889 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
890 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
891 * completes the scoreboard clear must have a non-zero execution mask. This
892 * means, if any kind of predication can change the execution mask or channel
893 * enable of the last instruction, the optimization must be avoided. This is
894 * to avoid instructions being shot down the pipeline when no writes are
898 * Dependency control does not work well over math instructions.
899 * NB: Discovered empirically
901 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
905 * Sets the dependency control fields on instructions after register
906 * allocation and before the generator is run.
908 * When you have a sequence of instructions like:
910 * DP4 temp.x vertex uniform[0]
911 * DP4 temp.y vertex uniform[0]
912 * DP4 temp.z vertex uniform[0]
913 * DP4 temp.w vertex uniform[0]
915 * The hardware doesn't know that it can actually run the later instructions
916 * while the previous ones are in flight, producing stalls. However, we have
917 * manual fields we can set in the instructions that let it do so.
920 vec4_visitor::opt_set_dependency_control()
922 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
923 uint8_t grf_channels_written
[BRW_MAX_GRF
];
924 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
925 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
927 assert(prog_data
->total_grf
||
928 !"Must be called after register allocation");
930 foreach_block (block
, cfg
) {
931 memset(last_grf_write
, 0, sizeof(last_grf_write
));
932 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
934 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
935 /* If we read from a register that we were doing dependency control
936 * on, don't do dependency control across the read.
938 for (int i
= 0; i
< 3; i
++) {
939 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
940 if (inst
->src
[i
].file
== GRF
) {
941 last_grf_write
[reg
] = NULL
;
942 } else if (inst
->src
[i
].file
== HW_REG
) {
943 memset(last_grf_write
, 0, sizeof(last_grf_write
));
946 assert(inst
->src
[i
].file
!= MRF
);
949 if (is_dep_ctrl_unsafe(inst
)) {
950 memset(last_grf_write
, 0, sizeof(last_grf_write
));
951 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
955 /* Now, see if we can do dependency control for this instruction
956 * against a previous one writing to its destination.
958 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
959 if (inst
->dst
.file
== GRF
) {
960 if (last_grf_write
[reg
] &&
961 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
962 last_grf_write
[reg
]->no_dd_clear
= true;
963 inst
->no_dd_check
= true;
965 grf_channels_written
[reg
] = 0;
968 last_grf_write
[reg
] = inst
;
969 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
970 } else if (inst
->dst
.file
== MRF
) {
971 if (last_mrf_write
[reg
] &&
972 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
973 last_mrf_write
[reg
]->no_dd_clear
= true;
974 inst
->no_dd_check
= true;
976 mrf_channels_written
[reg
] = 0;
979 last_mrf_write
[reg
] = inst
;
980 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
981 } else if (inst
->dst
.reg
== HW_REG
) {
982 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
983 memset(last_grf_write
, 0, sizeof(last_grf_write
));
984 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
985 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
992 vec4_instruction::can_reswizzle(int dst_writemask
,
996 /* If this instruction sets anything not referenced by swizzle, then we'd
997 * totally break it when we reswizzle.
999 if (dst
.writemask
& ~swizzle_mask
)
1009 * For any channels in the swizzle's source that were populated by this
1010 * instruction, rewrite the instruction to put the appropriate result directly
1011 * in those channels.
1013 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1016 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1018 int new_writemask
= 0;
1019 int new_swizzle
[4] = { 0 };
1021 /* Dot product instructions write a single result into all channels. */
1022 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1023 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
) {
1024 for (int i
= 0; i
< 3; i
++) {
1025 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1028 /* Destination write mask doesn't correspond to source swizzle for the
1029 * pack_bytes instruction.
1031 if (opcode
== VEC4_OPCODE_PACK_BYTES
)
1034 for (int c
= 0; c
< 4; c
++) {
1035 new_swizzle
[c
] = BRW_GET_SWZ(src
[i
].swizzle
, BRW_GET_SWZ(swizzle
, c
));
1038 src
[i
].swizzle
= BRW_SWIZZLE4(new_swizzle
[0], new_swizzle
[1],
1039 new_swizzle
[2], new_swizzle
[3]);
1043 for (int c
= 0; c
< 4; c
++) {
1044 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
1045 /* Skip components of the swizzle not used by the dst. */
1046 if (!(dst_writemask
& (1 << c
)))
1048 /* If we were populating this component, then populate the
1049 * corresponding channel of the new dst.
1051 if (dst
.writemask
& bit
)
1052 new_writemask
|= (1 << c
);
1054 dst
.writemask
= new_writemask
;
1058 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1059 * just written and then MOVed into another reg and making the original write
1060 * of the GRF write directly to the final destination instead.
1063 vec4_visitor::opt_register_coalesce()
1065 bool progress
= false;
1068 calculate_live_intervals();
1070 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1074 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1075 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1077 inst
->src
[0].file
!= GRF
||
1078 inst
->dst
.type
!= inst
->src
[0].type
||
1079 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1082 bool to_mrf
= (inst
->dst
.file
== MRF
);
1084 /* Can't coalesce this GRF if someone else was going to
1087 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1088 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1089 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1090 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1093 /* We need to check interference with the final destination between this
1094 * instruction and the earliest instruction involved in writing the GRF
1095 * we're eliminating. To do that, keep track of which of our source
1096 * channels we've seen initialized.
1098 bool chans_needed
[4] = {false, false, false, false};
1099 int chans_remaining
= 0;
1100 int swizzle_mask
= 0;
1101 for (int i
= 0; i
< 4; i
++) {
1102 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1104 if (!(inst
->dst
.writemask
& (1 << i
)))
1107 swizzle_mask
|= (1 << chan
);
1109 if (!chans_needed
[chan
]) {
1110 chans_needed
[chan
] = true;
1115 /* Now walk up the instruction stream trying to see if we can rewrite
1116 * everything writing to the temporary to write into the destination
1119 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1120 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1122 _scan_inst
= scan_inst
;
1124 if (scan_inst
->dst
.file
== GRF
&&
1125 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1126 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1127 /* Found something writing to the reg we want to coalesce away. */
1129 /* SEND instructions can't have MRF as a destination. */
1130 if (scan_inst
->mlen
)
1133 if (brw
->gen
== 6) {
1134 /* gen6 math instructions must have the destination be
1135 * GRF, so no compute-to-MRF for them.
1137 if (scan_inst
->is_math()) {
1143 /* If we can't handle the swizzle, bail. */
1144 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1145 inst
->src
[0].swizzle
,
1150 /* Mark which channels we found unconditional writes for. */
1151 if (!scan_inst
->predicate
) {
1152 for (int i
= 0; i
< 4; i
++) {
1153 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1155 chans_needed
[i
] = false;
1161 if (chans_remaining
== 0)
1165 /* You can't read from an MRF, so if someone else reads our MRF's
1166 * source GRF that we wanted to rewrite, that stops us. If it's a
1167 * GRF we're trying to coalesce to, we don't actually handle
1168 * rewriting sources so bail in that case as well.
1170 bool interfered
= false;
1171 for (int i
= 0; i
< 3; i
++) {
1172 if (scan_inst
->src
[i
].file
== GRF
&&
1173 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1174 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1181 /* If somebody else writes our destination here, we can't coalesce
1184 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1185 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1189 /* Check for reads of the register we're trying to coalesce into. We
1190 * can't go rewriting instructions above that to put some other value
1191 * in the register instead.
1193 if (to_mrf
&& scan_inst
->mlen
> 0) {
1194 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1195 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1199 for (int i
= 0; i
< 3; i
++) {
1200 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1201 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1202 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1211 if (chans_remaining
== 0) {
1212 /* If we've made it here, we have an MOV we want to coalesce out, and
1213 * a scan_inst pointing to the earliest instruction involved in
1214 * computing the value. Now go rewrite the instruction stream
1217 vec4_instruction
*scan_inst
= _scan_inst
;
1218 while (scan_inst
!= inst
) {
1219 if (scan_inst
->dst
.file
== GRF
&&
1220 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1221 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1222 scan_inst
->reswizzle(inst
->dst
.writemask
,
1223 inst
->src
[0].swizzle
);
1224 scan_inst
->dst
.file
= inst
->dst
.file
;
1225 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1226 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1227 scan_inst
->saturate
|= inst
->saturate
;
1229 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1231 inst
->remove(block
);
1237 invalidate_live_intervals();
1243 * Splits virtual GRFs requesting more than one contiguous physical register.
1245 * We initially create large virtual GRFs for temporary structures, arrays,
1246 * and matrices, so that the dereference visitor functions can add reg_offsets
1247 * to work their way down to the actual member being accessed. But when it
1248 * comes to optimization, we'd like to treat each register as individual
1249 * storage if possible.
1251 * So far, the only thing that might prevent splitting is a send message from
1255 vec4_visitor::split_virtual_grfs()
1257 int num_vars
= this->alloc
.count
;
1258 int new_virtual_grf
[num_vars
];
1259 bool split_grf
[num_vars
];
1261 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1263 /* Try to split anything > 0 sized. */
1264 for (int i
= 0; i
< num_vars
; i
++) {
1265 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1268 /* Check that the instructions are compatible with the registers we're trying
1271 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1272 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1275 if (inst
->is_send_from_grf()) {
1276 for (int i
= 0; i
< 3; i
++) {
1277 if (inst
->src
[i
].file
== GRF
) {
1278 split_grf
[inst
->src
[i
].reg
] = false;
1284 /* Allocate new space for split regs. Note that the virtual
1285 * numbers will be contiguous.
1287 for (int i
= 0; i
< num_vars
; i
++) {
1291 new_virtual_grf
[i
] = alloc
.allocate(1);
1292 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1293 unsigned reg
= alloc
.allocate(1);
1294 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1297 this->alloc
.sizes
[i
] = 1;
1300 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1301 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1302 inst
->dst
.reg_offset
!= 0) {
1303 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1304 inst
->dst
.reg_offset
- 1);
1305 inst
->dst
.reg_offset
= 0;
1307 for (int i
= 0; i
< 3; i
++) {
1308 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1309 inst
->src
[i
].reg_offset
!= 0) {
1310 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1311 inst
->src
[i
].reg_offset
- 1);
1312 inst
->src
[i
].reg_offset
= 0;
1316 invalidate_live_intervals();
1320 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1322 dump_instruction(be_inst
, stderr
);
1326 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1328 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1330 if (inst
->predicate
) {
1331 fprintf(file
, "(%cf0.%d) ",
1332 inst
->predicate_inverse
? '-' : '+',
1336 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1338 fprintf(file
, ".sat");
1339 if (inst
->conditional_mod
) {
1340 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1341 if (!inst
->predicate
&&
1342 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1343 inst
->opcode
!= BRW_OPCODE_IF
&&
1344 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1345 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1350 switch (inst
->dst
.file
) {
1352 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1355 fprintf(file
, "m%d", inst
->dst
.reg
);
1358 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1359 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1361 fprintf(file
, "null");
1363 case BRW_ARF_ADDRESS
:
1364 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1366 case BRW_ARF_ACCUMULATOR
:
1367 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1370 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1371 inst
->dst
.fixed_hw_reg
.subnr
);
1374 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1375 inst
->dst
.fixed_hw_reg
.subnr
);
1379 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1381 if (inst
->dst
.fixed_hw_reg
.subnr
)
1382 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1385 fprintf(file
, "(null)");
1388 fprintf(file
, "???");
1391 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1393 if (inst
->dst
.writemask
& 1)
1395 if (inst
->dst
.writemask
& 2)
1397 if (inst
->dst
.writemask
& 4)
1399 if (inst
->dst
.writemask
& 8)
1402 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1404 if (inst
->src
[0].file
!= BAD_FILE
)
1405 fprintf(file
, ", ");
1407 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1408 if (inst
->src
[i
].negate
)
1410 if (inst
->src
[i
].abs
)
1412 switch (inst
->src
[i
].file
) {
1414 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1417 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1420 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1423 switch (inst
->src
[i
].type
) {
1424 case BRW_REGISTER_TYPE_F
:
1425 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1427 case BRW_REGISTER_TYPE_D
:
1428 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1430 case BRW_REGISTER_TYPE_UD
:
1431 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1433 case BRW_REGISTER_TYPE_VF
:
1434 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1435 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1436 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1437 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1438 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1441 fprintf(file
, "???");
1446 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1448 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1450 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1451 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1453 fprintf(file
, "null");
1455 case BRW_ARF_ADDRESS
:
1456 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1458 case BRW_ARF_ACCUMULATOR
:
1459 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1462 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1463 inst
->src
[i
].fixed_hw_reg
.subnr
);
1466 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1467 inst
->src
[i
].fixed_hw_reg
.subnr
);
1471 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1473 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1474 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1475 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1479 fprintf(file
, "(null)");
1482 fprintf(file
, "???");
1486 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1487 if (inst
->src
[i
].reg_offset
!= 0 &&
1488 inst
->src
[i
].file
== GRF
&&
1489 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1490 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1492 if (inst
->src
[i
].file
!= IMM
) {
1493 static const char *chans
[4] = {"x", "y", "z", "w"};
1495 for (int c
= 0; c
< 4; c
++) {
1496 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1500 if (inst
->src
[i
].abs
)
1503 if (inst
->src
[i
].file
!= IMM
) {
1504 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1507 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1508 fprintf(file
, ", ");
1511 fprintf(file
, "\n");
1515 static inline struct brw_reg
1516 attribute_to_hw_reg(int attr
, bool interleaved
)
1519 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1521 return brw_vec8_grf(attr
, 0);
1526 * Replace each register of type ATTR in this->instructions with a reference
1527 * to a fixed HW register.
1529 * If interleaved is true, then each attribute takes up half a register, with
1530 * register N containing attribute 2*N in its first half and attribute 2*N+1
1531 * in its second half (this corresponds to the payload setup used by geometry
1532 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1533 * false, then each attribute takes up a whole register, with register N
1534 * containing attribute N (this corresponds to the payload setup used by
1535 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1538 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1541 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1542 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1543 if (inst
->dst
.file
== ATTR
) {
1544 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1546 /* All attributes used in the shader need to have been assigned a
1547 * hardware register by the caller
1551 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1552 reg
.type
= inst
->dst
.type
;
1553 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1555 inst
->dst
.file
= HW_REG
;
1556 inst
->dst
.fixed_hw_reg
= reg
;
1559 for (int i
= 0; i
< 3; i
++) {
1560 if (inst
->src
[i
].file
!= ATTR
)
1563 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1565 /* All attributes used in the shader need to have been assigned a
1566 * hardware register by the caller
1570 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1571 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1572 reg
.type
= inst
->src
[i
].type
;
1573 if (inst
->src
[i
].abs
)
1575 if (inst
->src
[i
].negate
)
1578 inst
->src
[i
].file
= HW_REG
;
1579 inst
->src
[i
].fixed_hw_reg
= reg
;
1585 vec4_vs_visitor::setup_attributes(int payload_reg
)
1588 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1589 memset(attribute_map
, 0, sizeof(attribute_map
));
1592 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1593 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1594 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1599 /* VertexID is stored by the VF as the last vertex element, but we
1600 * don't represent it with a flag in inputs_read, so we call it
1603 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1604 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1608 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1610 /* The BSpec says we always have to read at least one thing from
1611 * the VF, and it appears that the hardware wedges otherwise.
1613 if (nr_attributes
== 0)
1616 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1618 unsigned vue_entries
=
1619 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1622 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1624 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1626 return payload_reg
+ nr_attributes
;
1630 vec4_visitor::setup_uniforms(int reg
)
1632 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1634 /* The pre-gen6 VS requires that some push constants get loaded no
1635 * matter what, or the GPU would hang.
1637 if (brw
->gen
< 6 && this->uniforms
== 0) {
1638 assert(this->uniforms
< this->uniform_array_size
);
1639 this->uniform_vector_size
[this->uniforms
] = 1;
1641 stage_prog_data
->param
=
1642 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1643 for (unsigned int i
= 0; i
< 4; i
++) {
1644 unsigned int slot
= this->uniforms
* 4 + i
;
1645 static gl_constant_value zero
= { 0.0 };
1646 stage_prog_data
->param
[slot
] = &zero
;
1652 reg
+= ALIGN(uniforms
, 2) / 2;
1655 stage_prog_data
->nr_params
= this->uniforms
* 4;
1657 prog_data
->base
.curb_read_length
=
1658 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1664 vec4_vs_visitor::setup_payload(void)
1668 /* The payload always contains important data in g0, which contains
1669 * the URB handles that are passed on to the URB write at the end
1670 * of the thread. So, we always start push constants at g1.
1674 reg
= setup_uniforms(reg
);
1676 reg
= setup_attributes(reg
);
1678 this->first_non_payload_grf
= reg
;
1682 vec4_visitor::assign_binding_table_offsets()
1684 assign_common_binding_table_offsets(0);
1688 vec4_visitor::get_timestamp()
1690 assert(brw
->gen
>= 7);
1692 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1697 BRW_REGISTER_TYPE_UD
,
1698 BRW_VERTICAL_STRIDE_0
,
1700 BRW_HORIZONTAL_STRIDE_4
,
1704 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1706 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1707 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1708 * even if it's not enabled in the dispatch.
1710 mov
->force_writemask_all
= true;
1712 return src_reg(dst
);
1716 vec4_visitor::emit_shader_time_begin()
1718 current_annotation
= "shader time start";
1719 shader_start_time
= get_timestamp();
1723 vec4_visitor::emit_shader_time_end()
1725 current_annotation
= "shader time end";
1726 src_reg shader_end_time
= get_timestamp();
1729 /* Check that there weren't any timestamp reset events (assuming these
1730 * were the only two timestamp reads that happened).
1732 src_reg reset_end
= shader_end_time
;
1733 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1734 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1735 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1737 emit(IF(BRW_PREDICATE_NORMAL
));
1739 /* Take the current timestamp and get the delta. */
1740 shader_start_time
.negate
= true;
1741 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1742 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1744 /* If there were no instructions between the two timestamp gets, the diff
1745 * is 2 cycles. Remove that overhead, so I can forget about that when
1746 * trying to determine the time taken for single instructions.
1748 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1750 emit_shader_time_write(st_base
, src_reg(diff
));
1751 emit_shader_time_write(st_written
, src_reg(1u));
1752 emit(BRW_OPCODE_ELSE
);
1753 emit_shader_time_write(st_reset
, src_reg(1u));
1754 emit(BRW_OPCODE_ENDIF
);
1758 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1761 int shader_time_index
=
1762 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1765 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1767 dst_reg offset
= dst
;
1771 offset
.type
= BRW_REGISTER_TYPE_UD
;
1772 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1774 time
.type
= BRW_REGISTER_TYPE_UD
;
1775 emit(MOV(time
, src_reg(value
)));
1777 vec4_instruction
*inst
=
1778 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1785 sanity_param_count
= prog
->Parameters
->NumParameters
;
1787 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1788 emit_shader_time_begin();
1790 assign_binding_table_offsets();
1794 /* Generate VS IR for main(). (the visitor only descends into
1795 * functions called "main").
1798 visit_instructions(shader
->base
.ir
);
1800 emit_program_code();
1804 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1805 setup_uniform_clipplane_values();
1811 /* Before any optimization, push array accesses out to scratch
1812 * space where we need them to be. This pass may allocate new
1813 * virtual GRFs, so we want to do it early. It also makes sure
1814 * that we have reladdr computations available for CSE, since we'll
1815 * often do repeated subexpressions for those.
1818 move_grf_array_access_to_scratch();
1819 move_uniform_array_access_to_pull_constants();
1821 /* The ARB_vertex_program frontend emits pull constant loads directly
1822 * rather than using reladdr, so we don't need to walk through all the
1823 * instructions looking for things to move. There isn't anything.
1825 * We do still need to split things to vec4 size.
1827 split_uniform_registers();
1829 pack_uniform_registers();
1830 move_push_constants_to_pull_constants();
1831 split_virtual_grfs();
1833 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1835 #define OPT(pass, args...) ({ \
1837 bool this_progress = pass(args); \
1839 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1840 char filename[64]; \
1841 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1842 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1844 backend_visitor::dump_instructions(filename); \
1847 progress = progress || this_progress; \
1852 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1854 snprintf(filename
, 64, "%s-%04d-00-start",
1855 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1857 backend_visitor::dump_instructions(filename
);
1868 OPT(opt_reduce_swizzle
);
1869 OPT(dead_code_eliminate
);
1870 OPT(dead_control_flow_eliminate
, this);
1871 OPT(opt_copy_propagation
);
1874 OPT(opt_register_coalesce
);
1879 if (OPT(opt_vector_float
)) {
1881 OPT(opt_copy_propagation
, false);
1882 OPT(opt_copy_propagation
, true);
1883 OPT(dead_code_eliminate
);
1892 /* Debug of register spilling: Go spill everything. */
1893 const int grf_count
= alloc
.count
;
1894 float spill_costs
[alloc
.count
];
1895 bool no_spill
[alloc
.count
];
1896 evaluate_spill_costs(spill_costs
, no_spill
);
1897 for (int i
= 0; i
< grf_count
; i
++) {
1904 while (!reg_allocate()) {
1909 opt_schedule_instructions();
1911 opt_set_dependency_control();
1913 /* If any state parameters were appended, then ParameterValues could have
1914 * been realloced, in which case the driver uniform storage set up by
1915 * _mesa_associate_uniform_storage() would point to freed memory. Make
1916 * sure that didn't happen.
1918 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1923 } /* namespace brw */
1928 * Compile a vertex shader.
1930 * Returns the final assembly and the program's size.
1933 brw_vs_emit(struct brw_context
*brw
,
1934 struct gl_shader_program
*prog
,
1935 struct brw_vs_compile
*c
,
1936 struct brw_vs_prog_data
*prog_data
,
1938 unsigned *final_assembly_size
)
1940 bool start_busy
= false;
1941 double start_time
= 0;
1942 const unsigned *assembly
= NULL
;
1944 if (unlikely(brw
->perf_debug
)) {
1945 start_busy
= (brw
->batch
.last_bo
&&
1946 drm_intel_bo_busy(brw
->batch
.last_bo
));
1947 start_time
= get_time();
1950 struct brw_shader
*shader
= NULL
;
1952 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1954 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1955 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1957 if (prog
&& brw
->gen
>= 8 && brw
->scalar_vs
) {
1958 fs_visitor
v(brw
, mem_ctx
, &c
->key
, prog_data
, prog
, &c
->vp
->program
, 8);
1961 prog
->LinkStatus
= false;
1962 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1965 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1971 fs_generator
g(brw
, mem_ctx
, (void *) &c
->key
, &prog_data
->base
.base
,
1972 &c
->vp
->program
.Base
, v
.promoted_constants
,
1973 v
.runtime_check_aads_emit
, "VS");
1974 if (INTEL_DEBUG
& DEBUG_VS
) {
1975 char *name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1976 prog
->Label
? prog
->Label
: "unnamed",
1978 g
.enable_debug(name
);
1980 g
.generate_code(v
.cfg
, 8);
1981 assembly
= g
.get_assembly(final_assembly_size
);
1984 prog_data
->base
.simd8
= true;
1985 c
->base
.last_scratch
= v
.last_scratch
;
1989 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1992 prog
->LinkStatus
= false;
1993 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1996 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
2002 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
2003 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
2004 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
2007 if (unlikely(brw
->perf_debug
) && shader
) {
2008 if (shader
->compiled_once
) {
2009 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
2011 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
2012 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
2013 (get_time() - start_time
) * 1000);
2015 shader
->compiled_once
= true;
2023 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
2024 struct brw_vue_prog_key
*key
,
2025 GLuint id
, struct gl_program
*prog
)
2027 struct brw_context
*brw
= brw_context(ctx
);
2028 key
->program_string_id
= id
;
2030 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
2031 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
2032 for (unsigned i
= 0; i
< sampler_count
; i
++) {
2033 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
2034 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
2035 key
->tex
.swizzles
[i
] =
2036 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
2038 /* Color sampler: assume no swizzling. */
2039 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;