2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_print_visitor.h"
29 #include "main/macros.h"
30 #include "main/shaderobj.h"
31 #include "program/prog_print.h"
32 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
42 * Common helper for constructing swizzles. When only a subset of
43 * channels of a vec4 are used, we don't want to reference the other
44 * channels, as that will tell optimization passes that those other
48 swizzle_for_size(int size
)
50 static const unsigned size_swizzles
[4] = {
51 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
57 assert((size
>= 1) && (size
<= 4));
58 return size_swizzles
[size
- 1];
64 memset(this, 0, sizeof(*this));
66 this->file
= BAD_FILE
;
69 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
75 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
76 this->swizzle
= swizzle_for_size(type
->vector_elements
);
78 this->swizzle
= SWIZZLE_XYZW
;
81 /** Generic unset register constructor. */
87 src_reg::src_reg(float f
)
92 this->type
= BRW_REGISTER_TYPE_F
;
96 src_reg::src_reg(uint32_t u
)
101 this->type
= BRW_REGISTER_TYPE_UD
;
105 src_reg::src_reg(int32_t i
)
110 this->type
= BRW_REGISTER_TYPE_D
;
114 src_reg::src_reg(dst_reg reg
)
118 this->file
= reg
.file
;
120 this->reg_offset
= reg
.reg_offset
;
121 this->type
= reg
.type
;
122 this->reladdr
= reg
.reladdr
;
123 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
129 for (int i
= 0; i
< 4; i
++) {
130 if (!(reg
.writemask
& (1 << i
)))
133 swizzles
[next_chan
++] = last
= i
;
136 for (; next_chan
< 4; next_chan
++) {
137 swizzles
[next_chan
] = last
;
140 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
141 swizzles
[2], swizzles
[3]);
145 vec4_instruction::is_tex()
147 return (opcode
== SHADER_OPCODE_TEX
||
148 opcode
== SHADER_OPCODE_TXD
||
149 opcode
== SHADER_OPCODE_TXF
||
150 opcode
== SHADER_OPCODE_TXF_MS
||
151 opcode
== SHADER_OPCODE_TXL
||
152 opcode
== SHADER_OPCODE_TXS
);
158 memset(this, 0, sizeof(*this));
159 this->file
= BAD_FILE
;
160 this->writemask
= WRITEMASK_XYZW
;
168 dst_reg::dst_reg(register_file file
, int reg
)
176 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
183 this->type
= brw_type_for_base_type(type
);
184 this->writemask
= writemask
;
187 dst_reg::dst_reg(struct brw_reg reg
)
192 this->fixed_hw_reg
= reg
;
195 dst_reg::dst_reg(src_reg reg
)
199 this->file
= reg
.file
;
201 this->reg_offset
= reg
.reg_offset
;
202 this->type
= reg
.type
;
203 /* How should we do writemasking when converting from a src_reg? It seems
204 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
205 * what about for src.wx? Just special-case src.xxxx for now.
207 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
208 this->writemask
= WRITEMASK_X
;
210 this->writemask
= WRITEMASK_XYZW
;
211 this->reladdr
= reg
.reladdr
;
212 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
216 vec4_instruction::is_math()
218 return (opcode
== SHADER_OPCODE_RCP
||
219 opcode
== SHADER_OPCODE_RSQ
||
220 opcode
== SHADER_OPCODE_SQRT
||
221 opcode
== SHADER_OPCODE_EXP2
||
222 opcode
== SHADER_OPCODE_LOG2
||
223 opcode
== SHADER_OPCODE_SIN
||
224 opcode
== SHADER_OPCODE_COS
||
225 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
226 opcode
== SHADER_OPCODE_INT_REMAINDER
||
227 opcode
== SHADER_OPCODE_POW
);
231 vec4_instruction::is_send_from_grf()
234 case SHADER_OPCODE_SHADER_TIME_ADD
:
235 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
243 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
245 if (intel
->gen
== 6 && inst
->is_math())
248 if (inst
->is_send_from_grf())
255 * Returns how many MRFs an opcode will write over.
257 * Note that this is not the 0 or 1 implied writes in an actual gen
258 * instruction -- the generate_* functions generate additional MOVs
262 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
267 switch (inst
->opcode
) {
268 case SHADER_OPCODE_RCP
:
269 case SHADER_OPCODE_RSQ
:
270 case SHADER_OPCODE_SQRT
:
271 case SHADER_OPCODE_EXP2
:
272 case SHADER_OPCODE_LOG2
:
273 case SHADER_OPCODE_SIN
:
274 case SHADER_OPCODE_COS
:
276 case SHADER_OPCODE_POW
:
278 case VS_OPCODE_URB_WRITE
:
280 case VS_OPCODE_PULL_CONSTANT_LOAD
:
282 case VS_OPCODE_SCRATCH_READ
:
284 case VS_OPCODE_SCRATCH_WRITE
:
286 case SHADER_OPCODE_SHADER_TIME_ADD
:
289 assert(!"not reached");
295 src_reg::equals(src_reg
*r
)
297 return (file
== r
->file
&&
299 reg_offset
== r
->reg_offset
&&
301 negate
== r
->negate
&&
303 swizzle
== r
->swizzle
&&
304 !reladdr
&& !r
->reladdr
&&
305 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
306 sizeof(fixed_hw_reg
)) == 0 &&
311 * Must be called after calculate_live_intervales() to remove unused
312 * writes to registers -- register allocation will fail otherwise
313 * because something deffed but not used won't be considered to
314 * interfere with other regs.
317 vec4_visitor::dead_code_eliminate()
319 bool progress
= false;
322 calculate_live_intervals();
324 foreach_list_safe(node
, &this->instructions
) {
325 vec4_instruction
*inst
= (vec4_instruction
*)node
;
327 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
336 live_intervals_valid
= false;
342 vec4_visitor::split_uniform_registers()
344 /* Prior to this, uniforms have been in an array sized according to
345 * the number of vector uniforms present, sparsely filled (so an
346 * aggregate results in reg indices being skipped over). Now we're
347 * going to cut those aggregates up so each .reg index is one
348 * vector. The goal is to make elimination of unused uniform
349 * components easier later.
351 foreach_list(node
, &this->instructions
) {
352 vec4_instruction
*inst
= (vec4_instruction
*)node
;
354 for (int i
= 0 ; i
< 3; i
++) {
355 if (inst
->src
[i
].file
!= UNIFORM
)
358 assert(!inst
->src
[i
].reladdr
);
360 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
361 inst
->src
[i
].reg_offset
= 0;
365 /* Update that everything is now vector-sized. */
366 for (int i
= 0; i
< this->uniforms
; i
++) {
367 this->uniform_size
[i
] = 1;
372 vec4_visitor::pack_uniform_registers()
374 bool uniform_used
[this->uniforms
];
375 int new_loc
[this->uniforms
];
376 int new_chan
[this->uniforms
];
378 memset(uniform_used
, 0, sizeof(uniform_used
));
379 memset(new_loc
, 0, sizeof(new_loc
));
380 memset(new_chan
, 0, sizeof(new_chan
));
382 /* Find which uniform vectors are actually used by the program. We
383 * expect unused vector elements when we've moved array access out
384 * to pull constants, and from some GLSL code generators like wine.
386 foreach_list(node
, &this->instructions
) {
387 vec4_instruction
*inst
= (vec4_instruction
*)node
;
389 for (int i
= 0 ; i
< 3; i
++) {
390 if (inst
->src
[i
].file
!= UNIFORM
)
393 uniform_used
[inst
->src
[i
].reg
] = true;
397 int new_uniform_count
= 0;
399 /* Now, figure out a packing of the live uniform vectors into our
402 for (int src
= 0; src
< uniforms
; src
++) {
403 int size
= this->uniform_vector_size
[src
];
405 if (!uniform_used
[src
]) {
406 this->uniform_vector_size
[src
] = 0;
411 /* Find the lowest place we can slot this uniform in. */
412 for (dst
= 0; dst
< src
; dst
++) {
413 if (this->uniform_vector_size
[dst
] + size
<= 4)
422 new_chan
[src
] = this->uniform_vector_size
[dst
];
424 /* Move the references to the data */
425 for (int j
= 0; j
< size
; j
++) {
426 prog_data
->base
.param
[dst
* 4 + new_chan
[src
] + j
] =
427 prog_data
->base
.param
[src
* 4 + j
];
430 this->uniform_vector_size
[dst
] += size
;
431 this->uniform_vector_size
[src
] = 0;
434 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
437 this->uniforms
= new_uniform_count
;
439 /* Now, update the instructions for our repacked uniforms. */
440 foreach_list(node
, &this->instructions
) {
441 vec4_instruction
*inst
= (vec4_instruction
*)node
;
443 for (int i
= 0 ; i
< 3; i
++) {
444 int src
= inst
->src
[i
].reg
;
446 if (inst
->src
[i
].file
!= UNIFORM
)
449 inst
->src
[i
].reg
= new_loc
[src
];
451 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
452 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
453 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
454 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
455 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
461 src_reg::is_zero() const
466 if (type
== BRW_REGISTER_TYPE_F
) {
474 src_reg::is_one() const
479 if (type
== BRW_REGISTER_TYPE_F
) {
487 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
489 * While GLSL IR also performs this optimization, we end up with it in
490 * our instruction stream for a couple of reasons. One is that we
491 * sometimes generate silly instructions, for example in array access
492 * where we'll generate "ADD offset, index, base" even if base is 0.
493 * The other is that GLSL IR's constant propagation doesn't track the
494 * components of aggregates, so some VS patterns (initialize matrix to
495 * 0, accumulate in vertex blending factors) end up breaking down to
496 * instructions involving 0.
499 vec4_visitor::opt_algebraic()
501 bool progress
= false;
503 foreach_list(node
, &this->instructions
) {
504 vec4_instruction
*inst
= (vec4_instruction
*)node
;
506 switch (inst
->opcode
) {
508 if (inst
->src
[1].is_zero()) {
509 inst
->opcode
= BRW_OPCODE_MOV
;
510 inst
->src
[1] = src_reg();
516 if (inst
->src
[1].is_zero()) {
517 inst
->opcode
= BRW_OPCODE_MOV
;
518 switch (inst
->src
[0].type
) {
519 case BRW_REGISTER_TYPE_F
:
520 inst
->src
[0] = src_reg(0.0f
);
522 case BRW_REGISTER_TYPE_D
:
523 inst
->src
[0] = src_reg(0);
525 case BRW_REGISTER_TYPE_UD
:
526 inst
->src
[0] = src_reg(0u);
529 assert(!"not reached");
530 inst
->src
[0] = src_reg(0.0f
);
533 inst
->src
[1] = src_reg();
535 } else if (inst
->src
[1].is_one()) {
536 inst
->opcode
= BRW_OPCODE_MOV
;
537 inst
->src
[1] = src_reg();
547 this->live_intervals_valid
= false;
553 * Only a limited number of hardware registers may be used for push
554 * constants, so this turns access to the overflowed constants into
558 vec4_visitor::move_push_constants_to_pull_constants()
560 int pull_constant_loc
[this->uniforms
];
562 /* Only allow 32 registers (256 uniform components) as push constants,
563 * which is the limit on gen6.
565 int max_uniform_components
= 32 * 8;
566 if (this->uniforms
* 4 <= max_uniform_components
)
569 /* Make some sort of choice as to which uniforms get sent to pull
570 * constants. We could potentially do something clever here like
571 * look for the most infrequently used uniform vec4s, but leave
574 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
575 pull_constant_loc
[i
/ 4] = -1;
577 if (i
>= max_uniform_components
) {
578 const float **values
= &prog_data
->base
.param
[i
];
580 /* Try to find an existing copy of this uniform in the pull
581 * constants if it was part of an array access already.
583 for (unsigned int j
= 0; j
< prog_data
->base
.nr_pull_params
; j
+= 4) {
586 for (matches
= 0; matches
< 4; matches
++) {
587 if (prog_data
->base
.pull_param
[j
+ matches
] != values
[matches
])
592 pull_constant_loc
[i
/ 4] = j
/ 4;
597 if (pull_constant_loc
[i
/ 4] == -1) {
598 assert(prog_data
->base
.nr_pull_params
% 4 == 0);
599 pull_constant_loc
[i
/ 4] = prog_data
->base
.nr_pull_params
/ 4;
601 for (int j
= 0; j
< 4; j
++) {
602 prog_data
->base
.pull_param
[prog_data
->base
.nr_pull_params
++] = values
[j
];
608 /* Now actually rewrite usage of the things we've moved to pull
611 foreach_list_safe(node
, &this->instructions
) {
612 vec4_instruction
*inst
= (vec4_instruction
*)node
;
614 for (int i
= 0 ; i
< 3; i
++) {
615 if (inst
->src
[i
].file
!= UNIFORM
||
616 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
619 int uniform
= inst
->src
[i
].reg
;
621 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
623 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
624 pull_constant_loc
[uniform
]);
626 inst
->src
[i
].file
= temp
.file
;
627 inst
->src
[i
].reg
= temp
.reg
;
628 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
629 inst
->src
[i
].reladdr
= NULL
;
633 /* Repack push constants to remove the now-unused ones. */
634 pack_uniform_registers();
638 * Sets the dependency control fields on instructions after register
639 * allocation and before the generator is run.
641 * When you have a sequence of instructions like:
643 * DP4 temp.x vertex uniform[0]
644 * DP4 temp.y vertex uniform[0]
645 * DP4 temp.z vertex uniform[0]
646 * DP4 temp.w vertex uniform[0]
648 * The hardware doesn't know that it can actually run the later instructions
649 * while the previous ones are in flight, producing stalls. However, we have
650 * manual fields we can set in the instructions that let it do so.
653 vec4_visitor::opt_set_dependency_control()
655 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
656 uint8_t grf_channels_written
[BRW_MAX_GRF
];
657 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
658 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
662 assert(prog_data
->base
.total_grf
||
663 !"Must be called after register allocation");
665 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
666 bblock_t
*bblock
= cfg
.blocks
[i
];
667 vec4_instruction
*inst
;
669 memset(last_grf_write
, 0, sizeof(last_grf_write
));
670 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
672 for (inst
= (vec4_instruction
*)bblock
->start
;
673 inst
!= (vec4_instruction
*)bblock
->end
->next
;
674 inst
= (vec4_instruction
*)inst
->next
) {
675 /* If we read from a register that we were doing dependency control
676 * on, don't do dependency control across the read.
678 for (int i
= 0; i
< 3; i
++) {
679 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
680 if (inst
->src
[i
].file
== GRF
) {
681 last_grf_write
[reg
] = NULL
;
682 } else if (inst
->src
[i
].file
== HW_REG
) {
683 memset(last_grf_write
, 0, sizeof(last_grf_write
));
686 assert(inst
->src
[i
].file
!= MRF
);
689 /* In the presence of send messages, totally interrupt dependency
690 * control. They're long enough that the chance of dependency
691 * control around them just doesn't matter.
694 memset(last_grf_write
, 0, sizeof(last_grf_write
));
695 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
699 /* It looks like setting dependency control on a predicated
700 * instruction hangs the GPU.
702 if (inst
->predicate
) {
703 memset(last_grf_write
, 0, sizeof(last_grf_write
));
704 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
708 /* Now, see if we can do dependency control for this instruction
709 * against a previous one writing to its destination.
711 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
712 if (inst
->dst
.file
== GRF
) {
713 if (last_grf_write
[reg
] &&
714 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
715 last_grf_write
[reg
]->no_dd_clear
= true;
716 inst
->no_dd_check
= true;
718 grf_channels_written
[reg
] = 0;
721 last_grf_write
[reg
] = inst
;
722 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
723 } else if (inst
->dst
.file
== MRF
) {
724 if (last_mrf_write
[reg
] &&
725 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
726 last_mrf_write
[reg
]->no_dd_clear
= true;
727 inst
->no_dd_check
= true;
729 mrf_channels_written
[reg
] = 0;
732 last_mrf_write
[reg
] = inst
;
733 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
734 } else if (inst
->dst
.reg
== HW_REG
) {
735 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
736 memset(last_grf_write
, 0, sizeof(last_grf_write
));
737 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
738 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
745 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
749 /* If this instruction sets anything not referenced by swizzle, then we'd
750 * totally break it when we reswizzle.
752 if (dst
.writemask
& ~swizzle_mask
)
761 /* Check if there happens to be no reswizzling required. */
762 for (int c
= 0; c
< 4; c
++) {
763 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
764 /* Skip components of the swizzle not used by the dst. */
765 if (!(dst_writemask
& (1 << c
)))
768 /* We don't do the reswizzling yet, so just sanity check that we
779 * For any channels in the swizzle's source that were populated by this
780 * instruction, rewrite the instruction to put the appropriate result directly
783 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
786 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
788 int new_writemask
= 0;
794 for (int c
= 0; c
< 4; c
++) {
795 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
796 /* Skip components of the swizzle not used by the dst. */
797 if (!(dst_writemask
& (1 << c
)))
799 /* If we were populating this component, then populate the
800 * corresponding channel of the new dst.
802 if (dst
.writemask
& bit
)
803 new_writemask
|= (1 << c
);
805 dst
.writemask
= new_writemask
;
808 for (int c
= 0; c
< 4; c
++) {
809 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
810 /* Skip components of the swizzle not used by the dst. */
811 if (!(dst_writemask
& (1 << c
)))
814 /* We don't do the reswizzling yet, so just sanity check that we
817 assert(bit
== (1 << c
));
824 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
825 * just written and then MOVed into another reg and making the original write
826 * of the GRF write directly to the final destination instead.
829 vec4_visitor::opt_register_coalesce()
831 bool progress
= false;
834 calculate_live_intervals();
836 foreach_list_safe(node
, &this->instructions
) {
837 vec4_instruction
*inst
= (vec4_instruction
*)node
;
842 if (inst
->opcode
!= BRW_OPCODE_MOV
||
843 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
845 inst
->src
[0].file
!= GRF
||
846 inst
->dst
.type
!= inst
->src
[0].type
||
847 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
850 bool to_mrf
= (inst
->dst
.file
== MRF
);
852 /* Can't coalesce this GRF if someone else was going to
855 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
858 /* We need to check interference with the final destination between this
859 * instruction and the earliest instruction involved in writing the GRF
860 * we're eliminating. To do that, keep track of which of our source
861 * channels we've seen initialized.
863 bool chans_needed
[4] = {false, false, false, false};
864 int chans_remaining
= 0;
865 int swizzle_mask
= 0;
866 for (int i
= 0; i
< 4; i
++) {
867 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
869 if (!(inst
->dst
.writemask
& (1 << i
)))
872 swizzle_mask
|= (1 << chan
);
874 if (!chans_needed
[chan
]) {
875 chans_needed
[chan
] = true;
880 /* Now walk up the instruction stream trying to see if we can rewrite
881 * everything writing to the temporary to write into the destination
884 vec4_instruction
*scan_inst
;
885 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
886 scan_inst
->prev
!= NULL
;
887 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
888 if (scan_inst
->dst
.file
== GRF
&&
889 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
890 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
891 /* Found something writing to the reg we want to coalesce away. */
893 /* SEND instructions can't have MRF as a destination. */
897 if (intel
->gen
== 6) {
898 /* gen6 math instructions must have the destination be
899 * GRF, so no compute-to-MRF for them.
901 if (scan_inst
->is_math()) {
907 /* If we can't handle the swizzle, bail. */
908 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
909 inst
->src
[0].swizzle
,
914 /* Mark which channels we found unconditional writes for. */
915 if (!scan_inst
->predicate
) {
916 for (int i
= 0; i
< 4; i
++) {
917 if (scan_inst
->dst
.writemask
& (1 << i
) &&
919 chans_needed
[i
] = false;
925 if (chans_remaining
== 0)
929 /* We don't handle flow control here. Most computation of values
930 * that could be coalesced happens just before their use.
932 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
933 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
934 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
935 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
939 /* You can't read from an MRF, so if someone else reads our MRF's
940 * source GRF that we wanted to rewrite, that stops us. If it's a
941 * GRF we're trying to coalesce to, we don't actually handle
942 * rewriting sources so bail in that case as well.
944 bool interfered
= false;
945 for (int i
= 0; i
< 3; i
++) {
946 if (scan_inst
->src
[i
].file
== GRF
&&
947 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
948 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
955 /* If somebody else writes our destination here, we can't coalesce
958 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
959 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
963 /* Check for reads of the register we're trying to coalesce into. We
964 * can't go rewriting instructions above that to put some other value
965 * in the register instead.
967 if (to_mrf
&& scan_inst
->mlen
> 0) {
968 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
969 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
973 for (int i
= 0; i
< 3; i
++) {
974 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
975 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
976 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
985 if (chans_remaining
== 0) {
986 /* If we've made it here, we have an MOV we want to coalesce out, and
987 * a scan_inst pointing to the earliest instruction involved in
988 * computing the value. Now go rewrite the instruction stream
992 while (scan_inst
!= inst
) {
993 if (scan_inst
->dst
.file
== GRF
&&
994 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
995 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
996 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
997 inst
->src
[0].swizzle
);
998 scan_inst
->dst
.file
= inst
->dst
.file
;
999 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1000 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1001 scan_inst
->saturate
|= inst
->saturate
;
1003 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1011 live_intervals_valid
= false;
1017 * Splits virtual GRFs requesting more than one contiguous physical register.
1019 * We initially create large virtual GRFs for temporary structures, arrays,
1020 * and matrices, so that the dereference visitor functions can add reg_offsets
1021 * to work their way down to the actual member being accessed. But when it
1022 * comes to optimization, we'd like to treat each register as individual
1023 * storage if possible.
1025 * So far, the only thing that might prevent splitting is a send message from
1029 vec4_visitor::split_virtual_grfs()
1031 int num_vars
= this->virtual_grf_count
;
1032 int new_virtual_grf
[num_vars
];
1033 bool split_grf
[num_vars
];
1035 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1037 /* Try to split anything > 0 sized. */
1038 for (int i
= 0; i
< num_vars
; i
++) {
1039 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1042 /* Check that the instructions are compatible with the registers we're trying
1045 foreach_list(node
, &this->instructions
) {
1046 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1048 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1049 * contiguous. Assume that the GRF for the SEND is always in src[0].
1051 if (inst
->is_send_from_grf()) {
1052 split_grf
[inst
->src
[0].reg
] = false;
1056 /* Allocate new space for split regs. Note that the virtual
1057 * numbers will be contiguous.
1059 for (int i
= 0; i
< num_vars
; i
++) {
1063 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1064 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1065 int reg
= virtual_grf_alloc(1);
1066 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1069 this->virtual_grf_sizes
[i
] = 1;
1072 foreach_list(node
, &this->instructions
) {
1073 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1075 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1076 inst
->dst
.reg_offset
!= 0) {
1077 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1078 inst
->dst
.reg_offset
- 1);
1079 inst
->dst
.reg_offset
= 0;
1081 for (int i
= 0; i
< 3; i
++) {
1082 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1083 inst
->src
[i
].reg_offset
!= 0) {
1084 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1085 inst
->src
[i
].reg_offset
- 1);
1086 inst
->src
[i
].reg_offset
= 0;
1090 this->live_intervals_valid
= false;
1094 vec4_visitor::dump_instruction(vec4_instruction
*inst
)
1096 printf("%s ", brw_instruction_name(inst
->opcode
));
1098 switch (inst
->dst
.file
) {
1100 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1103 printf("m%d", inst
->dst
.reg
);
1112 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1114 if (inst
->dst
.writemask
& 1)
1116 if (inst
->dst
.writemask
& 2)
1118 if (inst
->dst
.writemask
& 4)
1120 if (inst
->dst
.writemask
& 8)
1125 for (int i
= 0; i
< 3; i
++) {
1126 switch (inst
->src
[i
].file
) {
1128 printf("vgrf%d", inst
->src
[i
].reg
);
1131 printf("attr%d", inst
->src
[i
].reg
);
1134 printf("u%d", inst
->src
[i
].reg
);
1137 switch (inst
->src
[i
].type
) {
1138 case BRW_REGISTER_TYPE_F
:
1139 printf("%fF", inst
->src
[i
].imm
.f
);
1141 case BRW_REGISTER_TYPE_D
:
1142 printf("%dD", inst
->src
[i
].imm
.i
);
1144 case BRW_REGISTER_TYPE_UD
:
1145 printf("%uU", inst
->src
[i
].imm
.u
);
1160 if (inst
->src
[i
].reg_offset
)
1161 printf(".%d", inst
->src
[i
].reg_offset
);
1163 static const char *chans
[4] = {"x", "y", "z", "w"};
1165 for (int c
= 0; c
< 4; c
++) {
1166 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1177 vec4_visitor::dump_instructions()
1180 foreach_list_safe(node
, &this->instructions
) {
1181 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1182 printf("%d: ", ip
++);
1183 dump_instruction(inst
);
1188 vec4_vs_visitor::setup_attributes(int payload_reg
)
1191 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1194 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1195 if (prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1196 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1201 /* VertexID is stored by the VF as the last vertex element, but we
1202 * don't represent it with a flag in inputs_read, so we call it
1205 if (prog_data
->uses_vertexid
) {
1206 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1210 foreach_list(node
, &this->instructions
) {
1211 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1213 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1214 if (inst
->dst
.file
== ATTR
) {
1215 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1217 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1218 reg
.type
= inst
->dst
.type
;
1219 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1221 inst
->dst
.file
= HW_REG
;
1222 inst
->dst
.fixed_hw_reg
= reg
;
1225 for (int i
= 0; i
< 3; i
++) {
1226 if (inst
->src
[i
].file
!= ATTR
)
1229 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1231 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1232 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1233 reg
.type
= inst
->src
[i
].type
;
1234 if (inst
->src
[i
].abs
)
1236 if (inst
->src
[i
].negate
)
1239 inst
->src
[i
].file
= HW_REG
;
1240 inst
->src
[i
].fixed_hw_reg
= reg
;
1244 /* The BSpec says we always have to read at least one thing from
1245 * the VF, and it appears that the hardware wedges otherwise.
1247 if (nr_attributes
== 0)
1250 prog_data
->base
.urb_read_length
= (nr_attributes
+ 1) / 2;
1252 unsigned vue_entries
=
1253 MAX2(nr_attributes
, prog_data
->base
.vue_map
.num_slots
);
1255 if (intel
->gen
== 6)
1256 prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1258 prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1260 return payload_reg
+ nr_attributes
;
1264 vec4_visitor::setup_uniforms(int reg
)
1266 /* The pre-gen6 VS requires that some push constants get loaded no
1267 * matter what, or the GPU would hang.
1269 if (intel
->gen
< 6 && this->uniforms
== 0) {
1270 this->uniform_vector_size
[this->uniforms
] = 1;
1272 for (unsigned int i
= 0; i
< 4; i
++) {
1273 unsigned int slot
= this->uniforms
* 4 + i
;
1274 static float zero
= 0.0;
1275 prog_data
->base
.param
[slot
] = &zero
;
1281 reg
+= ALIGN(uniforms
, 2) / 2;
1284 prog_data
->base
.nr_params
= this->uniforms
* 4;
1286 prog_data
->base
.curb_read_length
= reg
- 1;
1292 vec4_visitor::setup_payload(void)
1296 /* The payload always contains important data in g0, which contains
1297 * the URB handles that are passed on to the URB write at the end
1298 * of the thread. So, we always start push constants at g1.
1302 reg
= setup_uniforms(reg
);
1304 reg
= setup_attributes(reg
);
1306 this->first_non_payload_grf
= reg
;
1310 vec4_visitor::get_timestamp()
1312 assert(intel
->gen
>= 7);
1314 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1317 BRW_REGISTER_TYPE_UD
,
1318 BRW_VERTICAL_STRIDE_0
,
1320 BRW_HORIZONTAL_STRIDE_4
,
1324 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1326 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1327 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1328 * even if it's not enabled in the dispatch.
1330 mov
->force_writemask_all
= true;
1332 return src_reg(dst
);
1336 vec4_visitor::emit_shader_time_begin()
1338 current_annotation
= "shader time start";
1339 shader_start_time
= get_timestamp();
1343 vec4_visitor::emit_shader_time_end()
1345 current_annotation
= "shader time end";
1346 src_reg shader_end_time
= get_timestamp();
1349 /* Check that there weren't any timestamp reset events (assuming these
1350 * were the only two timestamp reads that happened).
1352 src_reg reset_end
= shader_end_time
;
1353 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1354 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1355 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1357 emit(IF(BRW_PREDICATE_NORMAL
));
1359 /* Take the current timestamp and get the delta. */
1360 shader_start_time
.negate
= true;
1361 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1362 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1364 /* If there were no instructions between the two timestamp gets, the diff
1365 * is 2 cycles. Remove that overhead, so I can forget about that when
1366 * trying to determine the time taken for single instructions.
1368 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1370 emit_shader_time_write(ST_VS
, src_reg(diff
));
1371 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1372 emit(BRW_OPCODE_ELSE
);
1373 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1374 emit(BRW_OPCODE_ENDIF
);
1378 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1381 int shader_time_index
=
1382 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1385 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1387 dst_reg offset
= dst
;
1391 offset
.type
= BRW_REGISTER_TYPE_UD
;
1392 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1394 time
.type
= BRW_REGISTER_TYPE_UD
;
1395 emit(MOV(time
, src_reg(value
)));
1397 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1403 sanity_param_count
= prog
->Parameters
->NumParameters
;
1405 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1406 emit_shader_time_begin();
1410 /* Generate VS IR for main(). (the visitor only descends into
1411 * functions called "main").
1414 visit_instructions(shader
->ir
);
1416 emit_program_code();
1420 if (c
->key
.base
.userclip_active
&& !c
->key
.base
.uses_clip_distance
)
1421 setup_uniform_clipplane_values();
1425 /* Before any optimization, push array accesses out to scratch
1426 * space where we need them to be. This pass may allocate new
1427 * virtual GRFs, so we want to do it early. It also makes sure
1428 * that we have reladdr computations available for CSE, since we'll
1429 * often do repeated subexpressions for those.
1432 move_grf_array_access_to_scratch();
1433 move_uniform_array_access_to_pull_constants();
1435 /* The ARB_vertex_program frontend emits pull constant loads directly
1436 * rather than using reladdr, so we don't need to walk through all the
1437 * instructions looking for things to move. There isn't anything.
1439 * We do still need to split things to vec4 size.
1441 split_uniform_registers();
1443 pack_uniform_registers();
1444 move_push_constants_to_pull_constants();
1445 split_virtual_grfs();
1450 progress
= dead_code_eliminate() || progress
;
1451 progress
= opt_copy_propagation() || progress
;
1452 progress
= opt_algebraic() || progress
;
1453 progress
= opt_register_coalesce() || progress
;
1463 /* Debug of register spilling: Go spill everything. */
1464 const int grf_count
= virtual_grf_count
;
1465 float spill_costs
[virtual_grf_count
];
1466 bool no_spill
[virtual_grf_count
];
1467 evaluate_spill_costs(spill_costs
, no_spill
);
1468 for (int i
= 0; i
< grf_count
; i
++) {
1475 while (!reg_allocate()) {
1480 opt_set_dependency_control();
1482 /* If any state parameters were appended, then ParameterValues could have
1483 * been realloced, in which case the driver uniform storage set up by
1484 * _mesa_associate_uniform_storage() would point to freed memory. Make
1485 * sure that didn't happen.
1487 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1492 } /* namespace brw */
1497 * Compile a vertex shader.
1499 * Returns the final assembly and the program's size.
1502 brw_vs_emit(struct brw_context
*brw
,
1503 struct gl_shader_program
*prog
,
1504 struct brw_vs_compile
*c
,
1505 struct brw_vs_prog_data
*prog_data
,
1507 unsigned *final_assembly_size
)
1509 struct intel_context
*intel
= &brw
->intel
;
1510 bool start_busy
= false;
1511 float start_time
= 0;
1513 if (unlikely(intel
->perf_debug
)) {
1514 start_busy
= (intel
->batch
.last_bo
&&
1515 drm_intel_bo_busy(intel
->batch
.last_bo
));
1516 start_time
= get_time();
1519 struct brw_shader
*shader
= NULL
;
1521 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1523 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1525 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1526 _mesa_print_ir(shader
->ir
, NULL
);
1529 printf("ARB_vertex_program %d for native vertex shader\n",
1530 c
->vp
->program
.Base
.Id
);
1531 _mesa_print_program(&c
->vp
->program
.Base
);
1535 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1537 prog
->LinkStatus
= false;
1538 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1542 vec4_generator
g(brw
, c
, prog
, mem_ctx
);
1543 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1544 final_assembly_size
);
1546 if (unlikely(intel
->perf_debug
) && shader
) {
1547 if (shader
->compiled_once
) {
1548 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1550 if (start_busy
&& !drm_intel_bo_busy(intel
->batch
.last_bo
)) {
1551 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1552 (get_time() - start_time
) * 1000);
1554 shader
->compiled_once
= true;