2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(float f
)
79 this->type
= BRW_REGISTER_TYPE_F
;
80 this->fixed_hw_reg
.dw1
.f
= f
;
83 src_reg::src_reg(uint32_t u
)
88 this->type
= BRW_REGISTER_TYPE_UD
;
89 this->fixed_hw_reg
.dw1
.ud
= u
;
92 src_reg::src_reg(int32_t i
)
97 this->type
= BRW_REGISTER_TYPE_D
;
98 this->fixed_hw_reg
.dw1
.d
= i
;
101 src_reg::src_reg(uint8_t vf
[4])
106 this->type
= BRW_REGISTER_TYPE_VF
;
107 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
110 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
115 this->type
= BRW_REGISTER_TYPE_VF
;
116 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
122 src_reg::src_reg(struct brw_reg reg
)
127 this->fixed_hw_reg
= reg
;
128 this->type
= reg
.type
;
131 src_reg::src_reg(const dst_reg
®
)
135 this->file
= reg
.file
;
137 this->reg_offset
= reg
.reg_offset
;
138 this->type
= reg
.type
;
139 this->reladdr
= reg
.reladdr
;
140 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
141 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(register_file file
, int reg
, brw_reg_type type
,
184 this->writemask
= writemask
;
187 dst_reg::dst_reg(struct brw_reg reg
)
192 this->fixed_hw_reg
= reg
;
193 this->type
= reg
.type
;
196 dst_reg::dst_reg(const src_reg
®
)
200 this->file
= reg
.file
;
202 this->reg_offset
= reg
.reg_offset
;
203 this->type
= reg
.type
;
204 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
205 this->reladdr
= reg
.reladdr
;
206 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
210 dst_reg::equals(const dst_reg
&r
) const
212 return (file
== r
.file
&&
214 reg_offset
== r
.reg_offset
&&
216 negate
== r
.negate
&&
218 writemask
== r
.writemask
&&
219 (reladdr
== r
.reladdr
||
220 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
221 ((file
!= HW_REG
&& file
!= IMM
) ||
222 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
223 sizeof(fixed_hw_reg
)) == 0));
227 vec4_instruction::is_send_from_grf()
230 case SHADER_OPCODE_SHADER_TIME_ADD
:
231 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
232 case SHADER_OPCODE_UNTYPED_ATOMIC
:
233 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
234 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
235 case SHADER_OPCODE_TYPED_ATOMIC
:
236 case SHADER_OPCODE_TYPED_SURFACE_READ
:
237 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
245 vec4_instruction::regs_read(unsigned arg
) const
247 if (src
[arg
].file
== BAD_FILE
)
251 case SHADER_OPCODE_SHADER_TIME_ADD
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 return arg
== 0 ? mlen
: 1;
260 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
261 return arg
== 1 ? mlen
: 1;
269 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
271 if (devinfo
->gen
== 6 && is_math())
274 if (is_send_from_grf())
277 if (!backend_instruction::can_do_source_mods())
284 vec4_instruction::can_change_types() const
286 return dst
.type
== src
[0].type
&&
287 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
288 (opcode
== BRW_OPCODE_MOV
||
289 (opcode
== BRW_OPCODE_SEL
&&
290 dst
.type
== src
[1].type
&&
291 predicate
!= BRW_PREDICATE_NONE
&&
292 !src
[1].abs
&& !src
[1].negate
));
296 * Returns how many MRFs an opcode will write over.
298 * Note that this is not the 0 or 1 implied writes in an actual gen
299 * instruction -- the generate_* functions generate additional MOVs
303 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
305 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
308 switch (inst
->opcode
) {
309 case SHADER_OPCODE_RCP
:
310 case SHADER_OPCODE_RSQ
:
311 case SHADER_OPCODE_SQRT
:
312 case SHADER_OPCODE_EXP2
:
313 case SHADER_OPCODE_LOG2
:
314 case SHADER_OPCODE_SIN
:
315 case SHADER_OPCODE_COS
:
317 case SHADER_OPCODE_INT_QUOTIENT
:
318 case SHADER_OPCODE_INT_REMAINDER
:
319 case SHADER_OPCODE_POW
:
321 case VS_OPCODE_URB_WRITE
:
323 case VS_OPCODE_PULL_CONSTANT_LOAD
:
325 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
327 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
329 case GS_OPCODE_URB_WRITE
:
330 case GS_OPCODE_URB_WRITE_ALLOCATE
:
331 case GS_OPCODE_THREAD_END
:
333 case GS_OPCODE_FF_SYNC
:
335 case SHADER_OPCODE_SHADER_TIME_ADD
:
337 case SHADER_OPCODE_TEX
:
338 case SHADER_OPCODE_TXL
:
339 case SHADER_OPCODE_TXD
:
340 case SHADER_OPCODE_TXF
:
341 case SHADER_OPCODE_TXF_CMS
:
342 case SHADER_OPCODE_TXF_MCS
:
343 case SHADER_OPCODE_TXS
:
344 case SHADER_OPCODE_TG4
:
345 case SHADER_OPCODE_TG4_OFFSET
:
346 case SHADER_OPCODE_SAMPLEINFO
:
347 case VS_OPCODE_GET_BUFFER_SIZE
:
348 return inst
->header_size
;
350 unreachable("not reached");
355 src_reg::equals(const src_reg
&r
) const
357 return (file
== r
.file
&&
359 reg_offset
== r
.reg_offset
&&
361 negate
== r
.negate
&&
363 swizzle
== r
.swizzle
&&
364 !reladdr
&& !r
.reladdr
&&
365 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
366 sizeof(fixed_hw_reg
)) == 0);
370 vec4_visitor::opt_vector_float()
372 bool progress
= false;
374 int last_reg
= -1, last_reg_offset
= -1;
375 enum register_file last_reg_file
= BAD_FILE
;
377 int remaining_channels
= 0;
380 vec4_instruction
*imm_inst
[4];
382 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
383 if (last_reg
!= inst
->dst
.reg
||
384 last_reg_offset
!= inst
->dst
.reg_offset
||
385 last_reg_file
!= inst
->dst
.file
) {
386 last_reg
= inst
->dst
.reg
;
387 last_reg_offset
= inst
->dst
.reg_offset
;
388 last_reg_file
= inst
->dst
.file
;
389 remaining_channels
= WRITEMASK_XYZW
;
394 if (inst
->opcode
!= BRW_OPCODE_MOV
||
395 inst
->dst
.writemask
== WRITEMASK_XYZW
||
396 inst
->src
[0].file
!= IMM
)
399 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
403 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
405 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
407 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
409 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
412 imm_inst
[inst_count
++] = inst
;
414 remaining_channels
&= ~inst
->dst
.writemask
;
415 if (remaining_channels
== 0) {
416 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
417 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
418 mov
->dst
.writemask
= WRITEMASK_XYZW
;
419 inst
->insert_after(block
, mov
);
422 for (int i
= 0; i
< inst_count
; i
++) {
423 imm_inst
[i
]->remove(block
);
430 invalidate_live_intervals();
435 /* Replaces unused channels of a swizzle with channels that are used.
437 * For instance, this pass transforms
439 * mov vgrf4.yz, vgrf5.wxzy
443 * mov vgrf4.yz, vgrf5.xxzx
445 * This eliminates false uses of some channels, letting dead code elimination
446 * remove the instructions that wrote them.
449 vec4_visitor::opt_reduce_swizzle()
451 bool progress
= false;
453 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
454 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
455 inst
->is_send_from_grf())
460 /* Determine which channels of the sources are read. */
461 switch (inst
->opcode
) {
462 case VEC4_OPCODE_PACK_BYTES
:
464 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
465 * but all four of src1.
467 swizzle
= brw_swizzle_for_size(4);
470 swizzle
= brw_swizzle_for_size(3);
473 swizzle
= brw_swizzle_for_size(2);
476 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
480 /* Update sources' swizzles. */
481 for (int i
= 0; i
< 3; i
++) {
482 if (inst
->src
[i
].file
!= GRF
&&
483 inst
->src
[i
].file
!= ATTR
&&
484 inst
->src
[i
].file
!= UNIFORM
)
487 const unsigned new_swizzle
=
488 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
489 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
490 inst
->src
[i
].swizzle
= new_swizzle
;
497 invalidate_live_intervals();
503 vec4_visitor::split_uniform_registers()
505 /* Prior to this, uniforms have been in an array sized according to
506 * the number of vector uniforms present, sparsely filled (so an
507 * aggregate results in reg indices being skipped over). Now we're
508 * going to cut those aggregates up so each .reg index is one
509 * vector. The goal is to make elimination of unused uniform
510 * components easier later.
512 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
513 for (int i
= 0 ; i
< 3; i
++) {
514 if (inst
->src
[i
].file
!= UNIFORM
)
517 assert(!inst
->src
[i
].reladdr
);
519 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
520 inst
->src
[i
].reg_offset
= 0;
524 /* Update that everything is now vector-sized. */
525 for (int i
= 0; i
< this->uniforms
; i
++) {
526 this->uniform_size
[i
] = 1;
531 vec4_visitor::pack_uniform_registers()
533 uint8_t chans_used
[this->uniforms
];
534 int new_loc
[this->uniforms
];
535 int new_chan
[this->uniforms
];
537 memset(chans_used
, 0, sizeof(chans_used
));
538 memset(new_loc
, 0, sizeof(new_loc
));
539 memset(new_chan
, 0, sizeof(new_chan
));
541 /* Find which uniform vectors are actually used by the program. We
542 * expect unused vector elements when we've moved array access out
543 * to pull constants, and from some GLSL code generators like wine.
545 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
547 switch (inst
->opcode
) {
548 case VEC4_OPCODE_PACK_BYTES
:
560 readmask
= inst
->dst
.writemask
;
564 for (int i
= 0 ; i
< 3; i
++) {
565 if (inst
->src
[i
].file
!= UNIFORM
)
568 int reg
= inst
->src
[i
].reg
;
569 for (int c
= 0; c
< 4; c
++) {
570 if (!(readmask
& (1 << c
)))
573 chans_used
[reg
] = MAX2(chans_used
[reg
],
574 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
579 int new_uniform_count
= 0;
581 /* Now, figure out a packing of the live uniform vectors into our
584 for (int src
= 0; src
< uniforms
; src
++) {
585 assert(src
< uniform_array_size
);
586 int size
= chans_used
[src
];
592 /* Find the lowest place we can slot this uniform in. */
593 for (dst
= 0; dst
< src
; dst
++) {
594 if (chans_used
[dst
] + size
<= 4)
603 new_chan
[src
] = chans_used
[dst
];
605 /* Move the references to the data */
606 for (int j
= 0; j
< size
; j
++) {
607 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
608 stage_prog_data
->param
[src
* 4 + j
];
611 chans_used
[dst
] += size
;
615 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
618 this->uniforms
= new_uniform_count
;
620 /* Now, update the instructions for our repacked uniforms. */
621 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
622 for (int i
= 0 ; i
< 3; i
++) {
623 int src
= inst
->src
[i
].reg
;
625 if (inst
->src
[i
].file
!= UNIFORM
)
628 inst
->src
[i
].reg
= new_loc
[src
];
629 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
630 new_chan
[src
], new_chan
[src
]);
636 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
638 * While GLSL IR also performs this optimization, we end up with it in
639 * our instruction stream for a couple of reasons. One is that we
640 * sometimes generate silly instructions, for example in array access
641 * where we'll generate "ADD offset, index, base" even if base is 0.
642 * The other is that GLSL IR's constant propagation doesn't track the
643 * components of aggregates, so some VS patterns (initialize matrix to
644 * 0, accumulate in vertex blending factors) end up breaking down to
645 * instructions involving 0.
648 vec4_visitor::opt_algebraic()
650 bool progress
= false;
652 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
653 switch (inst
->opcode
) {
655 if (inst
->src
[0].file
!= IMM
)
658 if (inst
->saturate
) {
659 if (inst
->dst
.type
!= inst
->src
[0].type
)
660 assert(!"unimplemented: saturate mixed types");
662 if (brw_saturate_immediate(inst
->dst
.type
,
663 &inst
->src
[0].fixed_hw_reg
)) {
664 inst
->saturate
= false;
670 case VEC4_OPCODE_UNPACK_UNIFORM
:
671 if (inst
->src
[0].file
!= UNIFORM
) {
672 inst
->opcode
= BRW_OPCODE_MOV
;
678 if (inst
->src
[1].is_zero()) {
679 inst
->opcode
= BRW_OPCODE_MOV
;
680 inst
->src
[1] = src_reg();
686 if (inst
->src
[1].is_zero()) {
687 inst
->opcode
= BRW_OPCODE_MOV
;
688 switch (inst
->src
[0].type
) {
689 case BRW_REGISTER_TYPE_F
:
690 inst
->src
[0] = src_reg(0.0f
);
692 case BRW_REGISTER_TYPE_D
:
693 inst
->src
[0] = src_reg(0);
695 case BRW_REGISTER_TYPE_UD
:
696 inst
->src
[0] = src_reg(0u);
699 unreachable("not reached");
701 inst
->src
[1] = src_reg();
703 } else if (inst
->src
[1].is_one()) {
704 inst
->opcode
= BRW_OPCODE_MOV
;
705 inst
->src
[1] = src_reg();
707 } else if (inst
->src
[1].is_negative_one()) {
708 inst
->opcode
= BRW_OPCODE_MOV
;
709 inst
->src
[0].negate
= !inst
->src
[0].negate
;
710 inst
->src
[1] = src_reg();
715 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
717 inst
->src
[0].negate
&&
718 inst
->src
[1].is_zero()) {
719 inst
->src
[0].abs
= false;
720 inst
->src
[0].negate
= false;
721 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
726 case SHADER_OPCODE_RCP
: {
727 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
728 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
729 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
730 inst
->opcode
= SHADER_OPCODE_RSQ
;
731 inst
->src
[0] = prev
->src
[0];
737 case SHADER_OPCODE_BROADCAST
:
738 if (is_uniform(inst
->src
[0]) ||
739 inst
->src
[1].is_zero()) {
740 inst
->opcode
= BRW_OPCODE_MOV
;
741 inst
->src
[1] = src_reg();
742 inst
->force_writemask_all
= true;
753 invalidate_live_intervals();
759 * Only a limited number of hardware registers may be used for push
760 * constants, so this turns access to the overflowed constants into
764 vec4_visitor::move_push_constants_to_pull_constants()
766 int pull_constant_loc
[this->uniforms
];
768 /* Only allow 32 registers (256 uniform components) as push constants,
769 * which is the limit on gen6.
771 * If changing this value, note the limitation about total_regs in
774 int max_uniform_components
= 32 * 8;
775 if (this->uniforms
* 4 <= max_uniform_components
)
778 /* Make some sort of choice as to which uniforms get sent to pull
779 * constants. We could potentially do something clever here like
780 * look for the most infrequently used uniform vec4s, but leave
783 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
784 pull_constant_loc
[i
/ 4] = -1;
786 if (i
>= max_uniform_components
) {
787 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
789 /* Try to find an existing copy of this uniform in the pull
790 * constants if it was part of an array access already.
792 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
795 for (matches
= 0; matches
< 4; matches
++) {
796 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
801 pull_constant_loc
[i
/ 4] = j
/ 4;
806 if (pull_constant_loc
[i
/ 4] == -1) {
807 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
808 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
810 for (int j
= 0; j
< 4; j
++) {
811 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
818 /* Now actually rewrite usage of the things we've moved to pull
821 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
822 for (int i
= 0 ; i
< 3; i
++) {
823 if (inst
->src
[i
].file
!= UNIFORM
||
824 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
827 int uniform
= inst
->src
[i
].reg
;
829 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
831 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
832 pull_constant_loc
[uniform
]);
834 inst
->src
[i
].file
= temp
.file
;
835 inst
->src
[i
].reg
= temp
.reg
;
836 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
837 inst
->src
[i
].reladdr
= NULL
;
841 /* Repack push constants to remove the now-unused ones. */
842 pack_uniform_registers();
845 /* Conditions for which we want to avoid setting the dependency control bits */
847 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
849 #define IS_DWORD(reg) \
850 (reg.type == BRW_REGISTER_TYPE_UD || \
851 reg.type == BRW_REGISTER_TYPE_D)
853 /* "When source or destination datatype is 64b or operation is integer DWord
854 * multiply, DepCtrl must not be used."
855 * May apply to future SoCs as well.
857 if (devinfo
->is_cherryview
) {
858 if (inst
->opcode
== BRW_OPCODE_MUL
&&
859 IS_DWORD(inst
->src
[0]) &&
860 IS_DWORD(inst
->src
[1]))
865 if (devinfo
->gen
>= 8) {
866 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
872 * In the presence of send messages, totally interrupt dependency
873 * control. They're long enough that the chance of dependency
874 * control around them just doesn't matter.
877 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
878 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
879 * completes the scoreboard clear must have a non-zero execution mask. This
880 * means, if any kind of predication can change the execution mask or channel
881 * enable of the last instruction, the optimization must be avoided. This is
882 * to avoid instructions being shot down the pipeline when no writes are
886 * Dependency control does not work well over math instructions.
887 * NB: Discovered empirically
889 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
893 * Sets the dependency control fields on instructions after register
894 * allocation and before the generator is run.
896 * When you have a sequence of instructions like:
898 * DP4 temp.x vertex uniform[0]
899 * DP4 temp.y vertex uniform[0]
900 * DP4 temp.z vertex uniform[0]
901 * DP4 temp.w vertex uniform[0]
903 * The hardware doesn't know that it can actually run the later instructions
904 * while the previous ones are in flight, producing stalls. However, we have
905 * manual fields we can set in the instructions that let it do so.
908 vec4_visitor::opt_set_dependency_control()
910 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
911 uint8_t grf_channels_written
[BRW_MAX_GRF
];
912 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
913 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
915 assert(prog_data
->total_grf
||
916 !"Must be called after register allocation");
918 foreach_block (block
, cfg
) {
919 memset(last_grf_write
, 0, sizeof(last_grf_write
));
920 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
922 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
923 /* If we read from a register that we were doing dependency control
924 * on, don't do dependency control across the read.
926 for (int i
= 0; i
< 3; i
++) {
927 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
928 if (inst
->src
[i
].file
== GRF
) {
929 last_grf_write
[reg
] = NULL
;
930 } else if (inst
->src
[i
].file
== HW_REG
) {
931 memset(last_grf_write
, 0, sizeof(last_grf_write
));
934 assert(inst
->src
[i
].file
!= MRF
);
937 if (is_dep_ctrl_unsafe(inst
)) {
938 memset(last_grf_write
, 0, sizeof(last_grf_write
));
939 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
943 /* Now, see if we can do dependency control for this instruction
944 * against a previous one writing to its destination.
946 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
947 if (inst
->dst
.file
== GRF
) {
948 if (last_grf_write
[reg
] &&
949 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
950 last_grf_write
[reg
]->no_dd_clear
= true;
951 inst
->no_dd_check
= true;
953 grf_channels_written
[reg
] = 0;
956 last_grf_write
[reg
] = inst
;
957 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
958 } else if (inst
->dst
.file
== MRF
) {
959 if (last_mrf_write
[reg
] &&
960 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
961 last_mrf_write
[reg
]->no_dd_clear
= true;
962 inst
->no_dd_check
= true;
964 mrf_channels_written
[reg
] = 0;
967 last_mrf_write
[reg
] = inst
;
968 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
969 } else if (inst
->dst
.reg
== HW_REG
) {
970 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
971 memset(last_grf_write
, 0, sizeof(last_grf_write
));
972 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
973 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
980 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
985 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
986 * or writemasking are not allowed.
988 if (devinfo
->gen
== 6 && is_math() &&
989 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
992 /* If this instruction sets anything not referenced by swizzle, then we'd
993 * totally break it when we reswizzle.
995 if (dst
.writemask
& ~swizzle_mask
)
1001 /* We can't use swizzles on the accumulator and that's really the only
1002 * HW_REG we would care to reswizzle so just disallow them all.
1004 for (int i
= 0; i
< 3; i
++) {
1005 if (src
[i
].file
== HW_REG
)
1013 * For any channels in the swizzle's source that were populated by this
1014 * instruction, rewrite the instruction to put the appropriate result directly
1015 * in those channels.
1017 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1020 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1022 /* Destination write mask doesn't correspond to source swizzle for the dot
1023 * product and pack_bytes instructions.
1025 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1026 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1027 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1028 for (int i
= 0; i
< 3; i
++) {
1029 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1032 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1036 /* Apply the specified swizzle and writemask to the original mask of
1037 * written components.
1039 dst
.writemask
= dst_writemask
&
1040 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1044 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1045 * just written and then MOVed into another reg and making the original write
1046 * of the GRF write directly to the final destination instead.
1049 vec4_visitor::opt_register_coalesce()
1051 bool progress
= false;
1054 calculate_live_intervals();
1056 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1060 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1061 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1063 inst
->src
[0].file
!= GRF
||
1064 inst
->dst
.type
!= inst
->src
[0].type
||
1065 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1068 /* Remove no-op MOVs */
1069 if (inst
->dst
.file
== inst
->src
[0].file
&&
1070 inst
->dst
.reg
== inst
->src
[0].reg
&&
1071 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1072 bool is_nop_mov
= true;
1074 for (unsigned c
= 0; c
< 4; c
++) {
1075 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1078 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1085 inst
->remove(block
);
1090 bool to_mrf
= (inst
->dst
.file
== MRF
);
1092 /* Can't coalesce this GRF if someone else was going to
1095 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1098 /* We need to check interference with the final destination between this
1099 * instruction and the earliest instruction involved in writing the GRF
1100 * we're eliminating. To do that, keep track of which of our source
1101 * channels we've seen initialized.
1103 const unsigned chans_needed
=
1104 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1105 inst
->dst
.writemask
);
1106 unsigned chans_remaining
= chans_needed
;
1108 /* Now walk up the instruction stream trying to see if we can rewrite
1109 * everything writing to the temporary to write into the destination
1112 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1113 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1115 _scan_inst
= scan_inst
;
1117 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1118 /* Found something writing to the reg we want to coalesce away. */
1120 /* SEND instructions can't have MRF as a destination. */
1121 if (scan_inst
->mlen
)
1124 if (devinfo
->gen
== 6) {
1125 /* gen6 math instructions must have the destination be
1126 * GRF, so no compute-to-MRF for them.
1128 if (scan_inst
->is_math()) {
1134 /* This doesn't handle saturation on the instruction we
1135 * want to coalesce away if the register types do not match.
1136 * But if scan_inst is a non type-converting 'mov', we can fix
1139 if (inst
->saturate
&&
1140 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1141 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1142 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1145 /* If we can't handle the swizzle, bail. */
1146 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1147 inst
->src
[0].swizzle
,
1152 /* This doesn't handle coalescing of multiple registers. */
1153 if (scan_inst
->regs_written
> 1)
1156 /* Mark which channels we found unconditional writes for. */
1157 if (!scan_inst
->predicate
)
1158 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1160 if (chans_remaining
== 0)
1164 /* You can't read from an MRF, so if someone else reads our MRF's
1165 * source GRF that we wanted to rewrite, that stops us. If it's a
1166 * GRF we're trying to coalesce to, we don't actually handle
1167 * rewriting sources so bail in that case as well.
1169 bool interfered
= false;
1170 for (int i
= 0; i
< 3; i
++) {
1171 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1172 scan_inst
->regs_read(i
)))
1178 /* If somebody else writes the same channels of our destination here,
1179 * we can't coalesce before that.
1181 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1182 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1186 /* Check for reads of the register we're trying to coalesce into. We
1187 * can't go rewriting instructions above that to put some other value
1188 * in the register instead.
1190 if (to_mrf
&& scan_inst
->mlen
> 0) {
1191 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1192 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1196 for (int i
= 0; i
< 3; i
++) {
1197 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1198 scan_inst
->regs_read(i
)))
1206 if (chans_remaining
== 0) {
1207 /* If we've made it here, we have an MOV we want to coalesce out, and
1208 * a scan_inst pointing to the earliest instruction involved in
1209 * computing the value. Now go rewrite the instruction stream
1212 vec4_instruction
*scan_inst
= _scan_inst
;
1213 while (scan_inst
!= inst
) {
1214 if (scan_inst
->dst
.file
== GRF
&&
1215 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1216 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1217 scan_inst
->reswizzle(inst
->dst
.writemask
,
1218 inst
->src
[0].swizzle
);
1219 scan_inst
->dst
.file
= inst
->dst
.file
;
1220 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1221 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1222 if (inst
->saturate
&&
1223 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1224 /* If we have reached this point, scan_inst is a non
1225 * type-converting 'mov' and we can modify its register types
1226 * to match the ones in inst. Otherwise, we could have an
1227 * incorrect saturation result.
1229 scan_inst
->dst
.type
= inst
->dst
.type
;
1230 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1232 scan_inst
->saturate
|= inst
->saturate
;
1234 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1236 inst
->remove(block
);
1242 invalidate_live_intervals();
1248 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1249 * flow. We could probably do better here with some form of divergence
1253 vec4_visitor::eliminate_find_live_channel()
1255 bool progress
= false;
1258 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1259 switch (inst
->opcode
) {
1265 case BRW_OPCODE_ENDIF
:
1266 case BRW_OPCODE_WHILE
:
1270 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1272 inst
->opcode
= BRW_OPCODE_MOV
;
1273 inst
->src
[0] = src_reg(0);
1274 inst
->force_writemask_all
= true;
1288 * Splits virtual GRFs requesting more than one contiguous physical register.
1290 * We initially create large virtual GRFs for temporary structures, arrays,
1291 * and matrices, so that the dereference visitor functions can add reg_offsets
1292 * to work their way down to the actual member being accessed. But when it
1293 * comes to optimization, we'd like to treat each register as individual
1294 * storage if possible.
1296 * So far, the only thing that might prevent splitting is a send message from
1300 vec4_visitor::split_virtual_grfs()
1302 int num_vars
= this->alloc
.count
;
1303 int new_virtual_grf
[num_vars
];
1304 bool split_grf
[num_vars
];
1306 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1308 /* Try to split anything > 0 sized. */
1309 for (int i
= 0; i
< num_vars
; i
++) {
1310 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1313 /* Check that the instructions are compatible with the registers we're trying
1316 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1317 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1318 split_grf
[inst
->dst
.reg
] = false;
1320 for (int i
= 0; i
< 3; i
++) {
1321 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1322 split_grf
[inst
->src
[i
].reg
] = false;
1326 /* Allocate new space for split regs. Note that the virtual
1327 * numbers will be contiguous.
1329 for (int i
= 0; i
< num_vars
; i
++) {
1333 new_virtual_grf
[i
] = alloc
.allocate(1);
1334 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1335 unsigned reg
= alloc
.allocate(1);
1336 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1339 this->alloc
.sizes
[i
] = 1;
1342 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1343 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1344 inst
->dst
.reg_offset
!= 0) {
1345 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1346 inst
->dst
.reg_offset
- 1);
1347 inst
->dst
.reg_offset
= 0;
1349 for (int i
= 0; i
< 3; i
++) {
1350 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1351 inst
->src
[i
].reg_offset
!= 0) {
1352 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1353 inst
->src
[i
].reg_offset
- 1);
1354 inst
->src
[i
].reg_offset
= 0;
1358 invalidate_live_intervals();
1362 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1364 dump_instruction(be_inst
, stderr
);
1368 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1370 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1372 if (inst
->predicate
) {
1373 fprintf(file
, "(%cf0.%d%s) ",
1374 inst
->predicate_inverse
? '-' : '+',
1376 pred_ctrl_align16
[inst
->predicate
]);
1379 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1381 fprintf(file
, ".sat");
1382 if (inst
->conditional_mod
) {
1383 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1384 if (!inst
->predicate
&&
1385 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1386 inst
->opcode
!= BRW_OPCODE_IF
&&
1387 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1388 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1393 switch (inst
->dst
.file
) {
1395 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1398 fprintf(file
, "m%d", inst
->dst
.reg
);
1401 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1402 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1404 fprintf(file
, "null");
1406 case BRW_ARF_ADDRESS
:
1407 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1409 case BRW_ARF_ACCUMULATOR
:
1410 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1413 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1414 inst
->dst
.fixed_hw_reg
.subnr
);
1417 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1418 inst
->dst
.fixed_hw_reg
.subnr
);
1422 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1424 if (inst
->dst
.fixed_hw_reg
.subnr
)
1425 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1428 fprintf(file
, "(null)");
1431 fprintf(file
, "???");
1434 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1436 if (inst
->dst
.writemask
& 1)
1438 if (inst
->dst
.writemask
& 2)
1440 if (inst
->dst
.writemask
& 4)
1442 if (inst
->dst
.writemask
& 8)
1445 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1447 if (inst
->src
[0].file
!= BAD_FILE
)
1448 fprintf(file
, ", ");
1450 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1451 if (inst
->src
[i
].negate
)
1453 if (inst
->src
[i
].abs
)
1455 switch (inst
->src
[i
].file
) {
1457 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1460 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1463 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1466 switch (inst
->src
[i
].type
) {
1467 case BRW_REGISTER_TYPE_F
:
1468 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1470 case BRW_REGISTER_TYPE_D
:
1471 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1473 case BRW_REGISTER_TYPE_UD
:
1474 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1476 case BRW_REGISTER_TYPE_VF
:
1477 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1478 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1479 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1480 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1481 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1484 fprintf(file
, "???");
1489 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1491 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1493 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1494 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1496 fprintf(file
, "null");
1498 case BRW_ARF_ADDRESS
:
1499 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1501 case BRW_ARF_ACCUMULATOR
:
1502 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1505 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1506 inst
->src
[i
].fixed_hw_reg
.subnr
);
1509 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1510 inst
->src
[i
].fixed_hw_reg
.subnr
);
1514 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1516 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1517 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1518 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1522 fprintf(file
, "(null)");
1525 fprintf(file
, "???");
1529 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1530 if (inst
->src
[i
].reg_offset
!= 0 &&
1531 inst
->src
[i
].file
== GRF
&&
1532 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1533 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1535 if (inst
->src
[i
].file
!= IMM
) {
1536 static const char *chans
[4] = {"x", "y", "z", "w"};
1538 for (int c
= 0; c
< 4; c
++) {
1539 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1543 if (inst
->src
[i
].abs
)
1546 if (inst
->src
[i
].file
!= IMM
) {
1547 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1550 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1551 fprintf(file
, ", ");
1554 fprintf(file
, "\n");
1558 static inline struct brw_reg
1559 attribute_to_hw_reg(int attr
, bool interleaved
)
1562 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1564 return brw_vec8_grf(attr
, 0);
1569 * Replace each register of type ATTR in this->instructions with a reference
1570 * to a fixed HW register.
1572 * If interleaved is true, then each attribute takes up half a register, with
1573 * register N containing attribute 2*N in its first half and attribute 2*N+1
1574 * in its second half (this corresponds to the payload setup used by geometry
1575 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1576 * false, then each attribute takes up a whole register, with register N
1577 * containing attribute N (this corresponds to the payload setup used by
1578 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1581 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1584 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1585 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1586 if (inst
->dst
.file
== ATTR
) {
1587 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1589 /* All attributes used in the shader need to have been assigned a
1590 * hardware register by the caller
1594 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1595 reg
.type
= inst
->dst
.type
;
1596 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1598 inst
->dst
.file
= HW_REG
;
1599 inst
->dst
.fixed_hw_reg
= reg
;
1602 for (int i
= 0; i
< 3; i
++) {
1603 if (inst
->src
[i
].file
!= ATTR
)
1606 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1608 /* All attributes used in the shader need to have been assigned a
1609 * hardware register by the caller
1613 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1614 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1615 reg
.type
= inst
->src
[i
].type
;
1616 if (inst
->src
[i
].abs
)
1618 if (inst
->src
[i
].negate
)
1621 inst
->src
[i
].file
= HW_REG
;
1622 inst
->src
[i
].fixed_hw_reg
= reg
;
1628 vec4_vs_visitor::setup_attributes(int payload_reg
)
1631 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1632 memset(attribute_map
, 0, sizeof(attribute_map
));
1635 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1636 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1637 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1642 /* VertexID is stored by the VF as the last vertex element, but we
1643 * don't represent it with a flag in inputs_read, so we call it
1646 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1647 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1650 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1652 return payload_reg
+ vs_prog_data
->nr_attributes
;
1656 vec4_visitor::setup_uniforms(int reg
)
1658 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1660 /* The pre-gen6 VS requires that some push constants get loaded no
1661 * matter what, or the GPU would hang.
1663 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1664 assert(this->uniforms
< this->uniform_array_size
);
1666 stage_prog_data
->param
=
1667 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1668 for (unsigned int i
= 0; i
< 4; i
++) {
1669 unsigned int slot
= this->uniforms
* 4 + i
;
1670 static gl_constant_value zero
= { 0.0 };
1671 stage_prog_data
->param
[slot
] = &zero
;
1677 reg
+= ALIGN(uniforms
, 2) / 2;
1680 stage_prog_data
->nr_params
= this->uniforms
* 4;
1682 prog_data
->base
.curb_read_length
=
1683 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1689 vec4_vs_visitor::setup_payload(void)
1693 /* The payload always contains important data in g0, which contains
1694 * the URB handles that are passed on to the URB write at the end
1695 * of the thread. So, we always start push constants at g1.
1699 reg
= setup_uniforms(reg
);
1701 reg
= setup_attributes(reg
);
1703 this->first_non_payload_grf
= reg
;
1707 vec4_visitor::get_timestamp()
1709 assert(devinfo
->gen
>= 7);
1711 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1716 BRW_REGISTER_TYPE_UD
,
1717 BRW_VERTICAL_STRIDE_0
,
1719 BRW_HORIZONTAL_STRIDE_4
,
1723 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1725 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1726 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1727 * even if it's not enabled in the dispatch.
1729 mov
->force_writemask_all
= true;
1731 return src_reg(dst
);
1735 vec4_visitor::emit_shader_time_begin()
1737 current_annotation
= "shader time start";
1738 shader_start_time
= get_timestamp();
1742 vec4_visitor::emit_shader_time_end()
1744 current_annotation
= "shader time end";
1745 src_reg shader_end_time
= get_timestamp();
1748 /* Check that there weren't any timestamp reset events (assuming these
1749 * were the only two timestamp reads that happened).
1751 src_reg reset_end
= shader_end_time
;
1752 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1753 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1754 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1756 emit(IF(BRW_PREDICATE_NORMAL
));
1758 /* Take the current timestamp and get the delta. */
1759 shader_start_time
.negate
= true;
1760 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1761 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1763 /* If there were no instructions between the two timestamp gets, the diff
1764 * is 2 cycles. Remove that overhead, so I can forget about that when
1765 * trying to determine the time taken for single instructions.
1767 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1769 emit_shader_time_write(0, src_reg(diff
));
1770 emit_shader_time_write(1, src_reg(1u));
1771 emit(BRW_OPCODE_ELSE
);
1772 emit_shader_time_write(2, src_reg(1u));
1773 emit(BRW_OPCODE_ENDIF
);
1777 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1780 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1782 dst_reg offset
= dst
;
1786 offset
.type
= BRW_REGISTER_TYPE_UD
;
1787 int index
= shader_time_index
* 3 + shader_time_subindex
;
1788 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1790 time
.type
= BRW_REGISTER_TYPE_UD
;
1791 emit(MOV(time
, src_reg(value
)));
1793 vec4_instruction
*inst
=
1794 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1801 if (shader_time_index
>= 0)
1802 emit_shader_time_begin();
1815 /* Before any optimization, push array accesses out to scratch
1816 * space where we need them to be. This pass may allocate new
1817 * virtual GRFs, so we want to do it early. It also makes sure
1818 * that we have reladdr computations available for CSE, since we'll
1819 * often do repeated subexpressions for those.
1821 move_grf_array_access_to_scratch();
1822 move_uniform_array_access_to_pull_constants();
1824 pack_uniform_registers();
1825 move_push_constants_to_pull_constants();
1826 split_virtual_grfs();
1828 #define OPT(pass, args...) ({ \
1830 bool this_progress = pass(args); \
1832 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1833 char filename[64]; \
1834 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1835 stage_abbrev, nir->info.name, iteration, pass_num); \
1837 backend_shader::dump_instructions(filename); \
1840 progress = progress || this_progress; \
1845 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1847 snprintf(filename
, 64, "%s-%s-00-start",
1848 stage_abbrev
, nir
->info
.name
);
1850 backend_shader::dump_instructions(filename
);
1861 OPT(opt_predicated_break
, this);
1862 OPT(opt_reduce_swizzle
);
1863 OPT(dead_code_eliminate
);
1864 OPT(dead_control_flow_eliminate
, this);
1865 OPT(opt_copy_propagation
);
1866 OPT(opt_cmod_propagation
);
1869 OPT(opt_register_coalesce
);
1870 OPT(eliminate_find_live_channel
);
1875 if (OPT(opt_vector_float
)) {
1877 OPT(opt_copy_propagation
, false);
1878 OPT(opt_copy_propagation
, true);
1879 OPT(dead_code_eliminate
);
1887 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1888 /* Debug of register spilling: Go spill everything. */
1889 const int grf_count
= alloc
.count
;
1890 float spill_costs
[alloc
.count
];
1891 bool no_spill
[alloc
.count
];
1892 evaluate_spill_costs(spill_costs
, no_spill
);
1893 for (int i
= 0; i
< grf_count
; i
++) {
1900 bool allocated_without_spills
= reg_allocate();
1902 if (!allocated_without_spills
) {
1903 compiler
->shader_perf_log(log_data
,
1904 "%s shader triggered register spilling. "
1905 "Try reducing the number of live vec4 values "
1906 "to improve performance.\n",
1909 while (!reg_allocate()) {
1915 opt_schedule_instructions();
1917 opt_set_dependency_control();
1919 if (last_scratch
> 0) {
1920 prog_data
->base
.total_scratch
=
1921 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1927 } /* namespace brw */
1932 * Compile a vertex shader.
1934 * Returns the final assembly and the program's size.
1937 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1939 const struct brw_vs_prog_key
*key
,
1940 struct brw_vs_prog_data
*prog_data
,
1941 const nir_shader
*shader
,
1942 gl_clip_plane
*clip_planes
,
1943 bool use_legacy_snorm_formula
,
1944 int shader_time_index
,
1945 unsigned *final_assembly_size
,
1948 const unsigned *assembly
= NULL
;
1950 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
1952 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
1953 * incoming vertex attribute. So, add an extra slot.
1955 if (shader
->info
.system_values_read
&
1956 (BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
1957 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
1961 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
1962 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
1963 * vec4 mode, the hardware appears to wedge unless we read something.
1965 if (compiler
->scalar_vs
)
1966 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
1968 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
1970 prog_data
->nr_attributes
= nr_attributes
;
1972 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
1973 * (overwriting the original contents), we need to make sure the size is
1974 * the larger of the two.
1976 const unsigned vue_entries
=
1977 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
1979 if (compiler
->devinfo
->gen
== 6)
1980 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
1982 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
1984 if (compiler
->scalar_vs
) {
1985 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1987 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
1988 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
1989 shader
, 8, shader_time_index
);
1990 if (!v
.run_vs(clip_planes
)) {
1992 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1997 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1998 &prog_data
->base
.base
, v
.promoted_constants
,
1999 v
.runtime_check_aads_emit
, "VS");
2000 if (INTEL_DEBUG
& DEBUG_VS
) {
2001 const char *debug_name
=
2002 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2003 shader
->info
.label
? shader
->info
.label
: "unnamed",
2006 g
.enable_debug(debug_name
);
2008 g
.generate_code(v
.cfg
, 8);
2009 assembly
= g
.get_assembly(final_assembly_size
);
2013 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2015 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2016 shader
, clip_planes
, mem_ctx
,
2017 shader_time_index
, use_legacy_snorm_formula
);
2020 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2025 vec4_generator
g(compiler
, log_data
, &prog_data
->base
,
2026 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
2027 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
, shader
);