2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int nr
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(float f
)
79 this->type
= BRW_REGISTER_TYPE_F
;
83 src_reg::src_reg(uint32_t u
)
88 this->type
= BRW_REGISTER_TYPE_UD
;
92 src_reg::src_reg(int32_t i
)
97 this->type
= BRW_REGISTER_TYPE_D
;
101 src_reg::src_reg(uint8_t vf
[4])
106 this->type
= BRW_REGISTER_TYPE_VF
;
107 memcpy(&this->ud
, vf
, sizeof(unsigned));
110 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
115 this->type
= BRW_REGISTER_TYPE_VF
;
116 this->ud
= (vf0
<< 0) | (vf1
<< 8) | (vf2
<< 16) | (vf3
<< 24);
119 src_reg::src_reg(struct brw_reg reg
) :
122 this->file
= (enum register_file
)reg
.file
;
123 this->reg_offset
= 0;
124 this->reladdr
= NULL
;
127 src_reg::src_reg(const dst_reg
®
) :
128 backend_reg(static_cast<struct brw_reg
>(reg
))
130 this->file
= (enum register_file
)reg
.file
;
131 this->reg_offset
= reg
.reg_offset
;
132 this->reladdr
= reg
.reladdr
;
133 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
139 memset(this, 0, sizeof(*this));
140 this->file
= BAD_FILE
;
141 this->writemask
= WRITEMASK_XYZW
;
149 dst_reg::dst_reg(register_file file
, int nr
)
157 dst_reg::dst_reg(register_file file
, int nr
, const glsl_type
*type
,
162 this->file
= (enum register_file
)file
;
164 this->type
= brw_type_for_base_type(type
);
165 this->writemask
= writemask
;
168 dst_reg::dst_reg(register_file file
, int nr
, brw_reg_type type
,
176 this->writemask
= writemask
;
179 dst_reg::dst_reg(struct brw_reg reg
) :
182 this->file
= (enum register_file
)reg
.file
;
183 this->reg_offset
= 0;
184 this->reladdr
= NULL
;
187 dst_reg::dst_reg(const src_reg
®
) :
188 backend_reg(static_cast<struct brw_reg
>(reg
))
190 this->file
= reg
.file
;
191 this->reg_offset
= reg
.reg_offset
;
192 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
193 this->reladdr
= reg
.reladdr
;
197 dst_reg::equals(const dst_reg
&r
) const
199 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
200 reg_offset
== r
.reg_offset
&&
201 (reladdr
== r
.reladdr
||
202 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
206 vec4_instruction::is_send_from_grf()
209 case SHADER_OPCODE_SHADER_TIME_ADD
:
210 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
211 case SHADER_OPCODE_UNTYPED_ATOMIC
:
212 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
213 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
214 case SHADER_OPCODE_TYPED_ATOMIC
:
215 case SHADER_OPCODE_TYPED_SURFACE_READ
:
216 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
224 vec4_instruction::regs_read(unsigned arg
) const
226 if (src
[arg
].file
== BAD_FILE
)
230 case SHADER_OPCODE_SHADER_TIME_ADD
:
231 case SHADER_OPCODE_UNTYPED_ATOMIC
:
232 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
233 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
234 case SHADER_OPCODE_TYPED_ATOMIC
:
235 case SHADER_OPCODE_TYPED_SURFACE_READ
:
236 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
237 return arg
== 0 ? mlen
: 1;
239 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
240 return arg
== 1 ? mlen
: 1;
248 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
250 if (devinfo
->gen
== 6 && is_math())
253 if (is_send_from_grf())
256 if (!backend_instruction::can_do_source_mods())
263 vec4_instruction::can_change_types() const
265 return dst
.type
== src
[0].type
&&
266 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
267 (opcode
== BRW_OPCODE_MOV
||
268 (opcode
== BRW_OPCODE_SEL
&&
269 dst
.type
== src
[1].type
&&
270 predicate
!= BRW_PREDICATE_NONE
&&
271 !src
[1].abs
&& !src
[1].negate
));
275 * Returns how many MRFs an opcode will write over.
277 * Note that this is not the 0 or 1 implied writes in an actual gen
278 * instruction -- the generate_* functions generate additional MOVs
282 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
284 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
287 switch (inst
->opcode
) {
288 case SHADER_OPCODE_RCP
:
289 case SHADER_OPCODE_RSQ
:
290 case SHADER_OPCODE_SQRT
:
291 case SHADER_OPCODE_EXP2
:
292 case SHADER_OPCODE_LOG2
:
293 case SHADER_OPCODE_SIN
:
294 case SHADER_OPCODE_COS
:
296 case SHADER_OPCODE_INT_QUOTIENT
:
297 case SHADER_OPCODE_INT_REMAINDER
:
298 case SHADER_OPCODE_POW
:
300 case VS_OPCODE_URB_WRITE
:
302 case VS_OPCODE_PULL_CONSTANT_LOAD
:
304 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
306 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
308 case GS_OPCODE_URB_WRITE
:
309 case GS_OPCODE_URB_WRITE_ALLOCATE
:
310 case GS_OPCODE_THREAD_END
:
312 case GS_OPCODE_FF_SYNC
:
314 case SHADER_OPCODE_SHADER_TIME_ADD
:
316 case SHADER_OPCODE_TEX
:
317 case SHADER_OPCODE_TXL
:
318 case SHADER_OPCODE_TXD
:
319 case SHADER_OPCODE_TXF
:
320 case SHADER_OPCODE_TXF_CMS
:
321 case SHADER_OPCODE_TXF_CMS_W
:
322 case SHADER_OPCODE_TXF_MCS
:
323 case SHADER_OPCODE_TXS
:
324 case SHADER_OPCODE_TG4
:
325 case SHADER_OPCODE_TG4_OFFSET
:
326 case SHADER_OPCODE_SAMPLEINFO
:
327 case VS_OPCODE_GET_BUFFER_SIZE
:
328 return inst
->header_size
;
330 unreachable("not reached");
335 src_reg::equals(const src_reg
&r
) const
337 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
338 reg_offset
== r
.reg_offset
&&
339 !reladdr
&& !r
.reladdr
);
343 vec4_visitor::opt_vector_float()
345 bool progress
= false;
347 int last_reg
= -1, last_reg_offset
= -1;
348 enum register_file last_reg_file
= BAD_FILE
;
350 int remaining_channels
= 0;
353 vec4_instruction
*imm_inst
[4];
355 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
356 if (last_reg
!= inst
->dst
.nr
||
357 last_reg_offset
!= inst
->dst
.reg_offset
||
358 last_reg_file
!= inst
->dst
.file
) {
359 last_reg
= inst
->dst
.nr
;
360 last_reg_offset
= inst
->dst
.reg_offset
;
361 last_reg_file
= inst
->dst
.file
;
362 remaining_channels
= WRITEMASK_XYZW
;
367 if (inst
->opcode
!= BRW_OPCODE_MOV
||
368 inst
->dst
.writemask
== WRITEMASK_XYZW
||
369 inst
->src
[0].file
!= IMM
)
372 int vf
= brw_float_to_vf(inst
->src
[0].f
);
376 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
378 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
380 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
382 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
385 imm_inst
[inst_count
++] = inst
;
387 remaining_channels
&= ~inst
->dst
.writemask
;
388 if (remaining_channels
== 0) {
389 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
390 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
391 mov
->dst
.writemask
= WRITEMASK_XYZW
;
392 inst
->insert_after(block
, mov
);
395 for (int i
= 0; i
< inst_count
; i
++) {
396 imm_inst
[i
]->remove(block
);
403 invalidate_live_intervals();
408 /* Replaces unused channels of a swizzle with channels that are used.
410 * For instance, this pass transforms
412 * mov vgrf4.yz, vgrf5.wxzy
416 * mov vgrf4.yz, vgrf5.xxzx
418 * This eliminates false uses of some channels, letting dead code elimination
419 * remove the instructions that wrote them.
422 vec4_visitor::opt_reduce_swizzle()
424 bool progress
= false;
426 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
427 if (inst
->dst
.file
== BAD_FILE
||
428 inst
->dst
.file
== ARF
||
429 inst
->dst
.file
== FIXED_GRF
||
430 inst
->is_send_from_grf())
435 /* Determine which channels of the sources are read. */
436 switch (inst
->opcode
) {
437 case VEC4_OPCODE_PACK_BYTES
:
439 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
440 * but all four of src1.
442 swizzle
= brw_swizzle_for_size(4);
445 swizzle
= brw_swizzle_for_size(3);
448 swizzle
= brw_swizzle_for_size(2);
451 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
455 /* Update sources' swizzles. */
456 for (int i
= 0; i
< 3; i
++) {
457 if (inst
->src
[i
].file
!= VGRF
&&
458 inst
->src
[i
].file
!= ATTR
&&
459 inst
->src
[i
].file
!= UNIFORM
)
462 const unsigned new_swizzle
=
463 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
464 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
465 inst
->src
[i
].swizzle
= new_swizzle
;
472 invalidate_live_intervals();
478 vec4_visitor::split_uniform_registers()
480 /* Prior to this, uniforms have been in an array sized according to
481 * the number of vector uniforms present, sparsely filled (so an
482 * aggregate results in reg indices being skipped over). Now we're
483 * going to cut those aggregates up so each .nr index is one
484 * vector. The goal is to make elimination of unused uniform
485 * components easier later.
487 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
488 for (int i
= 0 ; i
< 3; i
++) {
489 if (inst
->src
[i
].file
!= UNIFORM
)
492 assert(!inst
->src
[i
].reladdr
);
494 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
495 inst
->src
[i
].reg_offset
= 0;
499 /* Update that everything is now vector-sized. */
500 for (int i
= 0; i
< this->uniforms
; i
++) {
501 this->uniform_size
[i
] = 1;
506 vec4_visitor::pack_uniform_registers()
508 uint8_t chans_used
[this->uniforms
];
509 int new_loc
[this->uniforms
];
510 int new_chan
[this->uniforms
];
512 memset(chans_used
, 0, sizeof(chans_used
));
513 memset(new_loc
, 0, sizeof(new_loc
));
514 memset(new_chan
, 0, sizeof(new_chan
));
516 /* Find which uniform vectors are actually used by the program. We
517 * expect unused vector elements when we've moved array access out
518 * to pull constants, and from some GLSL code generators like wine.
520 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
522 switch (inst
->opcode
) {
523 case VEC4_OPCODE_PACK_BYTES
:
535 readmask
= inst
->dst
.writemask
;
539 for (int i
= 0 ; i
< 3; i
++) {
540 if (inst
->src
[i
].file
!= UNIFORM
)
543 int reg
= inst
->src
[i
].nr
;
544 for (int c
= 0; c
< 4; c
++) {
545 if (!(readmask
& (1 << c
)))
548 chans_used
[reg
] = MAX2(chans_used
[reg
],
549 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
554 int new_uniform_count
= 0;
556 /* Now, figure out a packing of the live uniform vectors into our
559 for (int src
= 0; src
< uniforms
; src
++) {
560 assert(src
< uniform_array_size
);
561 int size
= chans_used
[src
];
567 /* Find the lowest place we can slot this uniform in. */
568 for (dst
= 0; dst
< src
; dst
++) {
569 if (chans_used
[dst
] + size
<= 4)
578 new_chan
[src
] = chans_used
[dst
];
580 /* Move the references to the data */
581 for (int j
= 0; j
< size
; j
++) {
582 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
583 stage_prog_data
->param
[src
* 4 + j
];
586 chans_used
[dst
] += size
;
590 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
593 this->uniforms
= new_uniform_count
;
595 /* Now, update the instructions for our repacked uniforms. */
596 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
597 for (int i
= 0 ; i
< 3; i
++) {
598 int src
= inst
->src
[i
].nr
;
600 if (inst
->src
[i
].file
!= UNIFORM
)
603 inst
->src
[i
].nr
= new_loc
[src
];
604 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
605 new_chan
[src
], new_chan
[src
]);
611 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
613 * While GLSL IR also performs this optimization, we end up with it in
614 * our instruction stream for a couple of reasons. One is that we
615 * sometimes generate silly instructions, for example in array access
616 * where we'll generate "ADD offset, index, base" even if base is 0.
617 * The other is that GLSL IR's constant propagation doesn't track the
618 * components of aggregates, so some VS patterns (initialize matrix to
619 * 0, accumulate in vertex blending factors) end up breaking down to
620 * instructions involving 0.
623 vec4_visitor::opt_algebraic()
625 bool progress
= false;
627 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
628 switch (inst
->opcode
) {
630 if (inst
->src
[0].file
!= IMM
)
633 if (inst
->saturate
) {
634 if (inst
->dst
.type
!= inst
->src
[0].type
)
635 assert(!"unimplemented: saturate mixed types");
637 if (brw_saturate_immediate(inst
->dst
.type
, &inst
->src
[0])) {
638 inst
->saturate
= false;
644 case VEC4_OPCODE_UNPACK_UNIFORM
:
645 if (inst
->src
[0].file
!= UNIFORM
) {
646 inst
->opcode
= BRW_OPCODE_MOV
;
652 if (inst
->src
[1].is_zero()) {
653 inst
->opcode
= BRW_OPCODE_MOV
;
654 inst
->src
[1] = src_reg();
660 if (inst
->src
[1].is_zero()) {
661 inst
->opcode
= BRW_OPCODE_MOV
;
662 switch (inst
->src
[0].type
) {
663 case BRW_REGISTER_TYPE_F
:
664 inst
->src
[0] = src_reg(0.0f
);
666 case BRW_REGISTER_TYPE_D
:
667 inst
->src
[0] = src_reg(0);
669 case BRW_REGISTER_TYPE_UD
:
670 inst
->src
[0] = src_reg(0u);
673 unreachable("not reached");
675 inst
->src
[1] = src_reg();
677 } else if (inst
->src
[1].is_one()) {
678 inst
->opcode
= BRW_OPCODE_MOV
;
679 inst
->src
[1] = src_reg();
681 } else if (inst
->src
[1].is_negative_one()) {
682 inst
->opcode
= BRW_OPCODE_MOV
;
683 inst
->src
[0].negate
= !inst
->src
[0].negate
;
684 inst
->src
[1] = src_reg();
689 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
691 inst
->src
[0].negate
&&
692 inst
->src
[1].is_zero()) {
693 inst
->src
[0].abs
= false;
694 inst
->src
[0].negate
= false;
695 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
700 case SHADER_OPCODE_RCP
: {
701 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
702 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
703 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
704 inst
->opcode
= SHADER_OPCODE_RSQ
;
705 inst
->src
[0] = prev
->src
[0];
711 case SHADER_OPCODE_BROADCAST
:
712 if (is_uniform(inst
->src
[0]) ||
713 inst
->src
[1].is_zero()) {
714 inst
->opcode
= BRW_OPCODE_MOV
;
715 inst
->src
[1] = src_reg();
716 inst
->force_writemask_all
= true;
727 invalidate_live_intervals();
733 * Only a limited number of hardware registers may be used for push
734 * constants, so this turns access to the overflowed constants into
738 vec4_visitor::move_push_constants_to_pull_constants()
740 int pull_constant_loc
[this->uniforms
];
742 /* Only allow 32 registers (256 uniform components) as push constants,
743 * which is the limit on gen6.
745 * If changing this value, note the limitation about total_regs in
748 int max_uniform_components
= 32 * 8;
749 if (this->uniforms
* 4 <= max_uniform_components
)
752 /* Make some sort of choice as to which uniforms get sent to pull
753 * constants. We could potentially do something clever here like
754 * look for the most infrequently used uniform vec4s, but leave
757 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
758 pull_constant_loc
[i
/ 4] = -1;
760 if (i
>= max_uniform_components
) {
761 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
763 /* Try to find an existing copy of this uniform in the pull
764 * constants if it was part of an array access already.
766 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
769 for (matches
= 0; matches
< 4; matches
++) {
770 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
775 pull_constant_loc
[i
/ 4] = j
/ 4;
780 if (pull_constant_loc
[i
/ 4] == -1) {
781 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
782 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
784 for (int j
= 0; j
< 4; j
++) {
785 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
792 /* Now actually rewrite usage of the things we've moved to pull
795 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
796 for (int i
= 0 ; i
< 3; i
++) {
797 if (inst
->src
[i
].file
!= UNIFORM
||
798 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
801 int uniform
= inst
->src
[i
].nr
;
803 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
805 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
806 pull_constant_loc
[uniform
]);
808 inst
->src
[i
].file
= temp
.file
;
809 inst
->src
[i
].nr
= temp
.nr
;
810 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
811 inst
->src
[i
].reladdr
= NULL
;
815 /* Repack push constants to remove the now-unused ones. */
816 pack_uniform_registers();
819 /* Conditions for which we want to avoid setting the dependency control bits */
821 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
823 #define IS_DWORD(reg) \
824 (reg.type == BRW_REGISTER_TYPE_UD || \
825 reg.type == BRW_REGISTER_TYPE_D)
827 /* "When source or destination datatype is 64b or operation is integer DWord
828 * multiply, DepCtrl must not be used."
829 * May apply to future SoCs as well.
831 if (devinfo
->is_cherryview
) {
832 if (inst
->opcode
== BRW_OPCODE_MUL
&&
833 IS_DWORD(inst
->src
[0]) &&
834 IS_DWORD(inst
->src
[1]))
839 if (devinfo
->gen
>= 8) {
840 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
846 * In the presence of send messages, totally interrupt dependency
847 * control. They're long enough that the chance of dependency
848 * control around them just doesn't matter.
851 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
852 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
853 * completes the scoreboard clear must have a non-zero execution mask. This
854 * means, if any kind of predication can change the execution mask or channel
855 * enable of the last instruction, the optimization must be avoided. This is
856 * to avoid instructions being shot down the pipeline when no writes are
860 * Dependency control does not work well over math instructions.
861 * NB: Discovered empirically
863 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
867 * Sets the dependency control fields on instructions after register
868 * allocation and before the generator is run.
870 * When you have a sequence of instructions like:
872 * DP4 temp.x vertex uniform[0]
873 * DP4 temp.y vertex uniform[0]
874 * DP4 temp.z vertex uniform[0]
875 * DP4 temp.w vertex uniform[0]
877 * The hardware doesn't know that it can actually run the later instructions
878 * while the previous ones are in flight, producing stalls. However, we have
879 * manual fields we can set in the instructions that let it do so.
882 vec4_visitor::opt_set_dependency_control()
884 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
885 uint8_t grf_channels_written
[BRW_MAX_GRF
];
886 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
887 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
889 assert(prog_data
->total_grf
||
890 !"Must be called after register allocation");
892 foreach_block (block
, cfg
) {
893 memset(last_grf_write
, 0, sizeof(last_grf_write
));
894 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
896 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
897 /* If we read from a register that we were doing dependency control
898 * on, don't do dependency control across the read.
900 for (int i
= 0; i
< 3; i
++) {
901 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
902 if (inst
->src
[i
].file
== VGRF
) {
903 last_grf_write
[reg
] = NULL
;
904 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
905 memset(last_grf_write
, 0, sizeof(last_grf_write
));
908 assert(inst
->src
[i
].file
!= MRF
);
911 if (is_dep_ctrl_unsafe(inst
)) {
912 memset(last_grf_write
, 0, sizeof(last_grf_write
));
913 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
917 /* Now, see if we can do dependency control for this instruction
918 * against a previous one writing to its destination.
920 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
921 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
922 if (last_grf_write
[reg
] &&
923 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
924 last_grf_write
[reg
]->no_dd_clear
= true;
925 inst
->no_dd_check
= true;
927 grf_channels_written
[reg
] = 0;
930 last_grf_write
[reg
] = inst
;
931 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
932 } else if (inst
->dst
.file
== MRF
) {
933 if (last_mrf_write
[reg
] &&
934 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
935 last_mrf_write
[reg
]->no_dd_clear
= true;
936 inst
->no_dd_check
= true;
938 mrf_channels_written
[reg
] = 0;
941 last_mrf_write
[reg
] = inst
;
942 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
949 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
954 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
955 * or writemasking are not allowed.
957 if (devinfo
->gen
== 6 && is_math() &&
958 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
961 /* If this instruction sets anything not referenced by swizzle, then we'd
962 * totally break it when we reswizzle.
964 if (dst
.writemask
& ~swizzle_mask
)
970 for (int i
= 0; i
< 3; i
++) {
971 if (src
[i
].is_accumulator())
979 * For any channels in the swizzle's source that were populated by this
980 * instruction, rewrite the instruction to put the appropriate result directly
983 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
986 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
988 /* Destination write mask doesn't correspond to source swizzle for the dot
989 * product and pack_bytes instructions.
991 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
992 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
993 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
994 for (int i
= 0; i
< 3; i
++) {
995 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
998 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1002 /* Apply the specified swizzle and writemask to the original mask of
1003 * written components.
1005 dst
.writemask
= dst_writemask
&
1006 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1010 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1011 * just written and then MOVed into another reg and making the original write
1012 * of the GRF write directly to the final destination instead.
1015 vec4_visitor::opt_register_coalesce()
1017 bool progress
= false;
1020 calculate_live_intervals();
1022 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1026 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1027 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1029 inst
->src
[0].file
!= VGRF
||
1030 inst
->dst
.type
!= inst
->src
[0].type
||
1031 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1034 /* Remove no-op MOVs */
1035 if (inst
->dst
.file
== inst
->src
[0].file
&&
1036 inst
->dst
.nr
== inst
->src
[0].nr
&&
1037 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1038 bool is_nop_mov
= true;
1040 for (unsigned c
= 0; c
< 4; c
++) {
1041 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1044 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1051 inst
->remove(block
);
1056 bool to_mrf
= (inst
->dst
.file
== MRF
);
1058 /* Can't coalesce this GRF if someone else was going to
1061 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1064 /* We need to check interference with the final destination between this
1065 * instruction and the earliest instruction involved in writing the GRF
1066 * we're eliminating. To do that, keep track of which of our source
1067 * channels we've seen initialized.
1069 const unsigned chans_needed
=
1070 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1071 inst
->dst
.writemask
);
1072 unsigned chans_remaining
= chans_needed
;
1074 /* Now walk up the instruction stream trying to see if we can rewrite
1075 * everything writing to the temporary to write into the destination
1078 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1079 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1081 _scan_inst
= scan_inst
;
1083 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1084 /* Found something writing to the reg we want to coalesce away. */
1086 /* SEND instructions can't have MRF as a destination. */
1087 if (scan_inst
->mlen
)
1090 if (devinfo
->gen
== 6) {
1091 /* gen6 math instructions must have the destination be
1092 * VGRF, so no compute-to-MRF for them.
1094 if (scan_inst
->is_math()) {
1100 /* This doesn't handle saturation on the instruction we
1101 * want to coalesce away if the register types do not match.
1102 * But if scan_inst is a non type-converting 'mov', we can fix
1105 if (inst
->saturate
&&
1106 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1107 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1108 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1111 /* If we can't handle the swizzle, bail. */
1112 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1113 inst
->src
[0].swizzle
,
1118 /* This doesn't handle coalescing of multiple registers. */
1119 if (scan_inst
->regs_written
> 1)
1122 /* Mark which channels we found unconditional writes for. */
1123 if (!scan_inst
->predicate
)
1124 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1126 if (chans_remaining
== 0)
1130 /* You can't read from an MRF, so if someone else reads our MRF's
1131 * source GRF that we wanted to rewrite, that stops us. If it's a
1132 * GRF we're trying to coalesce to, we don't actually handle
1133 * rewriting sources so bail in that case as well.
1135 bool interfered
= false;
1136 for (int i
= 0; i
< 3; i
++) {
1137 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1138 scan_inst
->regs_read(i
)))
1144 /* If somebody else writes the same channels of our destination here,
1145 * we can't coalesce before that.
1147 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1148 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1152 /* Check for reads of the register we're trying to coalesce into. We
1153 * can't go rewriting instructions above that to put some other value
1154 * in the register instead.
1156 if (to_mrf
&& scan_inst
->mlen
> 0) {
1157 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1158 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1162 for (int i
= 0; i
< 3; i
++) {
1163 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1164 scan_inst
->regs_read(i
)))
1172 if (chans_remaining
== 0) {
1173 /* If we've made it here, we have an MOV we want to coalesce out, and
1174 * a scan_inst pointing to the earliest instruction involved in
1175 * computing the value. Now go rewrite the instruction stream
1178 vec4_instruction
*scan_inst
= _scan_inst
;
1179 while (scan_inst
!= inst
) {
1180 if (scan_inst
->dst
.file
== VGRF
&&
1181 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1182 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1183 scan_inst
->reswizzle(inst
->dst
.writemask
,
1184 inst
->src
[0].swizzle
);
1185 scan_inst
->dst
.file
= inst
->dst
.file
;
1186 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1187 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1188 if (inst
->saturate
&&
1189 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1190 /* If we have reached this point, scan_inst is a non
1191 * type-converting 'mov' and we can modify its register types
1192 * to match the ones in inst. Otherwise, we could have an
1193 * incorrect saturation result.
1195 scan_inst
->dst
.type
= inst
->dst
.type
;
1196 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1198 scan_inst
->saturate
|= inst
->saturate
;
1200 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1202 inst
->remove(block
);
1208 invalidate_live_intervals();
1214 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1215 * flow. We could probably do better here with some form of divergence
1219 vec4_visitor::eliminate_find_live_channel()
1221 bool progress
= false;
1224 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1225 switch (inst
->opcode
) {
1231 case BRW_OPCODE_ENDIF
:
1232 case BRW_OPCODE_WHILE
:
1236 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1238 inst
->opcode
= BRW_OPCODE_MOV
;
1239 inst
->src
[0] = src_reg(0);
1240 inst
->force_writemask_all
= true;
1254 * Splits virtual GRFs requesting more than one contiguous physical register.
1256 * We initially create large virtual GRFs for temporary structures, arrays,
1257 * and matrices, so that the dereference visitor functions can add reg_offsets
1258 * to work their way down to the actual member being accessed. But when it
1259 * comes to optimization, we'd like to treat each register as individual
1260 * storage if possible.
1262 * So far, the only thing that might prevent splitting is a send message from
1266 vec4_visitor::split_virtual_grfs()
1268 int num_vars
= this->alloc
.count
;
1269 int new_virtual_grf
[num_vars
];
1270 bool split_grf
[num_vars
];
1272 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1274 /* Try to split anything > 0 sized. */
1275 for (int i
= 0; i
< num_vars
; i
++) {
1276 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1279 /* Check that the instructions are compatible with the registers we're trying
1282 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1283 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1284 split_grf
[inst
->dst
.nr
] = false;
1286 for (int i
= 0; i
< 3; i
++) {
1287 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1288 split_grf
[inst
->src
[i
].nr
] = false;
1292 /* Allocate new space for split regs. Note that the virtual
1293 * numbers will be contiguous.
1295 for (int i
= 0; i
< num_vars
; i
++) {
1299 new_virtual_grf
[i
] = alloc
.allocate(1);
1300 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1301 unsigned reg
= alloc
.allocate(1);
1302 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1305 this->alloc
.sizes
[i
] = 1;
1308 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1309 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1310 inst
->dst
.reg_offset
!= 0) {
1311 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1312 inst
->dst
.reg_offset
- 1);
1313 inst
->dst
.reg_offset
= 0;
1315 for (int i
= 0; i
< 3; i
++) {
1316 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1317 inst
->src
[i
].reg_offset
!= 0) {
1318 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1319 inst
->src
[i
].reg_offset
- 1);
1320 inst
->src
[i
].reg_offset
= 0;
1324 invalidate_live_intervals();
1328 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1330 dump_instruction(be_inst
, stderr
);
1334 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1336 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1338 if (inst
->predicate
) {
1339 fprintf(file
, "(%cf0.%d%s) ",
1340 inst
->predicate_inverse
? '-' : '+',
1342 pred_ctrl_align16
[inst
->predicate
]);
1345 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1347 fprintf(file
, ".sat");
1348 if (inst
->conditional_mod
) {
1349 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1350 if (!inst
->predicate
&&
1351 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1352 inst
->opcode
!= BRW_OPCODE_IF
&&
1353 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1354 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1359 switch (inst
->dst
.file
) {
1361 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1364 fprintf(file
, "g%d", inst
->dst
.nr
);
1367 fprintf(file
, "m%d", inst
->dst
.nr
);
1370 switch (inst
->dst
.nr
) {
1372 fprintf(file
, "null");
1374 case BRW_ARF_ADDRESS
:
1375 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1377 case BRW_ARF_ACCUMULATOR
:
1378 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1381 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1384 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1387 if (inst
->dst
.subnr
)
1388 fprintf(file
, "+%d", inst
->dst
.subnr
);
1391 fprintf(file
, "(null)");
1396 unreachable("not reached");
1398 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1400 if (inst
->dst
.writemask
& 1)
1402 if (inst
->dst
.writemask
& 2)
1404 if (inst
->dst
.writemask
& 4)
1406 if (inst
->dst
.writemask
& 8)
1409 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1411 if (inst
->src
[0].file
!= BAD_FILE
)
1412 fprintf(file
, ", ");
1414 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1415 if (inst
->src
[i
].negate
)
1417 if (inst
->src
[i
].abs
)
1419 switch (inst
->src
[i
].file
) {
1421 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1424 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1427 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1430 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1433 switch (inst
->src
[i
].type
) {
1434 case BRW_REGISTER_TYPE_F
:
1435 fprintf(file
, "%fF", inst
->src
[i
].f
);
1437 case BRW_REGISTER_TYPE_D
:
1438 fprintf(file
, "%dD", inst
->src
[i
].d
);
1440 case BRW_REGISTER_TYPE_UD
:
1441 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1443 case BRW_REGISTER_TYPE_VF
:
1444 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1445 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1446 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1447 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1448 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1451 fprintf(file
, "???");
1456 switch (inst
->src
[i
].nr
) {
1458 fprintf(file
, "null");
1460 case BRW_ARF_ADDRESS
:
1461 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1463 case BRW_ARF_ACCUMULATOR
:
1464 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1467 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1470 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1473 if (inst
->src
[i
].subnr
)
1474 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1477 fprintf(file
, "(null)");
1480 unreachable("not reached");
1483 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1484 if (inst
->src
[i
].reg_offset
!= 0 &&
1485 inst
->src
[i
].file
== VGRF
&&
1486 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1487 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1489 if (inst
->src
[i
].file
!= IMM
) {
1490 static const char *chans
[4] = {"x", "y", "z", "w"};
1492 for (int c
= 0; c
< 4; c
++) {
1493 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1497 if (inst
->src
[i
].abs
)
1500 if (inst
->src
[i
].file
!= IMM
) {
1501 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1504 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1505 fprintf(file
, ", ");
1508 if (inst
->force_writemask_all
)
1509 fprintf(file
, " NoMask");
1511 fprintf(file
, "\n");
1515 static inline struct brw_reg
1516 attribute_to_hw_reg(int attr
, bool interleaved
)
1519 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1521 return brw_vec8_grf(attr
, 0);
1526 * Replace each register of type ATTR in this->instructions with a reference
1527 * to a fixed HW register.
1529 * If interleaved is true, then each attribute takes up half a register, with
1530 * register N containing attribute 2*N in its first half and attribute 2*N+1
1531 * in its second half (this corresponds to the payload setup used by geometry
1532 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1533 * false, then each attribute takes up a whole register, with register N
1534 * containing attribute N (this corresponds to the payload setup used by
1535 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1538 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1541 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1542 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1543 if (inst
->dst
.file
== ATTR
) {
1544 int grf
= attribute_map
[inst
->dst
.nr
+ inst
->dst
.reg_offset
];
1546 /* All attributes used in the shader need to have been assigned a
1547 * hardware register by the caller
1551 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1552 reg
.type
= inst
->dst
.type
;
1553 reg
.writemask
= inst
->dst
.writemask
;
1558 for (int i
= 0; i
< 3; i
++) {
1559 if (inst
->src
[i
].file
!= ATTR
)
1562 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1564 /* All attributes used in the shader need to have been assigned a
1565 * hardware register by the caller
1569 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1570 reg
.swizzle
= inst
->src
[i
].swizzle
;
1571 reg
.type
= inst
->src
[i
].type
;
1572 if (inst
->src
[i
].abs
)
1574 if (inst
->src
[i
].negate
)
1583 vec4_vs_visitor::setup_attributes(int payload_reg
)
1586 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1587 memset(attribute_map
, 0, sizeof(attribute_map
));
1590 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1591 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1592 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1597 /* VertexID is stored by the VF as the last vertex element, but we
1598 * don't represent it with a flag in inputs_read, so we call it
1601 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1602 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1605 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1607 return payload_reg
+ vs_prog_data
->nr_attributes
;
1611 vec4_visitor::setup_uniforms(int reg
)
1613 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1615 /* The pre-gen6 VS requires that some push constants get loaded no
1616 * matter what, or the GPU would hang.
1618 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1619 assert(this->uniforms
< this->uniform_array_size
);
1621 stage_prog_data
->param
=
1622 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1623 for (unsigned int i
= 0; i
< 4; i
++) {
1624 unsigned int slot
= this->uniforms
* 4 + i
;
1625 static gl_constant_value zero
= { 0.0 };
1626 stage_prog_data
->param
[slot
] = &zero
;
1632 reg
+= ALIGN(uniforms
, 2) / 2;
1635 stage_prog_data
->nr_params
= this->uniforms
* 4;
1637 prog_data
->base
.curb_read_length
=
1638 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1644 vec4_vs_visitor::setup_payload(void)
1648 /* The payload always contains important data in g0, which contains
1649 * the URB handles that are passed on to the URB write at the end
1650 * of the thread. So, we always start push constants at g1.
1654 reg
= setup_uniforms(reg
);
1656 reg
= setup_attributes(reg
);
1658 this->first_non_payload_grf
= reg
;
1662 vec4_visitor::get_timestamp()
1664 assert(devinfo
->gen
>= 7);
1666 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1671 BRW_REGISTER_TYPE_UD
,
1672 BRW_VERTICAL_STRIDE_0
,
1674 BRW_HORIZONTAL_STRIDE_4
,
1678 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1680 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1681 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1682 * even if it's not enabled in the dispatch.
1684 mov
->force_writemask_all
= true;
1686 return src_reg(dst
);
1690 vec4_visitor::emit_shader_time_begin()
1692 current_annotation
= "shader time start";
1693 shader_start_time
= get_timestamp();
1697 vec4_visitor::emit_shader_time_end()
1699 current_annotation
= "shader time end";
1700 src_reg shader_end_time
= get_timestamp();
1703 /* Check that there weren't any timestamp reset events (assuming these
1704 * were the only two timestamp reads that happened).
1706 src_reg reset_end
= shader_end_time
;
1707 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1708 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1709 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1711 emit(IF(BRW_PREDICATE_NORMAL
));
1713 /* Take the current timestamp and get the delta. */
1714 shader_start_time
.negate
= true;
1715 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1716 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1718 /* If there were no instructions between the two timestamp gets, the diff
1719 * is 2 cycles. Remove that overhead, so I can forget about that when
1720 * trying to determine the time taken for single instructions.
1722 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1724 emit_shader_time_write(0, src_reg(diff
));
1725 emit_shader_time_write(1, src_reg(1u));
1726 emit(BRW_OPCODE_ELSE
);
1727 emit_shader_time_write(2, src_reg(1u));
1728 emit(BRW_OPCODE_ENDIF
);
1732 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1735 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1737 dst_reg offset
= dst
;
1741 offset
.type
= BRW_REGISTER_TYPE_UD
;
1742 int index
= shader_time_index
* 3 + shader_time_subindex
;
1743 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1745 time
.type
= BRW_REGISTER_TYPE_UD
;
1746 emit(MOV(time
, value
));
1748 vec4_instruction
*inst
=
1749 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1754 vec4_visitor::convert_to_hw_regs()
1756 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1757 for (int i
= 0; i
< 3; i
++) {
1758 struct src_reg
&src
= inst
->src
[i
];
1762 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1763 reg
.type
= src
.type
;
1764 reg
.swizzle
= src
.swizzle
;
1766 reg
.negate
= src
.negate
;
1770 reg
= brw_imm_reg(src
.type
);
1775 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1776 (src
.nr
+ src
.reg_offset
) / 2,
1777 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1779 reg
.type
= src
.type
;
1780 reg
.swizzle
= src
.swizzle
;
1782 reg
.negate
= src
.negate
;
1784 /* This should have been moved to pull constants. */
1785 assert(!src
.reladdr
);
1793 /* Probably unused. */
1794 reg
= brw_null_reg();
1799 unreachable("not reached");
1804 dst_reg
&dst
= inst
->dst
;
1807 switch (inst
->dst
.file
) {
1809 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1810 reg
.type
= dst
.type
;
1811 reg
.writemask
= dst
.writemask
;
1815 assert(((dst
.nr
+ dst
.reg_offset
) & ~(1 << 7)) < BRW_MAX_MRF(devinfo
->gen
));
1816 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1817 reg
.type
= dst
.type
;
1818 reg
.writemask
= dst
.writemask
;
1827 reg
= brw_null_reg();
1833 unreachable("not reached");
1843 if (shader_time_index
>= 0)
1844 emit_shader_time_begin();
1857 /* Before any optimization, push array accesses out to scratch
1858 * space where we need them to be. This pass may allocate new
1859 * virtual GRFs, so we want to do it early. It also makes sure
1860 * that we have reladdr computations available for CSE, since we'll
1861 * often do repeated subexpressions for those.
1863 move_grf_array_access_to_scratch();
1864 move_uniform_array_access_to_pull_constants();
1866 pack_uniform_registers();
1867 move_push_constants_to_pull_constants();
1868 split_virtual_grfs();
1870 #define OPT(pass, args...) ({ \
1872 bool this_progress = pass(args); \
1874 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1875 char filename[64]; \
1876 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1877 stage_abbrev, nir->info.name, iteration, pass_num); \
1879 backend_shader::dump_instructions(filename); \
1882 progress = progress || this_progress; \
1887 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1889 snprintf(filename
, 64, "%s-%s-00-start",
1890 stage_abbrev
, nir
->info
.name
);
1892 backend_shader::dump_instructions(filename
);
1903 OPT(opt_predicated_break
, this);
1904 OPT(opt_reduce_swizzle
);
1905 OPT(dead_code_eliminate
);
1906 OPT(dead_control_flow_eliminate
, this);
1907 OPT(opt_copy_propagation
);
1908 OPT(opt_cmod_propagation
);
1911 OPT(opt_register_coalesce
);
1912 OPT(eliminate_find_live_channel
);
1917 if (OPT(opt_vector_float
)) {
1919 OPT(opt_copy_propagation
, false);
1920 OPT(opt_copy_propagation
, true);
1921 OPT(dead_code_eliminate
);
1929 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1930 /* Debug of register spilling: Go spill everything. */
1931 const int grf_count
= alloc
.count
;
1932 float spill_costs
[alloc
.count
];
1933 bool no_spill
[alloc
.count
];
1934 evaluate_spill_costs(spill_costs
, no_spill
);
1935 for (int i
= 0; i
< grf_count
; i
++) {
1942 bool allocated_without_spills
= reg_allocate();
1944 if (!allocated_without_spills
) {
1945 compiler
->shader_perf_log(log_data
,
1946 "%s shader triggered register spilling. "
1947 "Try reducing the number of live vec4 values "
1948 "to improve performance.\n",
1951 while (!reg_allocate()) {
1957 opt_schedule_instructions();
1959 opt_set_dependency_control();
1961 convert_to_hw_regs();
1963 if (last_scratch
> 0) {
1964 prog_data
->base
.total_scratch
=
1965 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1971 } /* namespace brw */
1976 * Compile a vertex shader.
1978 * Returns the final assembly and the program's size.
1981 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1983 const struct brw_vs_prog_key
*key
,
1984 struct brw_vs_prog_data
*prog_data
,
1985 const nir_shader
*shader
,
1986 gl_clip_plane
*clip_planes
,
1987 bool use_legacy_snorm_formula
,
1988 int shader_time_index
,
1989 unsigned *final_assembly_size
,
1992 const unsigned *assembly
= NULL
;
1994 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
1996 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
1997 * incoming vertex attribute. So, add an extra slot.
1999 if (shader
->info
.system_values_read
&
2000 (BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2001 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2005 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2006 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2007 * vec4 mode, the hardware appears to wedge unless we read something.
2009 if (compiler
->scalar_vs
)
2010 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
2012 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
2014 prog_data
->nr_attributes
= nr_attributes
;
2016 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2017 * (overwriting the original contents), we need to make sure the size is
2018 * the larger of the two.
2020 const unsigned vue_entries
=
2021 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2023 if (compiler
->devinfo
->gen
== 6)
2024 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2026 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2028 if (compiler
->scalar_vs
) {
2029 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2031 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2032 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2033 shader
, 8, shader_time_index
);
2034 if (!v
.run_vs(clip_planes
)) {
2036 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2041 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2042 &prog_data
->base
.base
, v
.promoted_constants
,
2043 v
.runtime_check_aads_emit
, "VS");
2044 if (INTEL_DEBUG
& DEBUG_VS
) {
2045 const char *debug_name
=
2046 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2047 shader
->info
.label
? shader
->info
.label
: "unnamed",
2050 g
.enable_debug(debug_name
);
2052 g
.generate_code(v
.cfg
, 8);
2053 assembly
= g
.get_assembly(final_assembly_size
);
2057 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2059 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2060 shader
, clip_planes
, mem_ctx
,
2061 shader_time_index
, use_legacy_snorm_formula
);
2064 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2069 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2070 shader
, &prog_data
->base
, v
.cfg
,
2071 final_assembly_size
);