2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
66 /** Generic unset register constructor. */
72 src_reg::src_reg(float f
)
77 this->type
= BRW_REGISTER_TYPE_F
;
78 this->fixed_hw_reg
.dw1
.f
= f
;
81 src_reg::src_reg(uint32_t u
)
86 this->type
= BRW_REGISTER_TYPE_UD
;
87 this->fixed_hw_reg
.dw1
.ud
= u
;
90 src_reg::src_reg(int32_t i
)
95 this->type
= BRW_REGISTER_TYPE_D
;
96 this->fixed_hw_reg
.dw1
.d
= i
;
99 src_reg::src_reg(uint8_t vf
[4])
104 this->type
= BRW_REGISTER_TYPE_VF
;
105 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
108 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
113 this->type
= BRW_REGISTER_TYPE_VF
;
114 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
120 src_reg::src_reg(struct brw_reg reg
)
125 this->fixed_hw_reg
= reg
;
126 this->type
= reg
.type
;
129 src_reg::src_reg(const dst_reg
®
)
133 this->file
= reg
.file
;
135 this->reg_offset
= reg
.reg_offset
;
136 this->type
= reg
.type
;
137 this->reladdr
= reg
.reladdr
;
138 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
145 memset(this, 0, sizeof(*this));
146 this->file
= BAD_FILE
;
147 this->writemask
= WRITEMASK_XYZW
;
155 dst_reg::dst_reg(register_file file
, int reg
)
163 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
170 this->type
= brw_type_for_base_type(type
);
171 this->writemask
= writemask
;
174 dst_reg::dst_reg(struct brw_reg reg
)
179 this->fixed_hw_reg
= reg
;
180 this->type
= reg
.type
;
183 dst_reg::dst_reg(const src_reg
®
)
187 this->file
= reg
.file
;
189 this->reg_offset
= reg
.reg_offset
;
190 this->type
= reg
.type
;
191 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
192 this->reladdr
= reg
.reladdr
;
193 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
197 dst_reg::equals(const dst_reg
&r
) const
199 return (file
== r
.file
&&
201 reg_offset
== r
.reg_offset
&&
203 negate
== r
.negate
&&
205 writemask
== r
.writemask
&&
206 (reladdr
== r
.reladdr
||
207 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
208 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
209 sizeof(fixed_hw_reg
)) == 0);
213 vec4_instruction::is_send_from_grf()
216 case SHADER_OPCODE_SHADER_TIME_ADD
:
217 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
218 case SHADER_OPCODE_UNTYPED_ATOMIC
:
219 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
220 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
221 case SHADER_OPCODE_TYPED_ATOMIC
:
222 case SHADER_OPCODE_TYPED_SURFACE_READ
:
223 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
231 vec4_instruction::regs_read(unsigned arg
) const
233 if (src
[arg
].file
== BAD_FILE
)
237 case SHADER_OPCODE_SHADER_TIME_ADD
:
238 case SHADER_OPCODE_UNTYPED_ATOMIC
:
239 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
240 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
241 case SHADER_OPCODE_TYPED_ATOMIC
:
242 case SHADER_OPCODE_TYPED_SURFACE_READ
:
243 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
244 return arg
== 0 ? mlen
: 1;
246 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
247 return arg
== 1 ? mlen
: 1;
255 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
257 if (devinfo
->gen
== 6 && is_math())
260 if (is_send_from_grf())
263 if (!backend_instruction::can_do_source_mods())
270 * Returns how many MRFs an opcode will write over.
272 * Note that this is not the 0 or 1 implied writes in an actual gen
273 * instruction -- the generate_* functions generate additional MOVs
277 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
279 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
282 switch (inst
->opcode
) {
283 case SHADER_OPCODE_RCP
:
284 case SHADER_OPCODE_RSQ
:
285 case SHADER_OPCODE_SQRT
:
286 case SHADER_OPCODE_EXP2
:
287 case SHADER_OPCODE_LOG2
:
288 case SHADER_OPCODE_SIN
:
289 case SHADER_OPCODE_COS
:
291 case SHADER_OPCODE_INT_QUOTIENT
:
292 case SHADER_OPCODE_INT_REMAINDER
:
293 case SHADER_OPCODE_POW
:
295 case VS_OPCODE_URB_WRITE
:
297 case VS_OPCODE_PULL_CONSTANT_LOAD
:
299 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
301 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
303 case GS_OPCODE_URB_WRITE
:
304 case GS_OPCODE_URB_WRITE_ALLOCATE
:
305 case GS_OPCODE_THREAD_END
:
307 case GS_OPCODE_FF_SYNC
:
309 case SHADER_OPCODE_SHADER_TIME_ADD
:
311 case SHADER_OPCODE_TEX
:
312 case SHADER_OPCODE_TXL
:
313 case SHADER_OPCODE_TXD
:
314 case SHADER_OPCODE_TXF
:
315 case SHADER_OPCODE_TXF_CMS
:
316 case SHADER_OPCODE_TXF_MCS
:
317 case SHADER_OPCODE_TXS
:
318 case SHADER_OPCODE_TG4
:
319 case SHADER_OPCODE_TG4_OFFSET
:
320 return inst
->header_size
;
322 unreachable("not reached");
327 src_reg::equals(const src_reg
&r
) const
329 return (file
== r
.file
&&
331 reg_offset
== r
.reg_offset
&&
333 negate
== r
.negate
&&
335 swizzle
== r
.swizzle
&&
336 !reladdr
&& !r
.reladdr
&&
337 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
338 sizeof(fixed_hw_reg
)) == 0);
342 vec4_visitor::opt_vector_float()
344 bool progress
= false;
346 int last_reg
= -1, last_reg_offset
= -1;
347 enum register_file last_reg_file
= BAD_FILE
;
349 int remaining_channels
= 0;
352 vec4_instruction
*imm_inst
[4];
354 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
355 if (last_reg
!= inst
->dst
.reg
||
356 last_reg_offset
!= inst
->dst
.reg_offset
||
357 last_reg_file
!= inst
->dst
.file
) {
358 last_reg
= inst
->dst
.reg
;
359 last_reg_offset
= inst
->dst
.reg_offset
;
360 last_reg_file
= inst
->dst
.file
;
361 remaining_channels
= WRITEMASK_XYZW
;
366 if (inst
->opcode
!= BRW_OPCODE_MOV
||
367 inst
->dst
.writemask
== WRITEMASK_XYZW
||
368 inst
->src
[0].file
!= IMM
)
371 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
375 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
377 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
379 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
381 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
384 imm_inst
[inst_count
++] = inst
;
386 remaining_channels
&= ~inst
->dst
.writemask
;
387 if (remaining_channels
== 0) {
388 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
389 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
390 mov
->dst
.writemask
= WRITEMASK_XYZW
;
391 inst
->insert_after(block
, mov
);
394 for (int i
= 0; i
< inst_count
; i
++) {
395 imm_inst
[i
]->remove(block
);
402 invalidate_live_intervals();
407 /* Replaces unused channels of a swizzle with channels that are used.
409 * For instance, this pass transforms
411 * mov vgrf4.yz, vgrf5.wxzy
415 * mov vgrf4.yz, vgrf5.xxzx
417 * This eliminates false uses of some channels, letting dead code elimination
418 * remove the instructions that wrote them.
421 vec4_visitor::opt_reduce_swizzle()
423 bool progress
= false;
425 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
426 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
427 inst
->is_send_from_grf())
432 /* Determine which channels of the sources are read. */
433 switch (inst
->opcode
) {
434 case VEC4_OPCODE_PACK_BYTES
:
436 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
437 * but all four of src1.
439 swizzle
= brw_swizzle_for_size(4);
442 swizzle
= brw_swizzle_for_size(3);
445 swizzle
= brw_swizzle_for_size(2);
448 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
452 /* Update sources' swizzles. */
453 for (int i
= 0; i
< 3; i
++) {
454 if (inst
->src
[i
].file
!= GRF
&&
455 inst
->src
[i
].file
!= ATTR
&&
456 inst
->src
[i
].file
!= UNIFORM
)
459 const unsigned new_swizzle
=
460 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
461 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
462 inst
->src
[i
].swizzle
= new_swizzle
;
469 invalidate_live_intervals();
475 vec4_visitor::split_uniform_registers()
477 /* Prior to this, uniforms have been in an array sized according to
478 * the number of vector uniforms present, sparsely filled (so an
479 * aggregate results in reg indices being skipped over). Now we're
480 * going to cut those aggregates up so each .reg index is one
481 * vector. The goal is to make elimination of unused uniform
482 * components easier later.
484 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
485 for (int i
= 0 ; i
< 3; i
++) {
486 if (inst
->src
[i
].file
!= UNIFORM
)
489 assert(!inst
->src
[i
].reladdr
);
491 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
492 inst
->src
[i
].reg_offset
= 0;
496 /* Update that everything is now vector-sized. */
497 for (int i
= 0; i
< this->uniforms
; i
++) {
498 this->uniform_size
[i
] = 1;
503 vec4_visitor::pack_uniform_registers()
505 bool uniform_used
[this->uniforms
];
506 int new_loc
[this->uniforms
];
507 int new_chan
[this->uniforms
];
509 memset(uniform_used
, 0, sizeof(uniform_used
));
510 memset(new_loc
, 0, sizeof(new_loc
));
511 memset(new_chan
, 0, sizeof(new_chan
));
513 /* Find which uniform vectors are actually used by the program. We
514 * expect unused vector elements when we've moved array access out
515 * to pull constants, and from some GLSL code generators like wine.
517 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
518 for (int i
= 0 ; i
< 3; i
++) {
519 if (inst
->src
[i
].file
!= UNIFORM
)
522 uniform_used
[inst
->src
[i
].reg
] = true;
526 int new_uniform_count
= 0;
528 /* Now, figure out a packing of the live uniform vectors into our
531 for (int src
= 0; src
< uniforms
; src
++) {
532 assert(src
< uniform_array_size
);
533 int size
= this->uniform_vector_size
[src
];
535 if (!uniform_used
[src
]) {
536 this->uniform_vector_size
[src
] = 0;
541 /* Find the lowest place we can slot this uniform in. */
542 for (dst
= 0; dst
< src
; dst
++) {
543 if (this->uniform_vector_size
[dst
] + size
<= 4)
552 new_chan
[src
] = this->uniform_vector_size
[dst
];
554 /* Move the references to the data */
555 for (int j
= 0; j
< size
; j
++) {
556 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
557 stage_prog_data
->param
[src
* 4 + j
];
560 this->uniform_vector_size
[dst
] += size
;
561 this->uniform_vector_size
[src
] = 0;
564 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
567 this->uniforms
= new_uniform_count
;
569 /* Now, update the instructions for our repacked uniforms. */
570 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
571 for (int i
= 0 ; i
< 3; i
++) {
572 int src
= inst
->src
[i
].reg
;
574 if (inst
->src
[i
].file
!= UNIFORM
)
577 inst
->src
[i
].reg
= new_loc
[src
];
578 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
579 new_chan
[src
], new_chan
[src
]);
585 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
587 * While GLSL IR also performs this optimization, we end up with it in
588 * our instruction stream for a couple of reasons. One is that we
589 * sometimes generate silly instructions, for example in array access
590 * where we'll generate "ADD offset, index, base" even if base is 0.
591 * The other is that GLSL IR's constant propagation doesn't track the
592 * components of aggregates, so some VS patterns (initialize matrix to
593 * 0, accumulate in vertex blending factors) end up breaking down to
594 * instructions involving 0.
597 vec4_visitor::opt_algebraic()
599 bool progress
= false;
601 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
602 switch (inst
->opcode
) {
604 if (inst
->src
[0].file
!= IMM
)
607 if (inst
->saturate
) {
608 if (inst
->dst
.type
!= inst
->src
[0].type
)
609 assert(!"unimplemented: saturate mixed types");
611 if (brw_saturate_immediate(inst
->dst
.type
,
612 &inst
->src
[0].fixed_hw_reg
)) {
613 inst
->saturate
= false;
619 case VEC4_OPCODE_UNPACK_UNIFORM
:
620 if (inst
->src
[0].file
!= UNIFORM
) {
621 inst
->opcode
= BRW_OPCODE_MOV
;
627 if (inst
->src
[1].is_zero()) {
628 inst
->opcode
= BRW_OPCODE_MOV
;
629 inst
->src
[1] = src_reg();
635 if (inst
->src
[1].is_zero()) {
636 inst
->opcode
= BRW_OPCODE_MOV
;
637 switch (inst
->src
[0].type
) {
638 case BRW_REGISTER_TYPE_F
:
639 inst
->src
[0] = src_reg(0.0f
);
641 case BRW_REGISTER_TYPE_D
:
642 inst
->src
[0] = src_reg(0);
644 case BRW_REGISTER_TYPE_UD
:
645 inst
->src
[0] = src_reg(0u);
648 unreachable("not reached");
650 inst
->src
[1] = src_reg();
652 } else if (inst
->src
[1].is_one()) {
653 inst
->opcode
= BRW_OPCODE_MOV
;
654 inst
->src
[1] = src_reg();
656 } else if (inst
->src
[1].is_negative_one()) {
657 inst
->opcode
= BRW_OPCODE_MOV
;
658 inst
->src
[0].negate
= !inst
->src
[0].negate
;
659 inst
->src
[1] = src_reg();
664 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
666 inst
->src
[0].negate
&&
667 inst
->src
[1].is_zero()) {
668 inst
->src
[0].abs
= false;
669 inst
->src
[0].negate
= false;
670 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
675 case SHADER_OPCODE_RCP
: {
676 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
677 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
678 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
679 inst
->opcode
= SHADER_OPCODE_RSQ
;
680 inst
->src
[0] = prev
->src
[0];
686 case SHADER_OPCODE_BROADCAST
:
687 if (is_uniform(inst
->src
[0]) ||
688 inst
->src
[1].is_zero()) {
689 inst
->opcode
= BRW_OPCODE_MOV
;
690 inst
->src
[1] = src_reg();
691 inst
->force_writemask_all
= true;
702 invalidate_live_intervals();
708 * Only a limited number of hardware registers may be used for push
709 * constants, so this turns access to the overflowed constants into
713 vec4_visitor::move_push_constants_to_pull_constants()
715 int pull_constant_loc
[this->uniforms
];
717 /* Only allow 32 registers (256 uniform components) as push constants,
718 * which is the limit on gen6.
720 * If changing this value, note the limitation about total_regs in
723 int max_uniform_components
= 32 * 8;
724 if (this->uniforms
* 4 <= max_uniform_components
)
727 /* Make some sort of choice as to which uniforms get sent to pull
728 * constants. We could potentially do something clever here like
729 * look for the most infrequently used uniform vec4s, but leave
732 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
733 pull_constant_loc
[i
/ 4] = -1;
735 if (i
>= max_uniform_components
) {
736 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
738 /* Try to find an existing copy of this uniform in the pull
739 * constants if it was part of an array access already.
741 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
744 for (matches
= 0; matches
< 4; matches
++) {
745 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
750 pull_constant_loc
[i
/ 4] = j
/ 4;
755 if (pull_constant_loc
[i
/ 4] == -1) {
756 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
757 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
759 for (int j
= 0; j
< 4; j
++) {
760 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
767 /* Now actually rewrite usage of the things we've moved to pull
770 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
771 for (int i
= 0 ; i
< 3; i
++) {
772 if (inst
->src
[i
].file
!= UNIFORM
||
773 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
776 int uniform
= inst
->src
[i
].reg
;
778 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
780 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
781 pull_constant_loc
[uniform
]);
783 inst
->src
[i
].file
= temp
.file
;
784 inst
->src
[i
].reg
= temp
.reg
;
785 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
786 inst
->src
[i
].reladdr
= NULL
;
790 /* Repack push constants to remove the now-unused ones. */
791 pack_uniform_registers();
794 /* Conditions for which we want to avoid setting the dependency control bits */
796 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
798 #define IS_DWORD(reg) \
799 (reg.type == BRW_REGISTER_TYPE_UD || \
800 reg.type == BRW_REGISTER_TYPE_D)
802 /* "When source or destination datatype is 64b or operation is integer DWord
803 * multiply, DepCtrl must not be used."
804 * May apply to future SoCs as well.
806 if (devinfo
->is_cherryview
) {
807 if (inst
->opcode
== BRW_OPCODE_MUL
&&
808 IS_DWORD(inst
->src
[0]) &&
809 IS_DWORD(inst
->src
[1]))
814 if (devinfo
->gen
>= 8) {
815 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
821 * In the presence of send messages, totally interrupt dependency
822 * control. They're long enough that the chance of dependency
823 * control around them just doesn't matter.
826 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
827 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
828 * completes the scoreboard clear must have a non-zero execution mask. This
829 * means, if any kind of predication can change the execution mask or channel
830 * enable of the last instruction, the optimization must be avoided. This is
831 * to avoid instructions being shot down the pipeline when no writes are
835 * Dependency control does not work well over math instructions.
836 * NB: Discovered empirically
838 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
842 * Sets the dependency control fields on instructions after register
843 * allocation and before the generator is run.
845 * When you have a sequence of instructions like:
847 * DP4 temp.x vertex uniform[0]
848 * DP4 temp.y vertex uniform[0]
849 * DP4 temp.z vertex uniform[0]
850 * DP4 temp.w vertex uniform[0]
852 * The hardware doesn't know that it can actually run the later instructions
853 * while the previous ones are in flight, producing stalls. However, we have
854 * manual fields we can set in the instructions that let it do so.
857 vec4_visitor::opt_set_dependency_control()
859 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
860 uint8_t grf_channels_written
[BRW_MAX_GRF
];
861 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
862 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
864 assert(prog_data
->total_grf
||
865 !"Must be called after register allocation");
867 foreach_block (block
, cfg
) {
868 memset(last_grf_write
, 0, sizeof(last_grf_write
));
869 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
871 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
872 /* If we read from a register that we were doing dependency control
873 * on, don't do dependency control across the read.
875 for (int i
= 0; i
< 3; i
++) {
876 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
877 if (inst
->src
[i
].file
== GRF
) {
878 last_grf_write
[reg
] = NULL
;
879 } else if (inst
->src
[i
].file
== HW_REG
) {
880 memset(last_grf_write
, 0, sizeof(last_grf_write
));
883 assert(inst
->src
[i
].file
!= MRF
);
886 if (is_dep_ctrl_unsafe(inst
)) {
887 memset(last_grf_write
, 0, sizeof(last_grf_write
));
888 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
892 /* Now, see if we can do dependency control for this instruction
893 * against a previous one writing to its destination.
895 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
896 if (inst
->dst
.file
== GRF
) {
897 if (last_grf_write
[reg
] &&
898 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
899 last_grf_write
[reg
]->no_dd_clear
= true;
900 inst
->no_dd_check
= true;
902 grf_channels_written
[reg
] = 0;
905 last_grf_write
[reg
] = inst
;
906 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
907 } else if (inst
->dst
.file
== MRF
) {
908 if (last_mrf_write
[reg
] &&
909 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
910 last_mrf_write
[reg
]->no_dd_clear
= true;
911 inst
->no_dd_check
= true;
913 mrf_channels_written
[reg
] = 0;
916 last_mrf_write
[reg
] = inst
;
917 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
918 } else if (inst
->dst
.reg
== HW_REG
) {
919 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
920 memset(last_grf_write
, 0, sizeof(last_grf_write
));
921 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
922 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
929 vec4_instruction::can_reswizzle(int dst_writemask
,
933 /* If this instruction sets anything not referenced by swizzle, then we'd
934 * totally break it when we reswizzle.
936 if (dst
.writemask
& ~swizzle_mask
)
946 * For any channels in the swizzle's source that were populated by this
947 * instruction, rewrite the instruction to put the appropriate result directly
950 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
953 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
955 /* Destination write mask doesn't correspond to source swizzle for the dot
956 * product and pack_bytes instructions.
958 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
959 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
960 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
961 for (int i
= 0; i
< 3; i
++) {
962 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
965 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
969 /* Apply the specified swizzle and writemask to the original mask of
970 * written components.
972 dst
.writemask
= dst_writemask
&
973 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
977 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
978 * just written and then MOVed into another reg and making the original write
979 * of the GRF write directly to the final destination instead.
982 vec4_visitor::opt_register_coalesce()
984 bool progress
= false;
987 calculate_live_intervals();
989 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
993 if (inst
->opcode
!= BRW_OPCODE_MOV
||
994 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
996 inst
->src
[0].file
!= GRF
||
997 inst
->dst
.type
!= inst
->src
[0].type
||
998 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1001 bool to_mrf
= (inst
->dst
.file
== MRF
);
1003 /* Can't coalesce this GRF if someone else was going to
1006 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1009 /* We need to check interference with the final destination between this
1010 * instruction and the earliest instruction involved in writing the GRF
1011 * we're eliminating. To do that, keep track of which of our source
1012 * channels we've seen initialized.
1014 const unsigned chans_needed
=
1015 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1016 inst
->dst
.writemask
);
1017 unsigned chans_remaining
= chans_needed
;
1019 /* Now walk up the instruction stream trying to see if we can rewrite
1020 * everything writing to the temporary to write into the destination
1023 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1024 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1026 _scan_inst
= scan_inst
;
1028 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1029 /* Found something writing to the reg we want to coalesce away. */
1031 /* SEND instructions can't have MRF as a destination. */
1032 if (scan_inst
->mlen
)
1035 if (devinfo
->gen
== 6) {
1036 /* gen6 math instructions must have the destination be
1037 * GRF, so no compute-to-MRF for them.
1039 if (scan_inst
->is_math()) {
1045 /* If we can't handle the swizzle, bail. */
1046 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1047 inst
->src
[0].swizzle
,
1052 /* This doesn't handle coalescing of multiple registers. */
1053 if (scan_inst
->regs_written
> 1)
1056 /* Mark which channels we found unconditional writes for. */
1057 if (!scan_inst
->predicate
)
1058 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1060 if (chans_remaining
== 0)
1064 /* You can't read from an MRF, so if someone else reads our MRF's
1065 * source GRF that we wanted to rewrite, that stops us. If it's a
1066 * GRF we're trying to coalesce to, we don't actually handle
1067 * rewriting sources so bail in that case as well.
1069 bool interfered
= false;
1070 for (int i
= 0; i
< 3; i
++) {
1071 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1072 scan_inst
->regs_read(i
)))
1078 /* If somebody else writes our destination here, we can't coalesce
1081 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
))
1084 /* Check for reads of the register we're trying to coalesce into. We
1085 * can't go rewriting instructions above that to put some other value
1086 * in the register instead.
1088 if (to_mrf
&& scan_inst
->mlen
> 0) {
1089 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1090 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1094 for (int i
= 0; i
< 3; i
++) {
1095 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1096 scan_inst
->regs_read(i
)))
1104 if (chans_remaining
== 0) {
1105 /* If we've made it here, we have an MOV we want to coalesce out, and
1106 * a scan_inst pointing to the earliest instruction involved in
1107 * computing the value. Now go rewrite the instruction stream
1110 vec4_instruction
*scan_inst
= _scan_inst
;
1111 while (scan_inst
!= inst
) {
1112 if (scan_inst
->dst
.file
== GRF
&&
1113 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1114 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1115 scan_inst
->reswizzle(inst
->dst
.writemask
,
1116 inst
->src
[0].swizzle
);
1117 scan_inst
->dst
.file
= inst
->dst
.file
;
1118 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1119 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1120 scan_inst
->saturate
|= inst
->saturate
;
1122 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1124 inst
->remove(block
);
1130 invalidate_live_intervals();
1136 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1137 * flow. We could probably do better here with some form of divergence
1141 vec4_visitor::eliminate_find_live_channel()
1143 bool progress
= false;
1146 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1147 switch (inst
->opcode
) {
1153 case BRW_OPCODE_ENDIF
:
1154 case BRW_OPCODE_WHILE
:
1158 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1160 inst
->opcode
= BRW_OPCODE_MOV
;
1161 inst
->src
[0] = src_reg(0);
1162 inst
->force_writemask_all
= true;
1176 * Splits virtual GRFs requesting more than one contiguous physical register.
1178 * We initially create large virtual GRFs for temporary structures, arrays,
1179 * and matrices, so that the dereference visitor functions can add reg_offsets
1180 * to work their way down to the actual member being accessed. But when it
1181 * comes to optimization, we'd like to treat each register as individual
1182 * storage if possible.
1184 * So far, the only thing that might prevent splitting is a send message from
1188 vec4_visitor::split_virtual_grfs()
1190 int num_vars
= this->alloc
.count
;
1191 int new_virtual_grf
[num_vars
];
1192 bool split_grf
[num_vars
];
1194 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1196 /* Try to split anything > 0 sized. */
1197 for (int i
= 0; i
< num_vars
; i
++) {
1198 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1201 /* Check that the instructions are compatible with the registers we're trying
1204 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1205 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1206 split_grf
[inst
->dst
.reg
] = false;
1208 for (int i
= 0; i
< 3; i
++) {
1209 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1210 split_grf
[inst
->src
[i
].reg
] = false;
1214 /* Allocate new space for split regs. Note that the virtual
1215 * numbers will be contiguous.
1217 for (int i
= 0; i
< num_vars
; i
++) {
1221 new_virtual_grf
[i
] = alloc
.allocate(1);
1222 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1223 unsigned reg
= alloc
.allocate(1);
1224 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1227 this->alloc
.sizes
[i
] = 1;
1230 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1231 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1232 inst
->dst
.reg_offset
!= 0) {
1233 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1234 inst
->dst
.reg_offset
- 1);
1235 inst
->dst
.reg_offset
= 0;
1237 for (int i
= 0; i
< 3; i
++) {
1238 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1239 inst
->src
[i
].reg_offset
!= 0) {
1240 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1241 inst
->src
[i
].reg_offset
- 1);
1242 inst
->src
[i
].reg_offset
= 0;
1246 invalidate_live_intervals();
1250 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1252 dump_instruction(be_inst
, stderr
);
1256 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1258 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1260 if (inst
->predicate
) {
1261 fprintf(file
, "(%cf0.%d) ",
1262 inst
->predicate_inverse
? '-' : '+',
1266 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1268 fprintf(file
, ".sat");
1269 if (inst
->conditional_mod
) {
1270 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1271 if (!inst
->predicate
&&
1272 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1273 inst
->opcode
!= BRW_OPCODE_IF
&&
1274 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1275 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1280 switch (inst
->dst
.file
) {
1282 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1285 fprintf(file
, "m%d", inst
->dst
.reg
);
1288 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1289 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1291 fprintf(file
, "null");
1293 case BRW_ARF_ADDRESS
:
1294 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1296 case BRW_ARF_ACCUMULATOR
:
1297 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1300 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1301 inst
->dst
.fixed_hw_reg
.subnr
);
1304 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1305 inst
->dst
.fixed_hw_reg
.subnr
);
1309 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1311 if (inst
->dst
.fixed_hw_reg
.subnr
)
1312 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1315 fprintf(file
, "(null)");
1318 fprintf(file
, "???");
1321 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1323 if (inst
->dst
.writemask
& 1)
1325 if (inst
->dst
.writemask
& 2)
1327 if (inst
->dst
.writemask
& 4)
1329 if (inst
->dst
.writemask
& 8)
1332 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1334 if (inst
->src
[0].file
!= BAD_FILE
)
1335 fprintf(file
, ", ");
1337 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1338 if (inst
->src
[i
].negate
)
1340 if (inst
->src
[i
].abs
)
1342 switch (inst
->src
[i
].file
) {
1344 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1347 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1350 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1353 switch (inst
->src
[i
].type
) {
1354 case BRW_REGISTER_TYPE_F
:
1355 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1357 case BRW_REGISTER_TYPE_D
:
1358 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1360 case BRW_REGISTER_TYPE_UD
:
1361 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1363 case BRW_REGISTER_TYPE_VF
:
1364 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1365 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1366 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1367 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1368 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1371 fprintf(file
, "???");
1376 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1378 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1380 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1381 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1383 fprintf(file
, "null");
1385 case BRW_ARF_ADDRESS
:
1386 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1388 case BRW_ARF_ACCUMULATOR
:
1389 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1392 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1393 inst
->src
[i
].fixed_hw_reg
.subnr
);
1396 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1397 inst
->src
[i
].fixed_hw_reg
.subnr
);
1401 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1403 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1404 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1405 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1409 fprintf(file
, "(null)");
1412 fprintf(file
, "???");
1416 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1417 if (inst
->src
[i
].reg_offset
!= 0 &&
1418 inst
->src
[i
].file
== GRF
&&
1419 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1420 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1422 if (inst
->src
[i
].file
!= IMM
) {
1423 static const char *chans
[4] = {"x", "y", "z", "w"};
1425 for (int c
= 0; c
< 4; c
++) {
1426 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1430 if (inst
->src
[i
].abs
)
1433 if (inst
->src
[i
].file
!= IMM
) {
1434 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1437 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1438 fprintf(file
, ", ");
1441 fprintf(file
, "\n");
1445 static inline struct brw_reg
1446 attribute_to_hw_reg(int attr
, bool interleaved
)
1449 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1451 return brw_vec8_grf(attr
, 0);
1456 * Replace each register of type ATTR in this->instructions with a reference
1457 * to a fixed HW register.
1459 * If interleaved is true, then each attribute takes up half a register, with
1460 * register N containing attribute 2*N in its first half and attribute 2*N+1
1461 * in its second half (this corresponds to the payload setup used by geometry
1462 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1463 * false, then each attribute takes up a whole register, with register N
1464 * containing attribute N (this corresponds to the payload setup used by
1465 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1468 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1471 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1472 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1473 if (inst
->dst
.file
== ATTR
) {
1474 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1476 /* All attributes used in the shader need to have been assigned a
1477 * hardware register by the caller
1481 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1482 reg
.type
= inst
->dst
.type
;
1483 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1485 inst
->dst
.file
= HW_REG
;
1486 inst
->dst
.fixed_hw_reg
= reg
;
1489 for (int i
= 0; i
< 3; i
++) {
1490 if (inst
->src
[i
].file
!= ATTR
)
1493 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1495 /* All attributes used in the shader need to have been assigned a
1496 * hardware register by the caller
1500 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1501 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1502 reg
.type
= inst
->src
[i
].type
;
1503 if (inst
->src
[i
].abs
)
1505 if (inst
->src
[i
].negate
)
1508 inst
->src
[i
].file
= HW_REG
;
1509 inst
->src
[i
].fixed_hw_reg
= reg
;
1515 vec4_vs_visitor::setup_attributes(int payload_reg
)
1518 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1519 memset(attribute_map
, 0, sizeof(attribute_map
));
1522 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1523 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1524 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1529 /* VertexID is stored by the VF as the last vertex element, but we
1530 * don't represent it with a flag in inputs_read, so we call it
1533 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1534 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1538 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1540 /* The BSpec says we always have to read at least one thing from
1541 * the VF, and it appears that the hardware wedges otherwise.
1543 if (nr_attributes
== 0)
1546 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1548 unsigned vue_entries
=
1549 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1551 if (devinfo
->gen
== 6)
1552 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1554 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1556 return payload_reg
+ nr_attributes
;
1560 vec4_visitor::setup_uniforms(int reg
)
1562 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1564 /* The pre-gen6 VS requires that some push constants get loaded no
1565 * matter what, or the GPU would hang.
1567 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1568 assert(this->uniforms
< this->uniform_array_size
);
1569 this->uniform_vector_size
[this->uniforms
] = 1;
1571 stage_prog_data
->param
=
1572 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1573 for (unsigned int i
= 0; i
< 4; i
++) {
1574 unsigned int slot
= this->uniforms
* 4 + i
;
1575 static gl_constant_value zero
= { 0.0 };
1576 stage_prog_data
->param
[slot
] = &zero
;
1582 reg
+= ALIGN(uniforms
, 2) / 2;
1585 stage_prog_data
->nr_params
= this->uniforms
* 4;
1587 prog_data
->base
.curb_read_length
=
1588 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1594 vec4_vs_visitor::setup_payload(void)
1598 /* The payload always contains important data in g0, which contains
1599 * the URB handles that are passed on to the URB write at the end
1600 * of the thread. So, we always start push constants at g1.
1604 reg
= setup_uniforms(reg
);
1606 reg
= setup_attributes(reg
);
1608 this->first_non_payload_grf
= reg
;
1612 vec4_visitor::assign_binding_table_offsets()
1614 assign_common_binding_table_offsets(0);
1618 vec4_visitor::get_timestamp()
1620 assert(devinfo
->gen
>= 7);
1622 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1627 BRW_REGISTER_TYPE_UD
,
1628 BRW_VERTICAL_STRIDE_0
,
1630 BRW_HORIZONTAL_STRIDE_4
,
1634 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1636 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1637 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1638 * even if it's not enabled in the dispatch.
1640 mov
->force_writemask_all
= true;
1642 return src_reg(dst
);
1646 vec4_visitor::emit_shader_time_begin()
1648 current_annotation
= "shader time start";
1649 shader_start_time
= get_timestamp();
1653 vec4_visitor::emit_shader_time_end()
1655 current_annotation
= "shader time end";
1656 src_reg shader_end_time
= get_timestamp();
1659 /* Check that there weren't any timestamp reset events (assuming these
1660 * were the only two timestamp reads that happened).
1662 src_reg reset_end
= shader_end_time
;
1663 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1664 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1665 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1667 emit(IF(BRW_PREDICATE_NORMAL
));
1669 /* Take the current timestamp and get the delta. */
1670 shader_start_time
.negate
= true;
1671 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1672 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1674 /* If there were no instructions between the two timestamp gets, the diff
1675 * is 2 cycles. Remove that overhead, so I can forget about that when
1676 * trying to determine the time taken for single instructions.
1678 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1680 emit_shader_time_write(0, src_reg(diff
));
1681 emit_shader_time_write(1, src_reg(1u));
1682 emit(BRW_OPCODE_ELSE
);
1683 emit_shader_time_write(2, src_reg(1u));
1684 emit(BRW_OPCODE_ENDIF
);
1688 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1691 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1693 dst_reg offset
= dst
;
1697 offset
.type
= BRW_REGISTER_TYPE_UD
;
1698 int index
= shader_time_index
* 3 + shader_time_subindex
;
1699 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1701 time
.type
= BRW_REGISTER_TYPE_UD
;
1702 emit(MOV(time
, src_reg(value
)));
1704 vec4_instruction
*inst
=
1705 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1710 vec4_visitor::run(gl_clip_plane
*clip_planes
)
1712 sanity_param_count
= prog
->Parameters
->NumParameters
;
1714 if (shader_time_index
>= 0)
1715 emit_shader_time_begin();
1717 assign_binding_table_offsets();
1721 /* Generate VS IR for main(). (the visitor only descends into
1722 * functions called "main").
1725 visit_instructions(shader
->base
.ir
);
1727 emit_program_code();
1731 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1732 setup_uniform_clipplane_values(clip_planes
);
1738 /* Before any optimization, push array accesses out to scratch
1739 * space where we need them to be. This pass may allocate new
1740 * virtual GRFs, so we want to do it early. It also makes sure
1741 * that we have reladdr computations available for CSE, since we'll
1742 * often do repeated subexpressions for those.
1745 move_grf_array_access_to_scratch();
1746 move_uniform_array_access_to_pull_constants();
1748 /* The ARB_vertex_program frontend emits pull constant loads directly
1749 * rather than using reladdr, so we don't need to walk through all the
1750 * instructions looking for things to move. There isn't anything.
1752 * We do still need to split things to vec4 size.
1754 split_uniform_registers();
1756 pack_uniform_registers();
1757 move_push_constants_to_pull_constants();
1758 split_virtual_grfs();
1760 #define OPT(pass, args...) ({ \
1762 bool this_progress = pass(args); \
1764 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1765 char filename[64]; \
1766 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1767 stage_abbrev, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1769 backend_shader::dump_instructions(filename); \
1772 progress = progress || this_progress; \
1777 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1779 snprintf(filename
, 64, "%s-%04d-00-start",
1780 stage_abbrev
, shader_prog
? shader_prog
->Name
: 0);
1782 backend_shader::dump_instructions(filename
);
1793 OPT(opt_reduce_swizzle
);
1794 OPT(dead_code_eliminate
);
1795 OPT(dead_control_flow_eliminate
, this);
1796 OPT(opt_copy_propagation
);
1799 OPT(opt_register_coalesce
);
1800 OPT(eliminate_find_live_channel
);
1805 if (OPT(opt_vector_float
)) {
1807 OPT(opt_copy_propagation
, false);
1808 OPT(opt_copy_propagation
, true);
1809 OPT(dead_code_eliminate
);
1818 /* Debug of register spilling: Go spill everything. */
1819 const int grf_count
= alloc
.count
;
1820 float spill_costs
[alloc
.count
];
1821 bool no_spill
[alloc
.count
];
1822 evaluate_spill_costs(spill_costs
, no_spill
);
1823 for (int i
= 0; i
< grf_count
; i
++) {
1830 bool allocated_without_spills
= reg_allocate();
1832 if (!allocated_without_spills
) {
1833 compiler
->shader_perf_log(log_data
,
1834 "%s shader triggered register spilling. "
1835 "Try reducing the number of live vec4 values "
1836 "to improve performance.\n",
1839 while (!reg_allocate()) {
1845 opt_schedule_instructions();
1847 opt_set_dependency_control();
1849 /* If any state parameters were appended, then ParameterValues could have
1850 * been realloced, in which case the driver uniform storage set up by
1851 * _mesa_associate_uniform_storage() would point to freed memory. Make
1852 * sure that didn't happen.
1854 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1859 } /* namespace brw */
1864 * Compile a vertex shader.
1866 * Returns the final assembly and the program's size.
1869 brw_vs_emit(struct brw_context
*brw
,
1870 struct gl_shader_program
*prog
,
1871 struct brw_vs_compile
*c
,
1872 struct brw_vs_prog_data
*prog_data
,
1874 unsigned *final_assembly_size
)
1876 bool start_busy
= false;
1877 double start_time
= 0;
1878 const unsigned *assembly
= NULL
;
1880 if (unlikely(brw
->perf_debug
)) {
1881 start_busy
= (brw
->batch
.last_bo
&&
1882 drm_intel_bo_busy(brw
->batch
.last_bo
));
1883 start_time
= get_time();
1886 struct brw_shader
*shader
= NULL
;
1888 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1891 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1892 st_index
= brw_get_shader_time_index(brw
, prog
, &c
->vp
->program
.Base
,
1895 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1896 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1898 if (brw
->intelScreen
->compiler
->scalar_vs
) {
1899 if (!c
->vp
->program
.Base
.nir
) {
1900 /* Normally we generate NIR in LinkShader() or
1901 * ProgramStringNotify(), but Mesa's fixed-function vertex program
1902 * handling doesn't notify the driver at all. Just do it here, at
1903 * the last minute, even though it's lame.
1905 assert(c
->vp
->program
.Base
.Id
== 0 && prog
== NULL
);
1906 c
->vp
->program
.Base
.nir
=
1907 brw_create_nir(brw
, NULL
, &c
->vp
->program
.Base
, MESA_SHADER_VERTEX
);
1910 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1912 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
1913 mem_ctx
, MESA_SHADER_VERTEX
, &c
->key
,
1914 &prog_data
->base
.base
, prog
, &c
->vp
->program
.Base
,
1916 if (!v
.run_vs(brw_select_clip_planes(&brw
->ctx
))) {
1918 prog
->LinkStatus
= false;
1919 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1922 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1928 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
1929 mem_ctx
, (void *) &c
->key
, &prog_data
->base
.base
,
1930 &c
->vp
->program
.Base
, v
.promoted_constants
,
1931 v
.runtime_check_aads_emit
, "VS");
1932 if (INTEL_DEBUG
& DEBUG_VS
) {
1935 name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1936 prog
->Label
? prog
->Label
: "unnamed",
1939 name
= ralloc_asprintf(mem_ctx
, "vertex program %d",
1940 c
->vp
->program
.Base
.Id
);
1942 g
.enable_debug(name
);
1944 g
.generate_code(v
.cfg
, 8);
1945 assembly
= g
.get_assembly(final_assembly_size
);
1947 c
->base
.last_scratch
= v
.last_scratch
;
1951 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
1953 vec4_vs_visitor
v(brw
->intelScreen
->compiler
, brw
,
1954 c
, prog_data
, prog
, mem_ctx
, st_index
,
1955 !_mesa_is_gles3(&brw
->ctx
));
1956 if (!v
.run(brw_select_clip_planes(&brw
->ctx
))) {
1958 prog
->LinkStatus
= false;
1959 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1962 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1968 vec4_generator
g(brw
->intelScreen
->compiler
, brw
,
1969 prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1970 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
1971 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1974 if (unlikely(brw
->perf_debug
) && shader
) {
1975 if (shader
->compiled_once
) {
1976 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1978 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1979 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1980 (get_time() - start_time
) * 1000);
1982 shader
->compiled_once
= true;
1990 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1991 struct brw_vue_prog_key
*key
,
1992 GLuint id
, struct gl_program
*prog
)
1994 struct brw_context
*brw
= brw_context(ctx
);
1995 key
->program_string_id
= id
;
1997 brw_setup_tex_for_precompile(brw
, &key
->tex
, prog
);