2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size
)
51 static const unsigned size_swizzles
[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
58 assert((size
>= 1) && (size
<= 4));
59 return size_swizzles
[size
- 1];
65 memset(this, 0, sizeof(*this));
67 this->file
= BAD_FILE
;
70 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= BRW_SWIZZLE_XYZW
;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f
)
93 this->type
= BRW_REGISTER_TYPE_F
;
94 this->fixed_hw_reg
.dw1
.f
= f
;
97 src_reg::src_reg(uint32_t u
)
102 this->type
= BRW_REGISTER_TYPE_UD
;
103 this->fixed_hw_reg
.dw1
.ud
= u
;
106 src_reg::src_reg(int32_t i
)
111 this->type
= BRW_REGISTER_TYPE_D
;
112 this->fixed_hw_reg
.dw1
.d
= i
;
115 src_reg::src_reg(struct brw_reg reg
)
120 this->fixed_hw_reg
= reg
;
121 this->type
= reg
.type
;
124 src_reg::src_reg(dst_reg reg
)
128 this->file
= reg
.file
;
130 this->reg_offset
= reg
.reg_offset
;
131 this->type
= reg
.type
;
132 this->reladdr
= reg
.reladdr
;
133 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
139 for (int i
= 0; i
< 4; i
++) {
140 if (!(reg
.writemask
& (1 << i
)))
143 swizzles
[next_chan
++] = last
= i
;
146 for (; next_chan
< 4; next_chan
++) {
147 swizzles
[next_chan
] = last
;
150 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
151 swizzles
[2], swizzles
[3]);
157 memset(this, 0, sizeof(*this));
158 this->file
= BAD_FILE
;
159 this->writemask
= WRITEMASK_XYZW
;
167 dst_reg::dst_reg(register_file file
, int reg
)
175 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
182 this->type
= brw_type_for_base_type(type
);
183 this->writemask
= writemask
;
186 dst_reg::dst_reg(struct brw_reg reg
)
191 this->fixed_hw_reg
= reg
;
192 this->type
= reg
.type
;
195 dst_reg::dst_reg(src_reg reg
)
199 this->file
= reg
.file
;
201 this->reg_offset
= reg
.reg_offset
;
202 this->type
= reg
.type
;
203 /* How should we do writemasking when converting from a src_reg? It seems
204 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
205 * what about for src.wx? Just special-case src.xxxx for now.
207 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
208 this->writemask
= WRITEMASK_X
;
210 this->writemask
= WRITEMASK_XYZW
;
211 this->reladdr
= reg
.reladdr
;
212 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
216 vec4_instruction::is_send_from_grf()
219 case SHADER_OPCODE_SHADER_TIME_ADD
:
220 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
228 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
230 if (brw
->gen
== 6 && is_math())
233 if (is_send_from_grf())
236 if (!backend_instruction::can_do_source_mods())
243 * Returns how many MRFs an opcode will write over.
245 * Note that this is not the 0 or 1 implied writes in an actual gen
246 * instruction -- the generate_* functions generate additional MOVs
250 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
255 switch (inst
->opcode
) {
256 case SHADER_OPCODE_RCP
:
257 case SHADER_OPCODE_RSQ
:
258 case SHADER_OPCODE_SQRT
:
259 case SHADER_OPCODE_EXP2
:
260 case SHADER_OPCODE_LOG2
:
261 case SHADER_OPCODE_SIN
:
262 case SHADER_OPCODE_COS
:
264 case SHADER_OPCODE_INT_QUOTIENT
:
265 case SHADER_OPCODE_INT_REMAINDER
:
266 case SHADER_OPCODE_POW
:
268 case VS_OPCODE_URB_WRITE
:
270 case VS_OPCODE_PULL_CONSTANT_LOAD
:
272 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
274 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
276 case GS_OPCODE_URB_WRITE
:
277 case GS_OPCODE_THREAD_END
:
279 case SHADER_OPCODE_SHADER_TIME_ADD
:
281 case SHADER_OPCODE_TEX
:
282 case SHADER_OPCODE_TXL
:
283 case SHADER_OPCODE_TXD
:
284 case SHADER_OPCODE_TXF
:
285 case SHADER_OPCODE_TXF_CMS
:
286 case SHADER_OPCODE_TXF_MCS
:
287 case SHADER_OPCODE_TXS
:
288 case SHADER_OPCODE_TG4
:
289 case SHADER_OPCODE_TG4_OFFSET
:
290 return inst
->header_present
? 1 : 0;
291 case SHADER_OPCODE_UNTYPED_ATOMIC
:
292 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
295 unreachable("not reached");
300 src_reg::equals(const src_reg
&r
) const
302 return (file
== r
.file
&&
304 reg_offset
== r
.reg_offset
&&
306 negate
== r
.negate
&&
308 swizzle
== r
.swizzle
&&
309 !reladdr
&& !r
.reladdr
&&
310 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
311 sizeof(fixed_hw_reg
)) == 0);
314 /* Replaces unused channels of a swizzle with channels that are used.
316 * For instance, this pass transforms
318 * mov vgrf4.yz, vgrf5.wxzy
322 * mov vgrf4.yz, vgrf5.xxzx
324 * This eliminates false uses of some channels, letting dead code elimination
325 * remove the instructions that wrote them.
328 vec4_visitor::opt_reduce_swizzle()
330 bool progress
= false;
332 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
333 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
)
338 /* Determine which channels of the sources are read. */
339 switch (inst
->opcode
) {
341 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
342 * but all four of src1.
362 swizzle
[0] = inst
->dst
.writemask
& WRITEMASK_X
? 0 : -1;
363 swizzle
[1] = inst
->dst
.writemask
& WRITEMASK_Y
? 1 : -1;
364 swizzle
[2] = inst
->dst
.writemask
& WRITEMASK_Z
? 2 : -1;
365 swizzle
[3] = inst
->dst
.writemask
& WRITEMASK_W
? 3 : -1;
369 /* Resolve unread channels (-1) by assigning them the swizzle of the
370 * first channel that is used.
372 int first_used_channel
= 0;
373 for (int i
= 0; i
< 4; i
++) {
374 if (swizzle
[i
] != -1) {
375 first_used_channel
= swizzle
[i
];
379 for (int i
= 0; i
< 4; i
++) {
380 if (swizzle
[i
] == -1) {
381 swizzle
[i
] = first_used_channel
;
385 /* Update sources' swizzles. */
386 for (int i
= 0; i
< 3; i
++) {
387 if (inst
->src
[i
].file
!= GRF
&&
388 inst
->src
[i
].file
!= ATTR
&&
389 inst
->src
[i
].file
!= UNIFORM
)
393 for (int j
= 0; j
< 4; j
++) {
394 swiz
[j
] = BRW_GET_SWZ(inst
->src
[i
].swizzle
, swizzle
[j
]);
397 unsigned new_swizzle
= BRW_SWIZZLE4(swiz
[0], swiz
[1], swiz
[2], swiz
[3]);
398 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
399 inst
->src
[i
].swizzle
= new_swizzle
;
406 invalidate_live_intervals(false);
412 try_eliminate_instruction(vec4_instruction
*inst
, int new_writemask
,
413 const struct brw_context
*brw
)
415 if (inst
->has_side_effects())
418 if (new_writemask
== 0) {
419 /* Don't dead code eliminate instructions that write to the
420 * accumulator as a side-effect. Instead just set the destination
421 * to the null register to free it.
423 if (inst
->writes_accumulator
|| inst
->writes_flag()) {
424 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
430 } else if (inst
->dst
.writemask
!= new_writemask
) {
431 switch (inst
->opcode
) {
432 case SHADER_OPCODE_TXF_CMS
:
433 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
434 case VS_OPCODE_PULL_CONSTANT_LOAD
:
435 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
438 /* Do not set a writemask on Gen6 for math instructions, those are
439 * executed using align1 mode that does not support a destination mask.
441 if (!(brw
->gen
== 6 && inst
->is_math()) && !inst
->is_tex()) {
442 inst
->dst
.writemask
= new_writemask
;
452 * Must be called after calculate_live_intervals() to remove unused
453 * writes to registers -- register allocation will fail otherwise
454 * because something deffed but not used won't be considered to
455 * interfere with other regs.
458 vec4_visitor::dead_code_eliminate()
460 bool progress
= false;
463 calculate_live_intervals();
465 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
468 bool inst_writes_flag
= false;
469 if (inst
->dst
.file
!= GRF
) {
470 if (inst
->dst
.is_null() && inst
->writes_flag()) {
471 inst_writes_flag
= true;
477 if (inst
->dst
.file
== GRF
) {
478 int write_mask
= inst
->dst
.writemask
;
480 for (int c
= 0; c
< 4; c
++) {
481 if (write_mask
& (1 << c
)) {
482 assert(this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] >= pc
);
483 if (this->virtual_grf_end
[inst
->dst
.reg
* 4 + c
] == pc
) {
484 write_mask
&= ~(1 << c
);
489 progress
= try_eliminate_instruction(inst
, write_mask
, brw
) ||
493 if (inst
->predicate
|| inst
->prev
== NULL
)
497 if (inst_writes_flag
) {
498 /* Arbitrarily chosen, other than not being an xyzw writemask. */
499 #define FLAG_WRITEMASK (1 << 5)
500 dead_channels
= inst
->reads_flag() ? 0 : FLAG_WRITEMASK
;
502 dead_channels
= inst
->dst
.writemask
;
504 for (int i
= 0; i
< 3; i
++) {
505 if (inst
->src
[i
].file
!= GRF
||
506 inst
->src
[i
].reg
!= inst
->dst
.reg
)
509 for (int j
= 0; j
< 4; j
++) {
510 int swiz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, j
);
511 dead_channels
&= ~(1 << swiz
);
516 for (exec_node
*node
= inst
->prev
, *prev
= node
->prev
;
517 prev
!= NULL
&& dead_channels
!= 0;
518 node
= prev
, prev
= prev
->prev
) {
519 vec4_instruction
*scan_inst
= (vec4_instruction
*)node
;
521 if (scan_inst
->is_control_flow())
524 if (inst_writes_flag
) {
525 if (scan_inst
->dst
.is_null() && scan_inst
->writes_flag()) {
529 } else if (scan_inst
->reads_flag()) {
534 if (inst
->dst
.file
== scan_inst
->dst
.file
&&
535 inst
->dst
.reg
== scan_inst
->dst
.reg
&&
536 inst
->dst
.reg_offset
== scan_inst
->dst
.reg_offset
) {
537 int new_writemask
= scan_inst
->dst
.writemask
& ~dead_channels
;
539 progress
= try_eliminate_instruction(scan_inst
, new_writemask
, brw
) ||
543 for (int i
= 0; i
< 3; i
++) {
544 if (scan_inst
->src
[i
].file
!= inst
->dst
.file
||
545 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
)
548 for (int j
= 0; j
< 4; j
++) {
549 int swiz
= BRW_GET_SWZ(scan_inst
->src
[i
].swizzle
, j
);
550 dead_channels
&= ~(1 << swiz
);
557 invalidate_live_intervals();
563 vec4_visitor::split_uniform_registers()
565 /* Prior to this, uniforms have been in an array sized according to
566 * the number of vector uniforms present, sparsely filled (so an
567 * aggregate results in reg indices being skipped over). Now we're
568 * going to cut those aggregates up so each .reg index is one
569 * vector. The goal is to make elimination of unused uniform
570 * components easier later.
572 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
573 for (int i
= 0 ; i
< 3; i
++) {
574 if (inst
->src
[i
].file
!= UNIFORM
)
577 assert(!inst
->src
[i
].reladdr
);
579 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
580 inst
->src
[i
].reg_offset
= 0;
584 /* Update that everything is now vector-sized. */
585 for (int i
= 0; i
< this->uniforms
; i
++) {
586 this->uniform_size
[i
] = 1;
591 vec4_visitor::pack_uniform_registers()
593 bool uniform_used
[this->uniforms
];
594 int new_loc
[this->uniforms
];
595 int new_chan
[this->uniforms
];
597 memset(uniform_used
, 0, sizeof(uniform_used
));
598 memset(new_loc
, 0, sizeof(new_loc
));
599 memset(new_chan
, 0, sizeof(new_chan
));
601 /* Find which uniform vectors are actually used by the program. We
602 * expect unused vector elements when we've moved array access out
603 * to pull constants, and from some GLSL code generators like wine.
605 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
606 for (int i
= 0 ; i
< 3; i
++) {
607 if (inst
->src
[i
].file
!= UNIFORM
)
610 uniform_used
[inst
->src
[i
].reg
] = true;
614 int new_uniform_count
= 0;
616 /* Now, figure out a packing of the live uniform vectors into our
619 for (int src
= 0; src
< uniforms
; src
++) {
620 assert(src
< uniform_array_size
);
621 int size
= this->uniform_vector_size
[src
];
623 if (!uniform_used
[src
]) {
624 this->uniform_vector_size
[src
] = 0;
629 /* Find the lowest place we can slot this uniform in. */
630 for (dst
= 0; dst
< src
; dst
++) {
631 if (this->uniform_vector_size
[dst
] + size
<= 4)
640 new_chan
[src
] = this->uniform_vector_size
[dst
];
642 /* Move the references to the data */
643 for (int j
= 0; j
< size
; j
++) {
644 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
645 stage_prog_data
->param
[src
* 4 + j
];
648 this->uniform_vector_size
[dst
] += size
;
649 this->uniform_vector_size
[src
] = 0;
652 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
655 this->uniforms
= new_uniform_count
;
657 /* Now, update the instructions for our repacked uniforms. */
658 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
659 for (int i
= 0 ; i
< 3; i
++) {
660 int src
= inst
->src
[i
].reg
;
662 if (inst
->src
[i
].file
!= UNIFORM
)
665 inst
->src
[i
].reg
= new_loc
[src
];
667 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
668 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
669 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
670 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
671 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
677 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
679 * While GLSL IR also performs this optimization, we end up with it in
680 * our instruction stream for a couple of reasons. One is that we
681 * sometimes generate silly instructions, for example in array access
682 * where we'll generate "ADD offset, index, base" even if base is 0.
683 * The other is that GLSL IR's constant propagation doesn't track the
684 * components of aggregates, so some VS patterns (initialize matrix to
685 * 0, accumulate in vertex blending factors) end up breaking down to
686 * instructions involving 0.
689 vec4_visitor::opt_algebraic()
691 bool progress
= false;
693 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
694 switch (inst
->opcode
) {
696 if (inst
->src
[1].is_zero()) {
697 inst
->opcode
= BRW_OPCODE_MOV
;
698 inst
->src
[1] = src_reg();
704 if (inst
->src
[1].is_zero()) {
705 inst
->opcode
= BRW_OPCODE_MOV
;
706 switch (inst
->src
[0].type
) {
707 case BRW_REGISTER_TYPE_F
:
708 inst
->src
[0] = src_reg(0.0f
);
710 case BRW_REGISTER_TYPE_D
:
711 inst
->src
[0] = src_reg(0);
713 case BRW_REGISTER_TYPE_UD
:
714 inst
->src
[0] = src_reg(0u);
717 unreachable("not reached");
719 inst
->src
[1] = src_reg();
721 } else if (inst
->src
[1].is_one()) {
722 inst
->opcode
= BRW_OPCODE_MOV
;
723 inst
->src
[1] = src_reg();
733 invalidate_live_intervals();
739 * Only a limited number of hardware registers may be used for push
740 * constants, so this turns access to the overflowed constants into
744 vec4_visitor::move_push_constants_to_pull_constants()
746 int pull_constant_loc
[this->uniforms
];
748 /* Only allow 32 registers (256 uniform components) as push constants,
749 * which is the limit on gen6.
751 * If changing this value, note the limitation about total_regs in
754 int max_uniform_components
= 32 * 8;
755 if (this->uniforms
* 4 <= max_uniform_components
)
758 /* Make some sort of choice as to which uniforms get sent to pull
759 * constants. We could potentially do something clever here like
760 * look for the most infrequently used uniform vec4s, but leave
763 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
764 pull_constant_loc
[i
/ 4] = -1;
766 if (i
>= max_uniform_components
) {
767 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
769 /* Try to find an existing copy of this uniform in the pull
770 * constants if it was part of an array access already.
772 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
775 for (matches
= 0; matches
< 4; matches
++) {
776 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
781 pull_constant_loc
[i
/ 4] = j
/ 4;
786 if (pull_constant_loc
[i
/ 4] == -1) {
787 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
788 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
790 for (int j
= 0; j
< 4; j
++) {
791 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
798 /* Now actually rewrite usage of the things we've moved to pull
801 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
802 for (int i
= 0 ; i
< 3; i
++) {
803 if (inst
->src
[i
].file
!= UNIFORM
||
804 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
807 int uniform
= inst
->src
[i
].reg
;
809 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
811 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
812 pull_constant_loc
[uniform
]);
814 inst
->src
[i
].file
= temp
.file
;
815 inst
->src
[i
].reg
= temp
.reg
;
816 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
817 inst
->src
[i
].reladdr
= NULL
;
821 /* Repack push constants to remove the now-unused ones. */
822 pack_uniform_registers();
826 * Sets the dependency control fields on instructions after register
827 * allocation and before the generator is run.
829 * When you have a sequence of instructions like:
831 * DP4 temp.x vertex uniform[0]
832 * DP4 temp.y vertex uniform[0]
833 * DP4 temp.z vertex uniform[0]
834 * DP4 temp.w vertex uniform[0]
836 * The hardware doesn't know that it can actually run the later instructions
837 * while the previous ones are in flight, producing stalls. However, we have
838 * manual fields we can set in the instructions that let it do so.
841 vec4_visitor::opt_set_dependency_control()
843 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
844 uint8_t grf_channels_written
[BRW_MAX_GRF
];
845 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
846 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
850 assert(prog_data
->total_grf
||
851 !"Must be called after register allocation");
853 foreach_block (block
, cfg
) {
854 memset(last_grf_write
, 0, sizeof(last_grf_write
));
855 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
857 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
858 /* If we read from a register that we were doing dependency control
859 * on, don't do dependency control across the read.
861 for (int i
= 0; i
< 3; i
++) {
862 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
863 if (inst
->src
[i
].file
== GRF
) {
864 last_grf_write
[reg
] = NULL
;
865 } else if (inst
->src
[i
].file
== HW_REG
) {
866 memset(last_grf_write
, 0, sizeof(last_grf_write
));
869 assert(inst
->src
[i
].file
!= MRF
);
872 /* In the presence of send messages, totally interrupt dependency
873 * control. They're long enough that the chance of dependency
874 * control around them just doesn't matter.
877 memset(last_grf_write
, 0, sizeof(last_grf_write
));
878 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
882 /* It looks like setting dependency control on a predicated
883 * instruction hangs the GPU.
885 if (inst
->predicate
) {
886 memset(last_grf_write
, 0, sizeof(last_grf_write
));
887 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
891 /* Dependency control does not work well over math instructions.
893 if (inst
->is_math()) {
894 memset(last_grf_write
, 0, sizeof(last_grf_write
));
895 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
899 /* Now, see if we can do dependency control for this instruction
900 * against a previous one writing to its destination.
902 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
903 if (inst
->dst
.file
== GRF
) {
904 if (last_grf_write
[reg
] &&
905 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
906 last_grf_write
[reg
]->no_dd_clear
= true;
907 inst
->no_dd_check
= true;
909 grf_channels_written
[reg
] = 0;
912 last_grf_write
[reg
] = inst
;
913 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
914 } else if (inst
->dst
.file
== MRF
) {
915 if (last_mrf_write
[reg
] &&
916 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
917 last_mrf_write
[reg
]->no_dd_clear
= true;
918 inst
->no_dd_check
= true;
920 mrf_channels_written
[reg
] = 0;
923 last_mrf_write
[reg
] = inst
;
924 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
925 } else if (inst
->dst
.reg
== HW_REG
) {
926 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
927 memset(last_grf_write
, 0, sizeof(last_grf_write
));
928 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
929 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
936 vec4_instruction::can_reswizzle(int dst_writemask
,
940 /* If this instruction sets anything not referenced by swizzle, then we'd
941 * totally break it when we reswizzle.
943 if (dst
.writemask
& ~swizzle_mask
)
953 * For any channels in the swizzle's source that were populated by this
954 * instruction, rewrite the instruction to put the appropriate result directly
957 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
960 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
962 int new_writemask
= 0;
963 int new_swizzle
[4] = { 0 };
965 /* Dot product instructions write a single result into all channels. */
966 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
967 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
) {
968 for (int i
= 0; i
< 3; i
++) {
969 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
972 for (int c
= 0; c
< 4; c
++) {
973 new_swizzle
[c
] = BRW_GET_SWZ(src
[i
].swizzle
, BRW_GET_SWZ(swizzle
, c
));
976 src
[i
].swizzle
= BRW_SWIZZLE4(new_swizzle
[0], new_swizzle
[1],
977 new_swizzle
[2], new_swizzle
[3]);
981 for (int c
= 0; c
< 4; c
++) {
982 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
983 /* Skip components of the swizzle not used by the dst. */
984 if (!(dst_writemask
& (1 << c
)))
986 /* If we were populating this component, then populate the
987 * corresponding channel of the new dst.
989 if (dst
.writemask
& bit
)
990 new_writemask
|= (1 << c
);
992 dst
.writemask
= new_writemask
;
996 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
997 * just written and then MOVed into another reg and making the original write
998 * of the GRF write directly to the final destination instead.
1001 vec4_visitor::opt_register_coalesce()
1003 bool progress
= false;
1006 calculate_live_intervals();
1008 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1012 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1013 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1015 inst
->src
[0].file
!= GRF
||
1016 inst
->dst
.type
!= inst
->src
[0].type
||
1017 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1020 bool to_mrf
= (inst
->dst
.file
== MRF
);
1022 /* Can't coalesce this GRF if someone else was going to
1025 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
1026 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
1027 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
1028 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
1031 /* We need to check interference with the final destination between this
1032 * instruction and the earliest instruction involved in writing the GRF
1033 * we're eliminating. To do that, keep track of which of our source
1034 * channels we've seen initialized.
1036 bool chans_needed
[4] = {false, false, false, false};
1037 int chans_remaining
= 0;
1038 int swizzle_mask
= 0;
1039 for (int i
= 0; i
< 4; i
++) {
1040 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
1042 if (!(inst
->dst
.writemask
& (1 << i
)))
1045 swizzle_mask
|= (1 << chan
);
1047 if (!chans_needed
[chan
]) {
1048 chans_needed
[chan
] = true;
1053 /* Now walk up the instruction stream trying to see if we can rewrite
1054 * everything writing to the temporary to write into the destination
1057 vec4_instruction
*scan_inst
;
1058 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
1059 scan_inst
->prev
!= NULL
;
1060 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
1061 if (scan_inst
->dst
.file
== GRF
&&
1062 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1063 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1064 /* Found something writing to the reg we want to coalesce away. */
1066 /* SEND instructions can't have MRF as a destination. */
1067 if (scan_inst
->mlen
)
1070 if (brw
->gen
== 6) {
1071 /* gen6 math instructions must have the destination be
1072 * GRF, so no compute-to-MRF for them.
1074 if (scan_inst
->is_math()) {
1080 /* If we can't handle the swizzle, bail. */
1081 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1082 inst
->src
[0].swizzle
,
1087 /* Mark which channels we found unconditional writes for. */
1088 if (!scan_inst
->predicate
) {
1089 for (int i
= 0; i
< 4; i
++) {
1090 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1092 chans_needed
[i
] = false;
1098 if (chans_remaining
== 0)
1102 /* We don't handle flow control here. Most computation of values
1103 * that could be coalesced happens just before their use.
1105 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1106 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1107 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1108 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1112 /* You can't read from an MRF, so if someone else reads our MRF's
1113 * source GRF that we wanted to rewrite, that stops us. If it's a
1114 * GRF we're trying to coalesce to, we don't actually handle
1115 * rewriting sources so bail in that case as well.
1117 bool interfered
= false;
1118 for (int i
= 0; i
< 3; i
++) {
1119 if (scan_inst
->src
[i
].file
== GRF
&&
1120 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1121 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1128 /* If somebody else writes our destination here, we can't coalesce
1131 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1132 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1136 /* Check for reads of the register we're trying to coalesce into. We
1137 * can't go rewriting instructions above that to put some other value
1138 * in the register instead.
1140 if (to_mrf
&& scan_inst
->mlen
> 0) {
1141 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1142 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1146 for (int i
= 0; i
< 3; i
++) {
1147 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1148 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1149 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1158 if (chans_remaining
== 0) {
1159 /* If we've made it here, we have an MOV we want to coalesce out, and
1160 * a scan_inst pointing to the earliest instruction involved in
1161 * computing the value. Now go rewrite the instruction stream
1165 while (scan_inst
!= inst
) {
1166 if (scan_inst
->dst
.file
== GRF
&&
1167 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1168 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1169 scan_inst
->reswizzle(inst
->dst
.writemask
,
1170 inst
->src
[0].swizzle
);
1171 scan_inst
->dst
.file
= inst
->dst
.file
;
1172 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1173 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1174 scan_inst
->saturate
|= inst
->saturate
;
1176 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1178 inst
->remove(block
);
1184 invalidate_live_intervals(false);
1190 * Splits virtual GRFs requesting more than one contiguous physical register.
1192 * We initially create large virtual GRFs for temporary structures, arrays,
1193 * and matrices, so that the dereference visitor functions can add reg_offsets
1194 * to work their way down to the actual member being accessed. But when it
1195 * comes to optimization, we'd like to treat each register as individual
1196 * storage if possible.
1198 * So far, the only thing that might prevent splitting is a send message from
1202 vec4_visitor::split_virtual_grfs()
1204 int num_vars
= this->virtual_grf_count
;
1205 int new_virtual_grf
[num_vars
];
1206 bool split_grf
[num_vars
];
1208 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1210 /* Try to split anything > 0 sized. */
1211 for (int i
= 0; i
< num_vars
; i
++) {
1212 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1215 /* Check that the instructions are compatible with the registers we're trying
1218 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1219 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1222 if (inst
->is_send_from_grf()) {
1223 for (int i
= 0; i
< 3; i
++) {
1224 if (inst
->src
[i
].file
== GRF
) {
1225 split_grf
[inst
->src
[i
].reg
] = false;
1231 /* Allocate new space for split regs. Note that the virtual
1232 * numbers will be contiguous.
1234 for (int i
= 0; i
< num_vars
; i
++) {
1238 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1239 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1240 int reg
= virtual_grf_alloc(1);
1241 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1244 this->virtual_grf_sizes
[i
] = 1;
1247 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1248 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1249 inst
->dst
.reg_offset
!= 0) {
1250 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1251 inst
->dst
.reg_offset
- 1);
1252 inst
->dst
.reg_offset
= 0;
1254 for (int i
= 0; i
< 3; i
++) {
1255 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1256 inst
->src
[i
].reg_offset
!= 0) {
1257 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1258 inst
->src
[i
].reg_offset
- 1);
1259 inst
->src
[i
].reg_offset
= 0;
1263 invalidate_live_intervals(false);
1267 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1269 dump_instruction(be_inst
, stderr
);
1273 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1275 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1277 if (inst
->predicate
) {
1278 fprintf(file
, "(%cf0) ",
1279 inst
->predicate_inverse
? '-' : '+');
1282 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1283 if (inst
->conditional_mod
) {
1284 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1288 switch (inst
->dst
.file
) {
1290 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1293 fprintf(file
, "m%d", inst
->dst
.reg
);
1296 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1297 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1299 fprintf(file
, "null");
1301 case BRW_ARF_ADDRESS
:
1302 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1304 case BRW_ARF_ACCUMULATOR
:
1305 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1308 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1309 inst
->dst
.fixed_hw_reg
.subnr
);
1312 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1313 inst
->dst
.fixed_hw_reg
.subnr
);
1317 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1319 if (inst
->dst
.fixed_hw_reg
.subnr
)
1320 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1323 fprintf(file
, "(null)");
1326 fprintf(file
, "???");
1329 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1331 if (inst
->dst
.writemask
& 1)
1333 if (inst
->dst
.writemask
& 2)
1335 if (inst
->dst
.writemask
& 4)
1337 if (inst
->dst
.writemask
& 8)
1340 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
1342 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1343 if (inst
->src
[i
].negate
)
1345 if (inst
->src
[i
].abs
)
1347 switch (inst
->src
[i
].file
) {
1349 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1352 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1355 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1358 switch (inst
->src
[i
].type
) {
1359 case BRW_REGISTER_TYPE_F
:
1360 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1362 case BRW_REGISTER_TYPE_D
:
1363 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1365 case BRW_REGISTER_TYPE_UD
:
1366 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1369 fprintf(file
, "???");
1374 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1376 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1378 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1379 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1381 fprintf(file
, "null");
1383 case BRW_ARF_ADDRESS
:
1384 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1386 case BRW_ARF_ACCUMULATOR
:
1387 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1390 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1391 inst
->src
[i
].fixed_hw_reg
.subnr
);
1394 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1395 inst
->src
[i
].fixed_hw_reg
.subnr
);
1399 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1401 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1402 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1403 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1407 fprintf(file
, "(null)");
1410 fprintf(file
, "???");
1414 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1415 if (inst
->src
[i
].reg_offset
!= 0 &&
1416 inst
->src
[i
].file
== GRF
&&
1417 virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1418 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1420 if (inst
->src
[i
].file
!= IMM
) {
1421 static const char *chans
[4] = {"x", "y", "z", "w"};
1423 for (int c
= 0; c
< 4; c
++) {
1424 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1428 if (inst
->src
[i
].abs
)
1431 if (inst
->src
[i
].file
!= IMM
) {
1432 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1435 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1436 fprintf(file
, ", ");
1439 fprintf(file
, "\n");
1443 static inline struct brw_reg
1444 attribute_to_hw_reg(int attr
, bool interleaved
)
1447 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1449 return brw_vec8_grf(attr
, 0);
1454 * Replace each register of type ATTR in this->instructions with a reference
1455 * to a fixed HW register.
1457 * If interleaved is true, then each attribute takes up half a register, with
1458 * register N containing attribute 2*N in its first half and attribute 2*N+1
1459 * in its second half (this corresponds to the payload setup used by geometry
1460 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1461 * false, then each attribute takes up a whole register, with register N
1462 * containing attribute N (this corresponds to the payload setup used by
1463 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1466 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1469 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
1470 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1471 if (inst
->dst
.file
== ATTR
) {
1472 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1474 /* All attributes used in the shader need to have been assigned a
1475 * hardware register by the caller
1479 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1480 reg
.type
= inst
->dst
.type
;
1481 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1483 inst
->dst
.file
= HW_REG
;
1484 inst
->dst
.fixed_hw_reg
= reg
;
1487 for (int i
= 0; i
< 3; i
++) {
1488 if (inst
->src
[i
].file
!= ATTR
)
1491 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1493 /* All attributes used in the shader need to have been assigned a
1494 * hardware register by the caller
1498 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1499 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1500 reg
.type
= inst
->src
[i
].type
;
1501 if (inst
->src
[i
].abs
)
1503 if (inst
->src
[i
].negate
)
1506 inst
->src
[i
].file
= HW_REG
;
1507 inst
->src
[i
].fixed_hw_reg
= reg
;
1513 vec4_vs_visitor::setup_attributes(int payload_reg
)
1516 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1517 memset(attribute_map
, 0, sizeof(attribute_map
));
1520 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1521 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1522 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1527 /* VertexID is stored by the VF as the last vertex element, but we
1528 * don't represent it with a flag in inputs_read, so we call it
1531 if (vs_prog_data
->uses_vertexid
) {
1532 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1536 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1538 /* The BSpec says we always have to read at least one thing from
1539 * the VF, and it appears that the hardware wedges otherwise.
1541 if (nr_attributes
== 0)
1544 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1546 unsigned vue_entries
=
1547 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1550 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1552 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1554 return payload_reg
+ nr_attributes
;
1558 vec4_visitor::setup_uniforms(int reg
)
1560 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1562 /* The pre-gen6 VS requires that some push constants get loaded no
1563 * matter what, or the GPU would hang.
1565 if (brw
->gen
< 6 && this->uniforms
== 0) {
1566 assert(this->uniforms
< this->uniform_array_size
);
1567 this->uniform_vector_size
[this->uniforms
] = 1;
1569 stage_prog_data
->param
=
1570 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1571 for (unsigned int i
= 0; i
< 4; i
++) {
1572 unsigned int slot
= this->uniforms
* 4 + i
;
1573 static gl_constant_value zero
= { 0.0 };
1574 stage_prog_data
->param
[slot
] = &zero
;
1580 reg
+= ALIGN(uniforms
, 2) / 2;
1583 stage_prog_data
->nr_params
= this->uniforms
* 4;
1585 prog_data
->base
.curb_read_length
=
1586 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1592 vec4_vs_visitor::setup_payload(void)
1596 /* The payload always contains important data in g0, which contains
1597 * the URB handles that are passed on to the URB write at the end
1598 * of the thread. So, we always start push constants at g1.
1602 reg
= setup_uniforms(reg
);
1604 reg
= setup_attributes(reg
);
1606 this->first_non_payload_grf
= reg
;
1610 vec4_visitor::get_timestamp()
1612 assert(brw
->gen
>= 7);
1614 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1617 BRW_REGISTER_TYPE_UD
,
1618 BRW_VERTICAL_STRIDE_0
,
1620 BRW_HORIZONTAL_STRIDE_4
,
1624 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1626 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1627 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1628 * even if it's not enabled in the dispatch.
1630 mov
->force_writemask_all
= true;
1632 return src_reg(dst
);
1636 vec4_visitor::emit_shader_time_begin()
1638 current_annotation
= "shader time start";
1639 shader_start_time
= get_timestamp();
1643 vec4_visitor::emit_shader_time_end()
1645 current_annotation
= "shader time end";
1646 src_reg shader_end_time
= get_timestamp();
1649 /* Check that there weren't any timestamp reset events (assuming these
1650 * were the only two timestamp reads that happened).
1652 src_reg reset_end
= shader_end_time
;
1653 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1654 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1655 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1657 emit(IF(BRW_PREDICATE_NORMAL
));
1659 /* Take the current timestamp and get the delta. */
1660 shader_start_time
.negate
= true;
1661 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1662 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1664 /* If there were no instructions between the two timestamp gets, the diff
1665 * is 2 cycles. Remove that overhead, so I can forget about that when
1666 * trying to determine the time taken for single instructions.
1668 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1670 emit_shader_time_write(st_base
, src_reg(diff
));
1671 emit_shader_time_write(st_written
, src_reg(1u));
1672 emit(BRW_OPCODE_ELSE
);
1673 emit_shader_time_write(st_reset
, src_reg(1u));
1674 emit(BRW_OPCODE_ENDIF
);
1678 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1681 int shader_time_index
=
1682 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1685 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1687 dst_reg offset
= dst
;
1691 offset
.type
= BRW_REGISTER_TYPE_UD
;
1692 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1694 time
.type
= BRW_REGISTER_TYPE_UD
;
1695 emit(MOV(time
, src_reg(value
)));
1697 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1703 sanity_param_count
= prog
->Parameters
->NumParameters
;
1705 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1706 emit_shader_time_begin();
1708 assign_common_binding_table_offsets(0);
1712 /* Generate VS IR for main(). (the visitor only descends into
1713 * functions called "main").
1716 visit_instructions(shader
->base
.ir
);
1718 emit_program_code();
1722 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1723 setup_uniform_clipplane_values();
1727 /* Before any optimization, push array accesses out to scratch
1728 * space where we need them to be. This pass may allocate new
1729 * virtual GRFs, so we want to do it early. It also makes sure
1730 * that we have reladdr computations available for CSE, since we'll
1731 * often do repeated subexpressions for those.
1734 move_grf_array_access_to_scratch();
1735 move_uniform_array_access_to_pull_constants();
1737 /* The ARB_vertex_program frontend emits pull constant loads directly
1738 * rather than using reladdr, so we don't need to walk through all the
1739 * instructions looking for things to move. There isn't anything.
1741 * We do still need to split things to vec4 size.
1743 split_uniform_registers();
1745 pack_uniform_registers();
1746 move_push_constants_to_pull_constants();
1747 split_virtual_grfs();
1749 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1751 #define OPT(pass, args...) do { \
1753 bool this_progress = pass(args); \
1755 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1756 char filename[64]; \
1757 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1758 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1760 backend_visitor::dump_instructions(filename); \
1763 progress = progress || this_progress; \
1767 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1769 snprintf(filename
, 64, "%s-%04d-00-start",
1770 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1772 backend_visitor::dump_instructions(filename
);
1782 OPT(opt_reduce_swizzle
);
1783 OPT(dead_code_eliminate
);
1784 OPT(dead_control_flow_eliminate
, this);
1785 OPT(opt_copy_propagation
);
1788 OPT(opt_register_coalesce
);
1798 /* Debug of register spilling: Go spill everything. */
1799 const int grf_count
= virtual_grf_count
;
1800 float spill_costs
[virtual_grf_count
];
1801 bool no_spill
[virtual_grf_count
];
1802 evaluate_spill_costs(spill_costs
, no_spill
);
1803 for (int i
= 0; i
< grf_count
; i
++) {
1810 while (!reg_allocate()) {
1815 opt_schedule_instructions();
1817 opt_set_dependency_control();
1819 /* If any state parameters were appended, then ParameterValues could have
1820 * been realloced, in which case the driver uniform storage set up by
1821 * _mesa_associate_uniform_storage() would point to freed memory. Make
1822 * sure that didn't happen.
1824 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1831 } /* namespace brw */
1836 * Compile a vertex shader.
1838 * Returns the final assembly and the program's size.
1841 brw_vs_emit(struct brw_context
*brw
,
1842 struct gl_shader_program
*prog
,
1843 struct brw_vs_compile
*c
,
1844 struct brw_vs_prog_data
*prog_data
,
1846 unsigned *final_assembly_size
)
1848 bool start_busy
= false;
1849 double start_time
= 0;
1851 if (unlikely(brw
->perf_debug
)) {
1852 start_busy
= (brw
->batch
.last_bo
&&
1853 drm_intel_bo_busy(brw
->batch
.last_bo
));
1854 start_time
= get_time();
1857 struct brw_shader
*shader
= NULL
;
1859 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1861 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1862 brw_dump_ir(brw
, "vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1864 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1867 prog
->LinkStatus
= false;
1868 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1871 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1877 const unsigned *assembly
= NULL
;
1878 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1879 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1880 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1882 if (unlikely(brw
->perf_debug
) && shader
) {
1883 if (shader
->compiled_once
) {
1884 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1886 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1887 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1888 (get_time() - start_time
) * 1000);
1890 shader
->compiled_once
= true;
1898 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1899 struct brw_vec4_prog_key
*key
,
1900 GLuint id
, struct gl_program
*prog
)
1902 key
->program_string_id
= id
;
1903 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1905 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1906 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1907 if (prog
->ShadowSamplers
& (1 << i
)) {
1908 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1909 key
->tex
.swizzles
[i
] =
1910 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1912 /* Color sampler: assume no swizzling. */
1913 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;