2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
38 #include "main/context.h"
40 #define MAX_INSTRUCTION (1 << 30)
49 memset(this, 0, sizeof(*this));
51 this->file
= BAD_FILE
;
54 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
60 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
61 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
63 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 this->type
= brw_type_for_base_type(type
);
68 /** Generic unset register constructor. */
74 src_reg::src_reg(float f
)
79 this->type
= BRW_REGISTER_TYPE_F
;
80 this->fixed_hw_reg
.dw1
.f
= f
;
83 src_reg::src_reg(uint32_t u
)
88 this->type
= BRW_REGISTER_TYPE_UD
;
89 this->fixed_hw_reg
.dw1
.ud
= u
;
92 src_reg::src_reg(int32_t i
)
97 this->type
= BRW_REGISTER_TYPE_D
;
98 this->fixed_hw_reg
.dw1
.d
= i
;
101 src_reg::src_reg(uint8_t vf
[4])
106 this->type
= BRW_REGISTER_TYPE_VF
;
107 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
110 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
115 this->type
= BRW_REGISTER_TYPE_VF
;
116 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
122 src_reg::src_reg(struct brw_reg reg
)
127 this->fixed_hw_reg
= reg
;
128 this->type
= reg
.type
;
131 src_reg::src_reg(const dst_reg
®
)
135 this->file
= reg
.file
;
137 this->reg_offset
= reg
.reg_offset
;
138 this->type
= reg
.type
;
139 this->reladdr
= reg
.reladdr
;
140 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
141 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(register_file file
, int reg
, brw_reg_type type
,
184 this->writemask
= writemask
;
187 dst_reg::dst_reg(struct brw_reg reg
)
192 this->fixed_hw_reg
= reg
;
193 this->type
= reg
.type
;
196 dst_reg::dst_reg(const src_reg
®
)
200 this->file
= reg
.file
;
202 this->reg_offset
= reg
.reg_offset
;
203 this->type
= reg
.type
;
204 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
205 this->reladdr
= reg
.reladdr
;
206 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
210 dst_reg::equals(const dst_reg
&r
) const
212 return (file
== r
.file
&&
214 reg_offset
== r
.reg_offset
&&
216 negate
== r
.negate
&&
218 writemask
== r
.writemask
&&
219 (reladdr
== r
.reladdr
||
220 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
221 ((file
!= HW_REG
&& file
!= IMM
) ||
222 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
223 sizeof(fixed_hw_reg
)) == 0));
227 vec4_instruction::is_send_from_grf()
230 case SHADER_OPCODE_SHADER_TIME_ADD
:
231 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
232 case SHADER_OPCODE_UNTYPED_ATOMIC
:
233 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
234 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
235 case SHADER_OPCODE_TYPED_ATOMIC
:
236 case SHADER_OPCODE_TYPED_SURFACE_READ
:
237 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
245 vec4_instruction::regs_read(unsigned arg
) const
247 if (src
[arg
].file
== BAD_FILE
)
251 case SHADER_OPCODE_SHADER_TIME_ADD
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 return arg
== 0 ? mlen
: 1;
260 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
261 return arg
== 1 ? mlen
: 1;
269 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
271 if (devinfo
->gen
== 6 && is_math())
274 if (is_send_from_grf())
277 if (!backend_instruction::can_do_source_mods())
284 * Returns how many MRFs an opcode will write over.
286 * Note that this is not the 0 or 1 implied writes in an actual gen
287 * instruction -- the generate_* functions generate additional MOVs
291 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
293 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
296 switch (inst
->opcode
) {
297 case SHADER_OPCODE_RCP
:
298 case SHADER_OPCODE_RSQ
:
299 case SHADER_OPCODE_SQRT
:
300 case SHADER_OPCODE_EXP2
:
301 case SHADER_OPCODE_LOG2
:
302 case SHADER_OPCODE_SIN
:
303 case SHADER_OPCODE_COS
:
305 case SHADER_OPCODE_INT_QUOTIENT
:
306 case SHADER_OPCODE_INT_REMAINDER
:
307 case SHADER_OPCODE_POW
:
309 case VS_OPCODE_URB_WRITE
:
311 case VS_OPCODE_PULL_CONSTANT_LOAD
:
313 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
315 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
317 case GS_OPCODE_URB_WRITE
:
318 case GS_OPCODE_URB_WRITE_ALLOCATE
:
319 case GS_OPCODE_THREAD_END
:
321 case GS_OPCODE_FF_SYNC
:
323 case SHADER_OPCODE_SHADER_TIME_ADD
:
325 case SHADER_OPCODE_TEX
:
326 case SHADER_OPCODE_TXL
:
327 case SHADER_OPCODE_TXD
:
328 case SHADER_OPCODE_TXF
:
329 case SHADER_OPCODE_TXF_CMS
:
330 case SHADER_OPCODE_TXF_MCS
:
331 case SHADER_OPCODE_TXS
:
332 case SHADER_OPCODE_TG4
:
333 case SHADER_OPCODE_TG4_OFFSET
:
334 case SHADER_OPCODE_SAMPLEINFO
:
335 return inst
->header_size
;
337 unreachable("not reached");
342 src_reg::equals(const src_reg
&r
) const
344 return (file
== r
.file
&&
346 reg_offset
== r
.reg_offset
&&
348 negate
== r
.negate
&&
350 swizzle
== r
.swizzle
&&
351 !reladdr
&& !r
.reladdr
&&
352 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
353 sizeof(fixed_hw_reg
)) == 0);
357 vec4_visitor::opt_vector_float()
359 bool progress
= false;
361 int last_reg
= -1, last_reg_offset
= -1;
362 enum register_file last_reg_file
= BAD_FILE
;
364 int remaining_channels
= 0;
367 vec4_instruction
*imm_inst
[4];
369 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
370 if (last_reg
!= inst
->dst
.reg
||
371 last_reg_offset
!= inst
->dst
.reg_offset
||
372 last_reg_file
!= inst
->dst
.file
) {
373 last_reg
= inst
->dst
.reg
;
374 last_reg_offset
= inst
->dst
.reg_offset
;
375 last_reg_file
= inst
->dst
.file
;
376 remaining_channels
= WRITEMASK_XYZW
;
381 if (inst
->opcode
!= BRW_OPCODE_MOV
||
382 inst
->dst
.writemask
== WRITEMASK_XYZW
||
383 inst
->src
[0].file
!= IMM
)
386 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
390 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
392 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
394 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
396 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
399 imm_inst
[inst_count
++] = inst
;
401 remaining_channels
&= ~inst
->dst
.writemask
;
402 if (remaining_channels
== 0) {
403 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
404 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
405 mov
->dst
.writemask
= WRITEMASK_XYZW
;
406 inst
->insert_after(block
, mov
);
409 for (int i
= 0; i
< inst_count
; i
++) {
410 imm_inst
[i
]->remove(block
);
417 invalidate_live_intervals();
422 /* Replaces unused channels of a swizzle with channels that are used.
424 * For instance, this pass transforms
426 * mov vgrf4.yz, vgrf5.wxzy
430 * mov vgrf4.yz, vgrf5.xxzx
432 * This eliminates false uses of some channels, letting dead code elimination
433 * remove the instructions that wrote them.
436 vec4_visitor::opt_reduce_swizzle()
438 bool progress
= false;
440 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
441 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
442 inst
->is_send_from_grf())
447 /* Determine which channels of the sources are read. */
448 switch (inst
->opcode
) {
449 case VEC4_OPCODE_PACK_BYTES
:
451 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
452 * but all four of src1.
454 swizzle
= brw_swizzle_for_size(4);
457 swizzle
= brw_swizzle_for_size(3);
460 swizzle
= brw_swizzle_for_size(2);
463 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
467 /* Update sources' swizzles. */
468 for (int i
= 0; i
< 3; i
++) {
469 if (inst
->src
[i
].file
!= GRF
&&
470 inst
->src
[i
].file
!= ATTR
&&
471 inst
->src
[i
].file
!= UNIFORM
)
474 const unsigned new_swizzle
=
475 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
476 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
477 inst
->src
[i
].swizzle
= new_swizzle
;
484 invalidate_live_intervals();
490 vec4_visitor::split_uniform_registers()
492 /* Prior to this, uniforms have been in an array sized according to
493 * the number of vector uniforms present, sparsely filled (so an
494 * aggregate results in reg indices being skipped over). Now we're
495 * going to cut those aggregates up so each .reg index is one
496 * vector. The goal is to make elimination of unused uniform
497 * components easier later.
499 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
500 for (int i
= 0 ; i
< 3; i
++) {
501 if (inst
->src
[i
].file
!= UNIFORM
)
504 assert(!inst
->src
[i
].reladdr
);
506 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
507 inst
->src
[i
].reg_offset
= 0;
511 /* Update that everything is now vector-sized. */
512 for (int i
= 0; i
< this->uniforms
; i
++) {
513 this->uniform_size
[i
] = 1;
518 vec4_visitor::pack_uniform_registers()
520 bool uniform_used
[this->uniforms
];
521 int new_loc
[this->uniforms
];
522 int new_chan
[this->uniforms
];
524 memset(uniform_used
, 0, sizeof(uniform_used
));
525 memset(new_loc
, 0, sizeof(new_loc
));
526 memset(new_chan
, 0, sizeof(new_chan
));
528 /* Find which uniform vectors are actually used by the program. We
529 * expect unused vector elements when we've moved array access out
530 * to pull constants, and from some GLSL code generators like wine.
532 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
533 for (int i
= 0 ; i
< 3; i
++) {
534 if (inst
->src
[i
].file
!= UNIFORM
)
537 uniform_used
[inst
->src
[i
].reg
] = true;
541 int new_uniform_count
= 0;
543 /* Now, figure out a packing of the live uniform vectors into our
546 for (int src
= 0; src
< uniforms
; src
++) {
547 assert(src
< uniform_array_size
);
548 int size
= this->uniform_vector_size
[src
];
550 if (!uniform_used
[src
]) {
551 this->uniform_vector_size
[src
] = 0;
556 /* Find the lowest place we can slot this uniform in. */
557 for (dst
= 0; dst
< src
; dst
++) {
558 if (this->uniform_vector_size
[dst
] + size
<= 4)
567 new_chan
[src
] = this->uniform_vector_size
[dst
];
569 /* Move the references to the data */
570 for (int j
= 0; j
< size
; j
++) {
571 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
572 stage_prog_data
->param
[src
* 4 + j
];
575 this->uniform_vector_size
[dst
] += size
;
576 this->uniform_vector_size
[src
] = 0;
579 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
582 this->uniforms
= new_uniform_count
;
584 /* Now, update the instructions for our repacked uniforms. */
585 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
586 for (int i
= 0 ; i
< 3; i
++) {
587 int src
= inst
->src
[i
].reg
;
589 if (inst
->src
[i
].file
!= UNIFORM
)
592 inst
->src
[i
].reg
= new_loc
[src
];
593 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
594 new_chan
[src
], new_chan
[src
]);
600 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
602 * While GLSL IR also performs this optimization, we end up with it in
603 * our instruction stream for a couple of reasons. One is that we
604 * sometimes generate silly instructions, for example in array access
605 * where we'll generate "ADD offset, index, base" even if base is 0.
606 * The other is that GLSL IR's constant propagation doesn't track the
607 * components of aggregates, so some VS patterns (initialize matrix to
608 * 0, accumulate in vertex blending factors) end up breaking down to
609 * instructions involving 0.
612 vec4_visitor::opt_algebraic()
614 bool progress
= false;
616 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
617 switch (inst
->opcode
) {
619 if (inst
->src
[0].file
!= IMM
)
622 if (inst
->saturate
) {
623 if (inst
->dst
.type
!= inst
->src
[0].type
)
624 assert(!"unimplemented: saturate mixed types");
626 if (brw_saturate_immediate(inst
->dst
.type
,
627 &inst
->src
[0].fixed_hw_reg
)) {
628 inst
->saturate
= false;
634 case VEC4_OPCODE_UNPACK_UNIFORM
:
635 if (inst
->src
[0].file
!= UNIFORM
) {
636 inst
->opcode
= BRW_OPCODE_MOV
;
642 if (inst
->src
[1].is_zero()) {
643 inst
->opcode
= BRW_OPCODE_MOV
;
644 inst
->src
[1] = src_reg();
650 if (inst
->src
[1].is_zero()) {
651 inst
->opcode
= BRW_OPCODE_MOV
;
652 switch (inst
->src
[0].type
) {
653 case BRW_REGISTER_TYPE_F
:
654 inst
->src
[0] = src_reg(0.0f
);
656 case BRW_REGISTER_TYPE_D
:
657 inst
->src
[0] = src_reg(0);
659 case BRW_REGISTER_TYPE_UD
:
660 inst
->src
[0] = src_reg(0u);
663 unreachable("not reached");
665 inst
->src
[1] = src_reg();
667 } else if (inst
->src
[1].is_one()) {
668 inst
->opcode
= BRW_OPCODE_MOV
;
669 inst
->src
[1] = src_reg();
671 } else if (inst
->src
[1].is_negative_one()) {
672 inst
->opcode
= BRW_OPCODE_MOV
;
673 inst
->src
[0].negate
= !inst
->src
[0].negate
;
674 inst
->src
[1] = src_reg();
679 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
681 inst
->src
[0].negate
&&
682 inst
->src
[1].is_zero()) {
683 inst
->src
[0].abs
= false;
684 inst
->src
[0].negate
= false;
685 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
690 case SHADER_OPCODE_RCP
: {
691 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
692 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
693 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
694 inst
->opcode
= SHADER_OPCODE_RSQ
;
695 inst
->src
[0] = prev
->src
[0];
701 case SHADER_OPCODE_BROADCAST
:
702 if (is_uniform(inst
->src
[0]) ||
703 inst
->src
[1].is_zero()) {
704 inst
->opcode
= BRW_OPCODE_MOV
;
705 inst
->src
[1] = src_reg();
706 inst
->force_writemask_all
= true;
717 invalidate_live_intervals();
723 * Only a limited number of hardware registers may be used for push
724 * constants, so this turns access to the overflowed constants into
728 vec4_visitor::move_push_constants_to_pull_constants()
730 int pull_constant_loc
[this->uniforms
];
732 /* Only allow 32 registers (256 uniform components) as push constants,
733 * which is the limit on gen6.
735 * If changing this value, note the limitation about total_regs in
738 int max_uniform_components
= 32 * 8;
739 if (this->uniforms
* 4 <= max_uniform_components
)
742 /* Make some sort of choice as to which uniforms get sent to pull
743 * constants. We could potentially do something clever here like
744 * look for the most infrequently used uniform vec4s, but leave
747 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
748 pull_constant_loc
[i
/ 4] = -1;
750 if (i
>= max_uniform_components
) {
751 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
753 /* Try to find an existing copy of this uniform in the pull
754 * constants if it was part of an array access already.
756 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
759 for (matches
= 0; matches
< 4; matches
++) {
760 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
765 pull_constant_loc
[i
/ 4] = j
/ 4;
770 if (pull_constant_loc
[i
/ 4] == -1) {
771 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
772 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
774 for (int j
= 0; j
< 4; j
++) {
775 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
782 /* Now actually rewrite usage of the things we've moved to pull
785 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
786 for (int i
= 0 ; i
< 3; i
++) {
787 if (inst
->src
[i
].file
!= UNIFORM
||
788 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
791 int uniform
= inst
->src
[i
].reg
;
793 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
795 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
796 pull_constant_loc
[uniform
]);
798 inst
->src
[i
].file
= temp
.file
;
799 inst
->src
[i
].reg
= temp
.reg
;
800 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
801 inst
->src
[i
].reladdr
= NULL
;
805 /* Repack push constants to remove the now-unused ones. */
806 pack_uniform_registers();
809 /* Conditions for which we want to avoid setting the dependency control bits */
811 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
813 #define IS_DWORD(reg) \
814 (reg.type == BRW_REGISTER_TYPE_UD || \
815 reg.type == BRW_REGISTER_TYPE_D)
817 /* "When source or destination datatype is 64b or operation is integer DWord
818 * multiply, DepCtrl must not be used."
819 * May apply to future SoCs as well.
821 if (devinfo
->is_cherryview
) {
822 if (inst
->opcode
== BRW_OPCODE_MUL
&&
823 IS_DWORD(inst
->src
[0]) &&
824 IS_DWORD(inst
->src
[1]))
829 if (devinfo
->gen
>= 8) {
830 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
836 * In the presence of send messages, totally interrupt dependency
837 * control. They're long enough that the chance of dependency
838 * control around them just doesn't matter.
841 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
842 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
843 * completes the scoreboard clear must have a non-zero execution mask. This
844 * means, if any kind of predication can change the execution mask or channel
845 * enable of the last instruction, the optimization must be avoided. This is
846 * to avoid instructions being shot down the pipeline when no writes are
850 * Dependency control does not work well over math instructions.
851 * NB: Discovered empirically
853 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
857 * Sets the dependency control fields on instructions after register
858 * allocation and before the generator is run.
860 * When you have a sequence of instructions like:
862 * DP4 temp.x vertex uniform[0]
863 * DP4 temp.y vertex uniform[0]
864 * DP4 temp.z vertex uniform[0]
865 * DP4 temp.w vertex uniform[0]
867 * The hardware doesn't know that it can actually run the later instructions
868 * while the previous ones are in flight, producing stalls. However, we have
869 * manual fields we can set in the instructions that let it do so.
872 vec4_visitor::opt_set_dependency_control()
874 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
875 uint8_t grf_channels_written
[BRW_MAX_GRF
];
876 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
877 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
879 assert(prog_data
->total_grf
||
880 !"Must be called after register allocation");
882 foreach_block (block
, cfg
) {
883 memset(last_grf_write
, 0, sizeof(last_grf_write
));
884 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
886 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
887 /* If we read from a register that we were doing dependency control
888 * on, don't do dependency control across the read.
890 for (int i
= 0; i
< 3; i
++) {
891 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
892 if (inst
->src
[i
].file
== GRF
) {
893 last_grf_write
[reg
] = NULL
;
894 } else if (inst
->src
[i
].file
== HW_REG
) {
895 memset(last_grf_write
, 0, sizeof(last_grf_write
));
898 assert(inst
->src
[i
].file
!= MRF
);
901 if (is_dep_ctrl_unsafe(inst
)) {
902 memset(last_grf_write
, 0, sizeof(last_grf_write
));
903 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
907 /* Now, see if we can do dependency control for this instruction
908 * against a previous one writing to its destination.
910 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
911 if (inst
->dst
.file
== GRF
) {
912 if (last_grf_write
[reg
] &&
913 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
914 last_grf_write
[reg
]->no_dd_clear
= true;
915 inst
->no_dd_check
= true;
917 grf_channels_written
[reg
] = 0;
920 last_grf_write
[reg
] = inst
;
921 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
922 } else if (inst
->dst
.file
== MRF
) {
923 if (last_mrf_write
[reg
] &&
924 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
925 last_mrf_write
[reg
]->no_dd_clear
= true;
926 inst
->no_dd_check
= true;
928 mrf_channels_written
[reg
] = 0;
931 last_mrf_write
[reg
] = inst
;
932 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
933 } else if (inst
->dst
.reg
== HW_REG
) {
934 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
935 memset(last_grf_write
, 0, sizeof(last_grf_write
));
936 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
937 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
944 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
949 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
950 * or writemasking are not allowed.
952 if (devinfo
->gen
== 6 && is_math() &&
953 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
956 /* If this instruction sets anything not referenced by swizzle, then we'd
957 * totally break it when we reswizzle.
959 if (dst
.writemask
& ~swizzle_mask
)
965 /* We can't use swizzles on the accumulator and that's really the only
966 * HW_REG we would care to reswizzle so just disallow them all.
968 for (int i
= 0; i
< 3; i
++) {
969 if (src
[i
].file
== HW_REG
)
977 * For any channels in the swizzle's source that were populated by this
978 * instruction, rewrite the instruction to put the appropriate result directly
981 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
984 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
986 /* Destination write mask doesn't correspond to source swizzle for the dot
987 * product and pack_bytes instructions.
989 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
990 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
991 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
992 for (int i
= 0; i
< 3; i
++) {
993 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
996 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1000 /* Apply the specified swizzle and writemask to the original mask of
1001 * written components.
1003 dst
.writemask
= dst_writemask
&
1004 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1008 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1009 * just written and then MOVed into another reg and making the original write
1010 * of the GRF write directly to the final destination instead.
1013 vec4_visitor::opt_register_coalesce()
1015 bool progress
= false;
1018 calculate_live_intervals();
1020 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1024 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1025 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
1027 inst
->src
[0].file
!= GRF
||
1028 inst
->dst
.type
!= inst
->src
[0].type
||
1029 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1032 /* Remove no-op MOVs */
1033 if (inst
->dst
.file
== inst
->src
[0].file
&&
1034 inst
->dst
.reg
== inst
->src
[0].reg
&&
1035 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1036 bool is_nop_mov
= true;
1038 for (unsigned c
= 0; c
< 4; c
++) {
1039 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1042 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1049 inst
->remove(block
);
1054 bool to_mrf
= (inst
->dst
.file
== MRF
);
1056 /* Can't coalesce this GRF if someone else was going to
1059 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1062 /* We need to check interference with the final destination between this
1063 * instruction and the earliest instruction involved in writing the GRF
1064 * we're eliminating. To do that, keep track of which of our source
1065 * channels we've seen initialized.
1067 const unsigned chans_needed
=
1068 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1069 inst
->dst
.writemask
);
1070 unsigned chans_remaining
= chans_needed
;
1072 /* Now walk up the instruction stream trying to see if we can rewrite
1073 * everything writing to the temporary to write into the destination
1076 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1077 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1079 _scan_inst
= scan_inst
;
1081 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1082 /* Found something writing to the reg we want to coalesce away. */
1084 /* SEND instructions can't have MRF as a destination. */
1085 if (scan_inst
->mlen
)
1088 if (devinfo
->gen
== 6) {
1089 /* gen6 math instructions must have the destination be
1090 * GRF, so no compute-to-MRF for them.
1092 if (scan_inst
->is_math()) {
1098 /* This doesn't handle saturation on the instruction we
1099 * want to coalesce away if the register types do not match.
1100 * But if scan_inst is a non type-converting 'mov', we can fix
1103 if (inst
->saturate
&&
1104 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1105 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1106 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1109 /* If we can't handle the swizzle, bail. */
1110 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1111 inst
->src
[0].swizzle
,
1116 /* This doesn't handle coalescing of multiple registers. */
1117 if (scan_inst
->regs_written
> 1)
1120 /* Mark which channels we found unconditional writes for. */
1121 if (!scan_inst
->predicate
)
1122 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1124 if (chans_remaining
== 0)
1128 /* You can't read from an MRF, so if someone else reads our MRF's
1129 * source GRF that we wanted to rewrite, that stops us. If it's a
1130 * GRF we're trying to coalesce to, we don't actually handle
1131 * rewriting sources so bail in that case as well.
1133 bool interfered
= false;
1134 for (int i
= 0; i
< 3; i
++) {
1135 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1136 scan_inst
->regs_read(i
)))
1142 /* If somebody else writes the same channels of our destination here,
1143 * we can't coalesce before that.
1145 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1146 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1150 /* Check for reads of the register we're trying to coalesce into. We
1151 * can't go rewriting instructions above that to put some other value
1152 * in the register instead.
1154 if (to_mrf
&& scan_inst
->mlen
> 0) {
1155 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1156 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1160 for (int i
= 0; i
< 3; i
++) {
1161 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1162 scan_inst
->regs_read(i
)))
1170 if (chans_remaining
== 0) {
1171 /* If we've made it here, we have an MOV we want to coalesce out, and
1172 * a scan_inst pointing to the earliest instruction involved in
1173 * computing the value. Now go rewrite the instruction stream
1176 vec4_instruction
*scan_inst
= _scan_inst
;
1177 while (scan_inst
!= inst
) {
1178 if (scan_inst
->dst
.file
== GRF
&&
1179 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1180 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1181 scan_inst
->reswizzle(inst
->dst
.writemask
,
1182 inst
->src
[0].swizzle
);
1183 scan_inst
->dst
.file
= inst
->dst
.file
;
1184 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1185 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1186 if (inst
->saturate
&&
1187 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1188 /* If we have reached this point, scan_inst is a non
1189 * type-converting 'mov' and we can modify its register types
1190 * to match the ones in inst. Otherwise, we could have an
1191 * incorrect saturation result.
1193 scan_inst
->dst
.type
= inst
->dst
.type
;
1194 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1196 scan_inst
->saturate
|= inst
->saturate
;
1198 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1200 inst
->remove(block
);
1206 invalidate_live_intervals();
1212 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1213 * flow. We could probably do better here with some form of divergence
1217 vec4_visitor::eliminate_find_live_channel()
1219 bool progress
= false;
1222 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1223 switch (inst
->opcode
) {
1229 case BRW_OPCODE_ENDIF
:
1230 case BRW_OPCODE_WHILE
:
1234 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1236 inst
->opcode
= BRW_OPCODE_MOV
;
1237 inst
->src
[0] = src_reg(0);
1238 inst
->force_writemask_all
= true;
1252 * Splits virtual GRFs requesting more than one contiguous physical register.
1254 * We initially create large virtual GRFs for temporary structures, arrays,
1255 * and matrices, so that the dereference visitor functions can add reg_offsets
1256 * to work their way down to the actual member being accessed. But when it
1257 * comes to optimization, we'd like to treat each register as individual
1258 * storage if possible.
1260 * So far, the only thing that might prevent splitting is a send message from
1264 vec4_visitor::split_virtual_grfs()
1266 int num_vars
= this->alloc
.count
;
1267 int new_virtual_grf
[num_vars
];
1268 bool split_grf
[num_vars
];
1270 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1272 /* Try to split anything > 0 sized. */
1273 for (int i
= 0; i
< num_vars
; i
++) {
1274 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1277 /* Check that the instructions are compatible with the registers we're trying
1280 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1281 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1282 split_grf
[inst
->dst
.reg
] = false;
1284 for (int i
= 0; i
< 3; i
++) {
1285 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1286 split_grf
[inst
->src
[i
].reg
] = false;
1290 /* Allocate new space for split regs. Note that the virtual
1291 * numbers will be contiguous.
1293 for (int i
= 0; i
< num_vars
; i
++) {
1297 new_virtual_grf
[i
] = alloc
.allocate(1);
1298 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1299 unsigned reg
= alloc
.allocate(1);
1300 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1303 this->alloc
.sizes
[i
] = 1;
1306 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1307 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1308 inst
->dst
.reg_offset
!= 0) {
1309 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1310 inst
->dst
.reg_offset
- 1);
1311 inst
->dst
.reg_offset
= 0;
1313 for (int i
= 0; i
< 3; i
++) {
1314 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1315 inst
->src
[i
].reg_offset
!= 0) {
1316 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1317 inst
->src
[i
].reg_offset
- 1);
1318 inst
->src
[i
].reg_offset
= 0;
1322 invalidate_live_intervals();
1326 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1328 dump_instruction(be_inst
, stderr
);
1332 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1334 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1336 if (inst
->predicate
) {
1337 fprintf(file
, "(%cf0.%d) ",
1338 inst
->predicate_inverse
? '-' : '+',
1342 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1344 fprintf(file
, ".sat");
1345 if (inst
->conditional_mod
) {
1346 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1347 if (!inst
->predicate
&&
1348 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1349 inst
->opcode
!= BRW_OPCODE_IF
&&
1350 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1351 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1356 switch (inst
->dst
.file
) {
1358 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1361 fprintf(file
, "m%d", inst
->dst
.reg
);
1364 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1365 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1367 fprintf(file
, "null");
1369 case BRW_ARF_ADDRESS
:
1370 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1372 case BRW_ARF_ACCUMULATOR
:
1373 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1376 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1377 inst
->dst
.fixed_hw_reg
.subnr
);
1380 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1381 inst
->dst
.fixed_hw_reg
.subnr
);
1385 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1387 if (inst
->dst
.fixed_hw_reg
.subnr
)
1388 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1391 fprintf(file
, "(null)");
1394 fprintf(file
, "???");
1397 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1399 if (inst
->dst
.writemask
& 1)
1401 if (inst
->dst
.writemask
& 2)
1403 if (inst
->dst
.writemask
& 4)
1405 if (inst
->dst
.writemask
& 8)
1408 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1410 if (inst
->src
[0].file
!= BAD_FILE
)
1411 fprintf(file
, ", ");
1413 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1414 if (inst
->src
[i
].negate
)
1416 if (inst
->src
[i
].abs
)
1418 switch (inst
->src
[i
].file
) {
1420 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1423 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1426 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1429 switch (inst
->src
[i
].type
) {
1430 case BRW_REGISTER_TYPE_F
:
1431 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1433 case BRW_REGISTER_TYPE_D
:
1434 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1436 case BRW_REGISTER_TYPE_UD
:
1437 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1439 case BRW_REGISTER_TYPE_VF
:
1440 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1441 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1442 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1443 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1444 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1447 fprintf(file
, "???");
1452 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1454 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1456 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1457 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1459 fprintf(file
, "null");
1461 case BRW_ARF_ADDRESS
:
1462 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1464 case BRW_ARF_ACCUMULATOR
:
1465 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1468 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1469 inst
->src
[i
].fixed_hw_reg
.subnr
);
1472 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1473 inst
->src
[i
].fixed_hw_reg
.subnr
);
1477 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1479 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1480 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1481 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1485 fprintf(file
, "(null)");
1488 fprintf(file
, "???");
1492 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1493 if (inst
->src
[i
].reg_offset
!= 0 &&
1494 inst
->src
[i
].file
== GRF
&&
1495 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1496 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1498 if (inst
->src
[i
].file
!= IMM
) {
1499 static const char *chans
[4] = {"x", "y", "z", "w"};
1501 for (int c
= 0; c
< 4; c
++) {
1502 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1506 if (inst
->src
[i
].abs
)
1509 if (inst
->src
[i
].file
!= IMM
) {
1510 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1513 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1514 fprintf(file
, ", ");
1517 fprintf(file
, "\n");
1521 static inline struct brw_reg
1522 attribute_to_hw_reg(int attr
, bool interleaved
)
1525 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1527 return brw_vec8_grf(attr
, 0);
1532 * Replace each register of type ATTR in this->instructions with a reference
1533 * to a fixed HW register.
1535 * If interleaved is true, then each attribute takes up half a register, with
1536 * register N containing attribute 2*N in its first half and attribute 2*N+1
1537 * in its second half (this corresponds to the payload setup used by geometry
1538 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1539 * false, then each attribute takes up a whole register, with register N
1540 * containing attribute N (this corresponds to the payload setup used by
1541 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1544 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1547 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1548 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1549 if (inst
->dst
.file
== ATTR
) {
1550 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1552 /* All attributes used in the shader need to have been assigned a
1553 * hardware register by the caller
1557 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1558 reg
.type
= inst
->dst
.type
;
1559 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1561 inst
->dst
.file
= HW_REG
;
1562 inst
->dst
.fixed_hw_reg
= reg
;
1565 for (int i
= 0; i
< 3; i
++) {
1566 if (inst
->src
[i
].file
!= ATTR
)
1569 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1571 /* All attributes used in the shader need to have been assigned a
1572 * hardware register by the caller
1576 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1577 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1578 reg
.type
= inst
->src
[i
].type
;
1579 if (inst
->src
[i
].abs
)
1581 if (inst
->src
[i
].negate
)
1584 inst
->src
[i
].file
= HW_REG
;
1585 inst
->src
[i
].fixed_hw_reg
= reg
;
1591 vec4_vs_visitor::setup_attributes(int payload_reg
)
1594 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1595 memset(attribute_map
, 0, sizeof(attribute_map
));
1598 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1599 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1600 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1605 /* VertexID is stored by the VF as the last vertex element, but we
1606 * don't represent it with a flag in inputs_read, so we call it
1609 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1610 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1614 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1616 /* The BSpec says we always have to read at least one thing from
1617 * the VF, and it appears that the hardware wedges otherwise.
1619 if (nr_attributes
== 0)
1622 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1624 unsigned vue_entries
=
1625 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1627 if (devinfo
->gen
== 6)
1628 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1630 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1632 return payload_reg
+ nr_attributes
;
1636 vec4_visitor::setup_uniforms(int reg
)
1638 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1640 /* The pre-gen6 VS requires that some push constants get loaded no
1641 * matter what, or the GPU would hang.
1643 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1644 assert(this->uniforms
< this->uniform_array_size
);
1645 this->uniform_vector_size
[this->uniforms
] = 1;
1647 stage_prog_data
->param
=
1648 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1649 for (unsigned int i
= 0; i
< 4; i
++) {
1650 unsigned int slot
= this->uniforms
* 4 + i
;
1651 static gl_constant_value zero
= { 0.0 };
1652 stage_prog_data
->param
[slot
] = &zero
;
1658 reg
+= ALIGN(uniforms
, 2) / 2;
1661 stage_prog_data
->nr_params
= this->uniforms
* 4;
1663 prog_data
->base
.curb_read_length
=
1664 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1670 vec4_vs_visitor::setup_payload(void)
1674 /* The payload always contains important data in g0, which contains
1675 * the URB handles that are passed on to the URB write at the end
1676 * of the thread. So, we always start push constants at g1.
1680 reg
= setup_uniforms(reg
);
1682 reg
= setup_attributes(reg
);
1684 this->first_non_payload_grf
= reg
;
1688 vec4_visitor::assign_binding_table_offsets()
1690 assign_common_binding_table_offsets(0);
1694 vec4_visitor::get_timestamp()
1696 assert(devinfo
->gen
>= 7);
1698 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1703 BRW_REGISTER_TYPE_UD
,
1704 BRW_VERTICAL_STRIDE_0
,
1706 BRW_HORIZONTAL_STRIDE_4
,
1710 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1712 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1713 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1714 * even if it's not enabled in the dispatch.
1716 mov
->force_writemask_all
= true;
1718 return src_reg(dst
);
1722 vec4_visitor::emit_shader_time_begin()
1724 current_annotation
= "shader time start";
1725 shader_start_time
= get_timestamp();
1729 vec4_visitor::emit_shader_time_end()
1731 current_annotation
= "shader time end";
1732 src_reg shader_end_time
= get_timestamp();
1735 /* Check that there weren't any timestamp reset events (assuming these
1736 * were the only two timestamp reads that happened).
1738 src_reg reset_end
= shader_end_time
;
1739 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1740 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1741 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1743 emit(IF(BRW_PREDICATE_NORMAL
));
1745 /* Take the current timestamp and get the delta. */
1746 shader_start_time
.negate
= true;
1747 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1748 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1750 /* If there were no instructions between the two timestamp gets, the diff
1751 * is 2 cycles. Remove that overhead, so I can forget about that when
1752 * trying to determine the time taken for single instructions.
1754 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1756 emit_shader_time_write(0, src_reg(diff
));
1757 emit_shader_time_write(1, src_reg(1u));
1758 emit(BRW_OPCODE_ELSE
);
1759 emit_shader_time_write(2, src_reg(1u));
1760 emit(BRW_OPCODE_ENDIF
);
1764 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1767 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1769 dst_reg offset
= dst
;
1773 offset
.type
= BRW_REGISTER_TYPE_UD
;
1774 int index
= shader_time_index
* 3 + shader_time_subindex
;
1775 emit(MOV(offset
, src_reg(index
* SHADER_TIME_STRIDE
)));
1777 time
.type
= BRW_REGISTER_TYPE_UD
;
1778 emit(MOV(time
, src_reg(value
)));
1780 vec4_instruction
*inst
=
1781 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1789 compiler
->glsl_compiler_options
[stage
].NirOptions
!= NULL
;
1791 sanity_param_count
= prog
->Parameters
->NumParameters
;
1793 if (shader_time_index
>= 0)
1794 emit_shader_time_begin();
1796 assign_binding_table_offsets();
1801 assert(prog
->nir
!= NULL
);
1805 } else if (shader
) {
1806 /* Generate VS IR for main(). (the visitor only descends into
1807 * functions called "main").
1809 visit_instructions(shader
->base
.ir
);
1811 emit_program_code();
1819 /* Before any optimization, push array accesses out to scratch
1820 * space where we need them to be. This pass may allocate new
1821 * virtual GRFs, so we want to do it early. It also makes sure
1822 * that we have reladdr computations available for CSE, since we'll
1823 * often do repeated subexpressions for those.
1825 if (shader
|| use_vec4_nir
) {
1826 move_grf_array_access_to_scratch();
1827 move_uniform_array_access_to_pull_constants();
1829 /* The ARB_vertex_program frontend emits pull constant loads directly
1830 * rather than using reladdr, so we don't need to walk through all the
1831 * instructions looking for things to move. There isn't anything.
1833 * We do still need to split things to vec4 size.
1835 split_uniform_registers();
1837 pack_uniform_registers();
1838 move_push_constants_to_pull_constants();
1839 split_virtual_grfs();
1841 #define OPT(pass, args...) ({ \
1843 bool this_progress = pass(args); \
1845 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1846 char filename[64]; \
1847 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1848 stage_abbrev, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1850 backend_shader::dump_instructions(filename); \
1853 progress = progress || this_progress; \
1858 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1860 snprintf(filename
, 64, "%s-%04d-00-start",
1861 stage_abbrev
, shader_prog
? shader_prog
->Name
: 0);
1863 backend_shader::dump_instructions(filename
);
1874 OPT(opt_reduce_swizzle
);
1875 OPT(dead_code_eliminate
);
1876 OPT(dead_control_flow_eliminate
, this);
1877 OPT(opt_copy_propagation
);
1880 OPT(opt_register_coalesce
);
1881 OPT(eliminate_find_live_channel
);
1886 if (OPT(opt_vector_float
)) {
1888 OPT(opt_copy_propagation
, false);
1889 OPT(opt_copy_propagation
, true);
1890 OPT(dead_code_eliminate
);
1898 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1899 /* Debug of register spilling: Go spill everything. */
1900 const int grf_count
= alloc
.count
;
1901 float spill_costs
[alloc
.count
];
1902 bool no_spill
[alloc
.count
];
1903 evaluate_spill_costs(spill_costs
, no_spill
);
1904 for (int i
= 0; i
< grf_count
; i
++) {
1911 bool allocated_without_spills
= reg_allocate();
1913 if (!allocated_without_spills
) {
1914 compiler
->shader_perf_log(log_data
,
1915 "%s shader triggered register spilling. "
1916 "Try reducing the number of live vec4 values "
1917 "to improve performance.\n",
1920 while (!reg_allocate()) {
1926 opt_schedule_instructions();
1928 opt_set_dependency_control();
1930 if (last_scratch
> 0) {
1931 prog_data
->base
.total_scratch
=
1932 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1935 /* If any state parameters were appended, then ParameterValues could have
1936 * been realloced, in which case the driver uniform storage set up by
1937 * _mesa_associate_uniform_storage() would point to freed memory. Make
1938 * sure that didn't happen.
1940 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1945 } /* namespace brw */
1950 * Compile a vertex shader.
1952 * Returns the final assembly and the program's size.
1955 brw_vs_emit(struct brw_context
*brw
,
1957 const struct brw_vs_prog_key
*key
,
1958 struct brw_vs_prog_data
*prog_data
,
1959 struct gl_vertex_program
*vp
,
1960 struct gl_shader_program
*prog
,
1961 unsigned *final_assembly_size
)
1963 const unsigned *assembly
= NULL
;
1965 struct brw_shader
*shader
= NULL
;
1967 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1970 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1971 st_index
= brw_get_shader_time_index(brw
, prog
, &vp
->Base
, ST_VS
);
1973 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1974 brw_dump_ir("vertex", prog
, &shader
->base
, &vp
->Base
);
1976 if (!vp
->Base
.nir
&&
1977 (brw
->intelScreen
->compiler
->scalar_vs
||
1978 brw
->intelScreen
->compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].NirOptions
!= NULL
)) {
1979 /* Normally we generate NIR in LinkShader() or
1980 * ProgramStringNotify(), but Mesa's fixed-function vertex program
1981 * handling doesn't notify the driver at all. Just do it here, at
1982 * the last minute, even though it's lame.
1984 assert(vp
->Base
.Id
== 0 && prog
== NULL
);
1986 brw_create_nir(brw
, NULL
, &vp
->Base
, MESA_SHADER_VERTEX
,
1987 brw
->intelScreen
->compiler
->scalar_vs
);
1990 if (brw
->intelScreen
->compiler
->scalar_vs
) {
1991 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1993 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
1994 mem_ctx
, MESA_SHADER_VERTEX
, key
,
1995 &prog_data
->base
.base
, prog
, &vp
->Base
,
1997 if (!v
.run_vs(brw_select_clip_planes(&brw
->ctx
))) {
1999 prog
->LinkStatus
= false;
2000 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
2003 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
2009 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
2010 mem_ctx
, (void *) key
, &prog_data
->base
.base
,
2011 &vp
->Base
, v
.promoted_constants
,
2012 v
.runtime_check_aads_emit
, "VS");
2013 if (INTEL_DEBUG
& DEBUG_VS
) {
2016 name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
2017 prog
->Label
? prog
->Label
: "unnamed",
2020 name
= ralloc_asprintf(mem_ctx
, "vertex program %d",
2023 g
.enable_debug(name
);
2025 g
.generate_code(v
.cfg
, 8);
2026 assembly
= g
.get_assembly(final_assembly_size
);
2030 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2032 vec4_vs_visitor
v(brw
->intelScreen
->compiler
, brw
, key
, prog_data
,
2033 vp
, prog
, brw_select_clip_planes(&brw
->ctx
),
2035 !_mesa_is_gles3(&brw
->ctx
));
2038 prog
->LinkStatus
= false;
2039 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
2042 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
2048 vec4_generator
g(brw
->intelScreen
->compiler
, brw
,
2049 prog
, &vp
->Base
, &prog_data
->base
,
2050 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
2051 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);