src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39
  40 #ifdef __cplusplus
  41 }; /* extern "C" */
  42 #include "gen8_generator.h"
  43 #endif
  44
  45 #include "glsl/ir.h"
  46
  47
  48 struct brw_vec4_compile {
  49    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  50 };
  51
  52
  53 struct brw_vec4_prog_key {
  54    GLuint program_string_id;
  55
  56    /**
  57     * True if at least one clip flag is enabled, regardless of whether the
  58     * shader uses clip planes or gl_ClipDistance.
  59     */
  60    GLuint userclip_active:1;
  61
  62    /**
  63     * How many user clipping planes are being uploaded to the vertex shader as
  64     * push constants.
  65     */
  66    GLuint nr_userclip_plane_consts:4;
  67
  68    GLuint clamp_vertex_color:1;
  69
  70    struct brw_sampler_prog_key_data tex;
  71 };
  72
  73
  74 #ifdef __cplusplus
  75 extern "C" {
  76 #endif
  77
  78 void
  79 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
  80                                        struct brw_vec4_prog_key *key,
  81                                        GLuint id, struct gl_program *prog);
  82
  83 #ifdef __cplusplus
  84 } /* extern "C" */
  85
  86 namespace brw {
  87
  88 class dst_reg;
  89
  90 unsigned
  91 swizzle_for_size(int size);
  92
  93 class reg
  94 {
  95 public:
  96    /** Register file: GRF, MRF, IMM. */
  97    enum register_file file;
  98    /** virtual register number.  0 = fixed hw reg */
  99    int reg;
 100    /** Offset within the virtual register. */
 101    int reg_offset;
 102    /** Register type.  BRW_REGISTER_TYPE_* */
 103    int type;
 104    struct brw_reg fixed_hw_reg;
 105
 106    /** Value for file == BRW_IMMMEDIATE_FILE */
 107    union {
 108       int32_t i;
 109       uint32_t u;
 110       float f;
 111    } imm;
 112 };
 113
 114 class src_reg : public reg
 115 {
 116 public:
 117    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
 118
 119    void init();
 120
 121    src_reg(register_file file, int reg, const glsl_type *type);
 122    src_reg();
 123    src_reg(float f);
 124    src_reg(uint32_t u);
 125    src_reg(int32_t i);
 126    src_reg(struct brw_reg reg);
 127
 128    bool equals(src_reg *r);
 129    bool is_zero() const;
 130    bool is_one() const;
 131
 132    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 133
 134    explicit src_reg(dst_reg reg);
 135
 136    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 137    bool negate;
 138    bool abs;
 139
 140    src_reg *reladdr;
 141 };
 142
 143 static inline src_reg
 144 retype(src_reg reg, unsigned type)
 145 {
 146    reg.fixed_hw_reg.type = reg.type = type;
 147    return reg;
 148 }
 149
 150 static inline src_reg
 151 offset(src_reg reg, unsigned delta)
 152 {
 153    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 154    reg.reg_offset += delta;
 155    return reg;
 156 }
 157
 158 /**
 159  * Reswizzle a given source register.
 160  * \sa brw_swizzle().
 161  */
 162 static inline src_reg
 163 swizzle(src_reg reg, unsigned swizzle)
 164 {
 165    assert(reg.file != HW_REG);
 166    reg.swizzle = BRW_SWIZZLE4(
 167       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
 168       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
 169       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
 170       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
 171    return reg;
 172 }
 173
 174 static inline src_reg
 175 negate(src_reg reg)
 176 {
 177    assert(reg.file != HW_REG && reg.file != IMM);
 178    reg.negate = !reg.negate;
 179    return reg;
 180 }
 181
 182 class dst_reg : public reg
 183 {
 184 public:
 185    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 186
 187    void init();
 188
 189    dst_reg();
 190    dst_reg(register_file file, int reg);
 191    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 192    dst_reg(struct brw_reg reg);
 193    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 194
 195    explicit dst_reg(src_reg reg);
 196
 197    bool is_null() const;
 198
 199    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 200
 201    src_reg *reladdr;
 202 };
 203
 204 static inline dst_reg
 205 retype(dst_reg reg, unsigned type)
 206 {
 207    reg.fixed_hw_reg.type = reg.type = type;
 208    return reg;
 209 }
 210
 211 static inline dst_reg
 212 offset(dst_reg reg, unsigned delta)
 213 {
 214    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 215    reg.reg_offset += delta;
 216    return reg;
 217 }
 218
 219 static inline dst_reg
 220 writemask(dst_reg reg, unsigned mask)
 221 {
 222    assert(reg.file != HW_REG && reg.file != IMM);
 223    assert((reg.writemask & mask) != 0);
 224    reg.writemask &= mask;
 225    return reg;
 226 }
 227
 228 class vec4_instruction : public backend_instruction {
 229 public:
 230    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 231
 232    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 233                     dst_reg dst = dst_reg(),
 234                     src_reg src0 = src_reg(),
 235                     src_reg src1 = src_reg(),
 236                     src_reg src2 = src_reg());
 237
 238    struct brw_reg get_dst(void);
 239    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 240
 241    dst_reg dst;
 242    src_reg src[3];
 243
 244    bool saturate;
 245    bool force_writemask_all;
 246    bool no_dd_clear, no_dd_check;
 247
 248    int conditional_mod; /**< BRW_CONDITIONAL_* */
 249
 250    int sampler;
 251    uint32_t texture_offset; /**< Texture Offset bitfield */
 252    int target; /**< MRT target. */
 253    bool shadow_compare;
 254
 255    enum brw_urb_write_flags urb_write_flags;
 256    bool header_present;
 257    int mlen; /**< SEND message length */
 258    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 259
 260    uint32_t offset; /* spill/unspill offset */
 261    /** @{
 262     * Annotation for the generated IR.  One of the two can be set.
 263     */
 264    const void *ir;
 265    const char *annotation;
 266    /** @} */
 267
 268    bool is_send_from_grf();
 269    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 270    void reswizzle_dst(int dst_writemask, int swizzle);
 271
 272    bool reads_flag()
 273    {
 274       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 275    }
 276
 277    bool writes_flag()
 278    {
 279       return conditional_mod && opcode != BRW_OPCODE_SEL;
 280    }
 281 };
 282
 283 /**
 284  * The vertex shader front-end.
 285  *
 286  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 287  * fixed-function) into VS IR.
 288  */
 289 class vec4_visitor : public backend_visitor
 290 {
 291 public:
 292    vec4_visitor(struct brw_context *brw,
 293                 struct brw_vec4_compile *c,
 294                 struct gl_program *prog,
 295                 const struct brw_vec4_prog_key *key,
 296                 struct brw_vec4_prog_data *prog_data,
 297                 struct gl_shader_program *shader_prog,
 298                 gl_shader_stage stage,
 299                 void *mem_ctx,
 300                 bool debug_flag,
 301                 bool no_spills,
 302                 shader_time_shader_type st_base,
 303                 shader_time_shader_type st_written,
 304                 shader_time_shader_type st_reset);
 305    ~vec4_visitor();
 306
 307    dst_reg dst_null_f()
 308    {
 309       return dst_reg(brw_null_reg());
 310    }
 311
 312    dst_reg dst_null_d()
 313    {
 314       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 315    }
 316
 317    dst_reg dst_null_ud()
 318    {
 319       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 320    }
 321
 322    struct brw_vec4_compile * const c;
 323    const struct brw_vec4_prog_key * const key;
 324    struct brw_vec4_prog_data * const prog_data;
 325    unsigned int sanity_param_count;
 326
 327    char *fail_msg;
 328    bool failed;
 329
 330    /**
 331     * GLSL IR currently being processed, which is associated with our
 332     * driver IR instructions for debugging purposes.
 333     */
 334    const void *base_ir;
 335    const char *current_annotation;
 336
 337    int *virtual_grf_sizes;
 338    int virtual_grf_count;
 339    int virtual_grf_array_size;
 340    int first_non_payload_grf;
 341    unsigned int max_grf;
 342    int *virtual_grf_start;
 343    int *virtual_grf_end;
 344    dst_reg userplane[MAX_CLIP_PLANES];
 345
 346    /**
 347     * This is the size to be used for an array with an element per
 348     * reg_offset
 349     */
 350    int virtual_grf_reg_count;
 351    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 352    int *virtual_grf_reg_map;
 353
 354    bool live_intervals_valid;
 355
 356    dst_reg *variable_storage(ir_variable *var);
 357
 358    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 359
 360    bool need_all_constants_in_pull_buffer;
 361
 362    /**
 363     * \name Visit methods
 364     *
 365     * As typical for the visitor pattern, there must be one \c visit method for
 366     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 367     * the hierarchy should not have \c visit methods.
 368     */
 369    /*@{*/
 370    virtual void visit(ir_variable *);
 371    virtual void visit(ir_loop *);
 372    virtual void visit(ir_loop_jump *);
 373    virtual void visit(ir_function_signature *);
 374    virtual void visit(ir_function *);
 375    virtual void visit(ir_expression *);
 376    virtual void visit(ir_swizzle *);
 377    virtual void visit(ir_dereference_variable  *);
 378    virtual void visit(ir_dereference_array *);
 379    virtual void visit(ir_dereference_record *);
 380    virtual void visit(ir_assignment *);
 381    virtual void visit(ir_constant *);
 382    virtual void visit(ir_call *);
 383    virtual void visit(ir_return *);
 384    virtual void visit(ir_discard *);
 385    virtual void visit(ir_texture *);
 386    virtual void visit(ir_if *);
 387    virtual void visit(ir_emit_vertex *);
 388    virtual void visit(ir_end_primitive *);
 389    /*@}*/
 390
 391    src_reg result;
 392
 393    /* Regs for vertex results.  Generated at ir_variable visiting time
 394     * for the ir->location's used.
 395     */
 396    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 397    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 398    int *uniform_size;
 399    int *uniform_vector_size;
 400    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 401    int uniforms;
 402
 403    src_reg shader_start_time;
 404
 405    struct hash_table *variable_ht;
 406
 407    bool run(void);
 408    void fail(const char *msg, ...);
 409
 410    int virtual_grf_alloc(int size);
 411    void setup_uniform_clipplane_values();
 412    void setup_uniform_values(ir_variable *ir);
 413    void setup_builtin_uniform_values(ir_variable *ir);
 414    int setup_uniforms(int payload_reg);
 415    bool reg_allocate_trivial();
 416    bool reg_allocate();
 417    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 418    int choose_spill_reg(struct ra_graph *g);
 419    void spill_reg(int spill_reg);
 420    void move_grf_array_access_to_scratch();
 421    void move_uniform_array_access_to_pull_constants();
 422    void move_push_constants_to_pull_constants();
 423    void split_uniform_registers();
 424    void pack_uniform_registers();
 425    void calculate_live_intervals();
 426    void invalidate_live_intervals();
 427    void split_virtual_grfs();
 428    bool dead_code_eliminate();
 429    bool virtual_grf_interferes(int a, int b);
 430    bool opt_copy_propagation();
 431    bool opt_algebraic();
 432    bool opt_register_coalesce();
 433    void opt_set_dependency_control();
 434    void opt_schedule_instructions();
 435
 436    bool can_do_source_mods(vec4_instruction *inst);
 437
 438    vec4_instruction *emit(vec4_instruction *inst);
 439
 440    vec4_instruction *emit(enum opcode opcode);
 441
 442    vec4_instruction *emit(enum opcode opcode, dst_reg dst);
 443
 444    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 445
 446    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 447                           src_reg src0, src_reg src1);
 448
 449    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 450                           src_reg src0, src_reg src1, src_reg src2);
 451
 452    vec4_instruction *emit_before(vec4_instruction *inst,
 453                                  vec4_instruction *new_inst);
 454
 455    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 456    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 457    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 458    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 459    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 460    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 461    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 462    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 463    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 464    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 465    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 466    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 467    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 468    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 469    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 470    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 471    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 472    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 473    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 474    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 475    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 476    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 477                          uint32_t condition);
 478    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 479    vec4_instruction *IF(uint32_t predicate);
 480    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 481    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 482    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 483    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 484    vec4_instruction *BFREV(dst_reg dst, src_reg value);
 485    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
 486    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
 487    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
 488    vec4_instruction *FBH(dst_reg dst, src_reg value);
 489    vec4_instruction *FBL(dst_reg dst, src_reg value);
 490    vec4_instruction *CBIT(dst_reg dst, src_reg value);
 491    vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
 492    vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1);
 493    vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1);
 494
 495    int implied_mrf_writes(vec4_instruction *inst);
 496
 497    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 498                                dst_reg dst,
 499                                src_reg src,
 500                                vec4_instruction *pre_rhs_inst,
 501                                vec4_instruction *last_rhs_inst);
 502
 503    bool try_copy_propagation(vec4_instruction *inst, int arg,
 504                              src_reg *values[4]);
 505
 506    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 507    void visit_instructions(const exec_list *list);
 508
 509    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 510                     src_reg src0, src_reg src1, src_reg one);
 511
 512    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 513    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 514    void emit_if_gen6(ir_if *ir);
 515
 516    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 517
 518    void emit_lrp(const dst_reg &dst,
 519                  const src_reg &x, const src_reg &y, const src_reg &a);
 520
 521    void emit_block_move(dst_reg *dst, src_reg *src,
 522                         const struct glsl_type *type, uint32_t predicate);
 523
 524    void emit_constant_values(dst_reg *dst, ir_constant *value);
 525
 526    /**
 527     * Emit the correct dot-product instruction for the type of arguments
 528     */
 529    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 530
 531    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 532                     dst_reg dst, src_reg src0);
 533
 534    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 535                     dst_reg dst, src_reg src0, src_reg src1);
 536
 537    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 538                  dst_reg dst, const src_reg &src);
 539
 540    src_reg fix_3src_operand(src_reg src);
 541
 542    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 543    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 544    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 545    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 546    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 547    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 548    src_reg fix_math_operand(src_reg src);
 549
 550    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 551    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 552
 553    uint32_t gather_channel(ir_texture *ir, int sampler);
 554    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
 555    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 556    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 557
 558    void emit_ndc_computation();
 559    void emit_psiz_and_flags(struct brw_reg reg);
 560    void emit_clip_distances(dst_reg reg, int offset);
 561    void emit_generic_urb_slot(dst_reg reg, int varying);
 562    void emit_urb_slot(int mrf, int varying);
 563
 564    void emit_shader_time_begin();
 565    void emit_shader_time_end();
 566    void emit_shader_time_write(enum shader_time_shader_type type,
 567                                src_reg value);
 568
 569    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 570                             dst_reg dst, src_reg offset, src_reg src0,
 571                             src_reg src1);
 572
 573    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 574                                   src_reg offset);
 575
 576    src_reg get_scratch_offset(vec4_instruction *inst,
 577                               src_reg *reladdr, int reg_offset);
 578    src_reg get_pull_constant_offset(vec4_instruction *inst,
 579                                     src_reg *reladdr, int reg_offset);
 580    void emit_scratch_read(vec4_instruction *inst,
 581                           dst_reg dst,
 582                           src_reg orig_src,
 583                           int base_offset);
 584    void emit_scratch_write(vec4_instruction *inst,
 585                            int base_offset);
 586    void emit_pull_constant_load(vec4_instruction *inst,
 587                                 dst_reg dst,
 588                                 src_reg orig_src,
 589                                 int base_offset);
 590
 591    bool try_emit_sat(ir_expression *ir);
 592    bool try_emit_mad(ir_expression *ir, int mul_arg);
 593    void resolve_ud_negate(src_reg *reg);
 594
 595    src_reg get_timestamp();
 596
 597    bool process_move_condition(ir_rvalue *ir);
 598
 599    void dump_instruction(backend_instruction *inst);
 600
 601    void visit_atomic_counter_intrinsic(ir_call *ir);
 602
 603 protected:
 604    void emit_vertex();
 605    void lower_attributes_to_hw_regs(const int *attribute_map,
 606                                     bool interleaved);
 607    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 608                                    int reg_node_count);
 609    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 610    virtual void setup_payload() = 0;
 611    virtual void emit_prolog() = 0;
 612    virtual void emit_program_code() = 0;
 613    virtual void emit_thread_end() = 0;
 614    virtual void emit_urb_write_header(int mrf) = 0;
 615    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 616    virtual int compute_array_stride(ir_dereference_array *ir);
 617
 618    const bool debug_flag;
 619
 620 private:
 621    /**
 622     * If true, then register allocation should fail instead of spilling.
 623     */
 624    const bool no_spills;
 625
 626    const shader_time_shader_type st_base;
 627    const shader_time_shader_type st_written;
 628    const shader_time_shader_type st_reset;
 629 };
 630
 631
 632 /**
 633  * The vertex shader code generator.
 634  *
 635  * Translates VS IR to actual i965 assembly code.
 636  */
 637 class vec4_generator
 638 {
 639 public:
 640    vec4_generator(struct brw_context *brw,
 641                   struct gl_shader_program *shader_prog,
 642                   struct gl_program *prog,
 643                   struct brw_vec4_prog_data *prog_data,
 644                   void *mem_ctx,
 645                   bool debug_flag);
 646    ~vec4_generator();
 647
 648    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 649
 650 private:
 651    void generate_code(exec_list *instructions);
 652    void generate_vec4_instruction(vec4_instruction *inst,
 653                                   struct brw_reg dst,
 654                                   struct brw_reg *src);
 655
 656    void generate_math1_gen4(vec4_instruction *inst,
 657                             struct brw_reg dst,
 658                             struct brw_reg src);
 659    void generate_math1_gen6(vec4_instruction *inst,
 660                             struct brw_reg dst,
 661                             struct brw_reg src);
 662    void generate_math2_gen4(vec4_instruction *inst,
 663                             struct brw_reg dst,
 664                             struct brw_reg src0,
 665                             struct brw_reg src1);
 666    void generate_math2_gen6(vec4_instruction *inst,
 667                             struct brw_reg dst,
 668                             struct brw_reg src0,
 669                             struct brw_reg src1);
 670    void generate_math2_gen7(vec4_instruction *inst,
 671                             struct brw_reg dst,
 672                             struct brw_reg src0,
 673                             struct brw_reg src1);
 674
 675    void generate_tex(vec4_instruction *inst,
 676                      struct brw_reg dst,
 677                      struct brw_reg src);
 678
 679    void generate_vs_urb_write(vec4_instruction *inst);
 680    void generate_gs_urb_write(vec4_instruction *inst);
 681    void generate_gs_thread_end(vec4_instruction *inst);
 682    void generate_gs_set_write_offset(struct brw_reg dst,
 683                                      struct brw_reg src0,
 684                                      struct brw_reg src1);
 685    void generate_gs_set_vertex_count(struct brw_reg dst,
 686                                      struct brw_reg src);
 687    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 688    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 689    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 690    void generate_gs_get_instance_id(struct brw_reg dst);
 691    void generate_oword_dual_block_offsets(struct brw_reg m1,
 692                                           struct brw_reg index);
 693    void generate_scratch_write(vec4_instruction *inst,
 694                                struct brw_reg dst,
 695                                struct brw_reg src,
 696                                struct brw_reg index);
 697    void generate_scratch_read(vec4_instruction *inst,
 698                               struct brw_reg dst,
 699                               struct brw_reg index);
 700    void generate_pull_constant_load(vec4_instruction *inst,
 701                                     struct brw_reg dst,
 702                                     struct brw_reg index,
 703                                     struct brw_reg offset);
 704    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 705                                          struct brw_reg dst,
 706                                          struct brw_reg surf_index,
 707                                          struct brw_reg offset);
 708    void generate_unpack_flags(vec4_instruction *inst,
 709                               struct brw_reg dst);
 710
 711    void generate_untyped_atomic(vec4_instruction *inst,
 712                                 struct brw_reg dst,
 713                                 struct brw_reg atomic_op,
 714                                 struct brw_reg surf_index);
 715
 716    void generate_untyped_surface_read(vec4_instruction *inst,
 717                                       struct brw_reg dst,
 718                                       struct brw_reg surf_index);
 719
 720    struct brw_context *brw;
 721
 722    struct brw_compile *p;
 723
 724    struct gl_shader_program *shader_prog;
 725    const struct gl_program *prog;
 726
 727    struct brw_vec4_prog_data *prog_data;
 728
 729    void *mem_ctx;
 730    const bool debug_flag;
 731 };
 732
 733 /**
 734  * The vertex shader code generator.
 735  *
 736  * Translates VS IR to actual i965 assembly code.
 737  */
 738 class gen8_vec4_generator : public gen8_generator
 739 {
 740 public:
 741    gen8_vec4_generator(struct brw_context *brw,
 742                        struct gl_shader_program *shader_prog,
 743                        struct gl_program *prog,
 744                        struct brw_vec4_prog_data *prog_data,
 745                        void *mem_ctx,
 746                        bool debug_flag);
 747    ~gen8_vec4_generator();
 748
 749    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 750
 751 private:
 752    void generate_code(exec_list *instructions);
 753    void generate_vec4_instruction(vec4_instruction *inst,
 754                                   struct brw_reg dst,
 755                                   struct brw_reg *src);
 756
 757    void generate_tex(vec4_instruction *inst,
 758                      struct brw_reg dst);
 759
 760    void generate_urb_write(vec4_instruction *ir, bool copy_g0);
 761    void generate_gs_thread_end(vec4_instruction *ir);
 762    void generate_gs_set_write_offset(struct brw_reg dst,
 763                                      struct brw_reg src0,
 764                                      struct brw_reg src1);
 765    void generate_gs_set_vertex_count(struct brw_reg dst,
 766                                      struct brw_reg src);
 767    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 768    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 769    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 770
 771    void generate_oword_dual_block_offsets(struct brw_reg m1,
 772                                           struct brw_reg index);
 773    void generate_scratch_write(vec4_instruction *inst,
 774                                struct brw_reg dst,
 775                                struct brw_reg src,
 776                                struct brw_reg index);
 777    void generate_scratch_read(vec4_instruction *inst,
 778                               struct brw_reg dst,
 779                               struct brw_reg index);
 780    void generate_pull_constant_load(vec4_instruction *inst,
 781                                     struct brw_reg dst,
 782                                     struct brw_reg index,
 783                                     struct brw_reg offset);
 784
 785    void mark_surface_used(unsigned surf_index);
 786
 787    struct brw_vec4_prog_data *prog_data;
 788
 789    const bool debug_flag;
 790 };
 791
 792
 793 } /* namespace brw */
 794 #endif /* __cplusplus */
 795
 796 #endif /* BRW_VEC4_H */