2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
31 #include "brw_program.h"
37 #include "brw_context.h"
46 struct brw_vs_compile
;
49 struct brw_vec4_compile
{
50 GLuint last_scratch
; /**< measured in 32-byte (register size) units */
54 struct brw_vec4_prog_key
{
55 GLuint program_string_id
;
58 * True if at least one clip flag is enabled, regardless of whether the
59 * shader uses clip planes or gl_ClipDistance.
61 GLuint userclip_active
:1;
64 * How many user clipping planes are being uploaded to the vertex shader as
67 GLuint nr_userclip_plane_consts
:4;
70 * True if the shader uses gl_ClipDistance, regardless of whether any clip
73 GLuint uses_clip_distance
:1;
75 GLuint clamp_vertex_color
:1;
77 struct brw_sampler_prog_key_data tex
;
85 bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data
*a
,
86 const struct brw_vec4_prog_data
*b
);
87 void brw_vec4_prog_data_free(const struct brw_vec4_prog_data
*prog_data
);
97 swizzle_for_size(int size
);
102 /** Register file: ARF, GRF, MRF, IMM. */
103 enum register_file file
;
104 /** virtual register number. 0 = fixed hw reg */
106 /** Offset within the virtual register. */
108 /** Register type. BRW_REGISTER_TYPE_* */
110 struct brw_reg fixed_hw_reg
;
112 /** Value for file == BRW_IMMMEDIATE_FILE */
120 class src_reg
: public reg
123 /* Callers of this ralloc-based new need not call delete. It's
124 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
125 static void* operator new(size_t size
, void *ctx
)
129 node
= ralloc_size(ctx
, size
);
130 assert(node
!= NULL
);
137 src_reg(register_file file
, int reg
, const glsl_type
*type
);
143 bool equals(src_reg
*r
);
144 bool is_zero() const;
147 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
149 explicit src_reg(dst_reg reg
);
151 GLuint swizzle
; /**< SWIZZLE_XYZW swizzles from Mesa. */
158 class dst_reg
: public reg
161 /* Callers of this ralloc-based new need not call delete. It's
162 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
163 static void* operator new(size_t size
, void *ctx
)
167 node
= ralloc_size(ctx
, size
);
168 assert(node
!= NULL
);
176 dst_reg(register_file file
, int reg
);
177 dst_reg(register_file file
, int reg
, const glsl_type
*type
, int writemask
);
178 dst_reg(struct brw_reg reg
);
179 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
181 explicit dst_reg(src_reg reg
);
183 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
188 class vec4_instruction
: public backend_instruction
{
190 /* Callers of this ralloc-based new need not call delete. It's
191 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
192 static void* operator new(size_t size
, void *ctx
)
196 node
= rzalloc_size(ctx
, size
);
197 assert(node
!= NULL
);
202 vec4_instruction(vec4_visitor
*v
, enum opcode opcode
,
203 dst_reg dst
= dst_reg(),
204 src_reg src0
= src_reg(),
205 src_reg src1
= src_reg(),
206 src_reg src2
= src_reg());
208 struct brw_reg
get_dst(void);
209 struct brw_reg
get_src(const struct brw_vec4_prog_data
*prog_data
, int i
);
215 bool force_writemask_all
;
216 bool no_dd_clear
, no_dd_check
;
218 int conditional_mod
; /**< BRW_CONDITIONAL_* */
221 uint32_t texture_offset
; /**< Texture Offset bitfield */
222 int target
; /**< MRT target. */
227 int mlen
; /**< SEND message length */
228 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
230 uint32_t offset
; /* spill/unspill offset */
232 * Annotation for the generated IR. One of the two can be set.
235 const char *annotation
;
237 bool is_send_from_grf();
238 bool can_reswizzle_dst(int dst_writemask
, int swizzle
, int swizzle_mask
);
239 void reswizzle_dst(int dst_writemask
, int swizzle
);
241 bool depends_on_flags()
243 return predicate
|| opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
;
248 * The vertex shader front-end.
250 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
251 * fixed-function) into VS IR.
253 class vec4_visitor
: public backend_visitor
256 vec4_visitor(struct brw_context
*brw
,
257 struct brw_vec4_compile
*c
,
258 struct gl_program
*prog
,
259 const struct brw_vec4_prog_key
*key
,
260 struct brw_vec4_prog_data
*prog_data
,
261 struct gl_shader_program
*shader_prog
,
262 struct brw_shader
*shader
,
269 return dst_reg(brw_null_reg());
274 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
277 struct gl_program
*prog
;
278 struct brw_vec4_compile
*c
;
279 const struct brw_vec4_prog_key
*key
;
280 struct brw_vec4_prog_data
*prog_data
;
281 unsigned int sanity_param_count
;
287 * GLSL IR currently being processed, which is associated with our
288 * driver IR instructions for debugging purposes.
291 const char *current_annotation
;
293 int *virtual_grf_sizes
;
294 int virtual_grf_count
;
295 int virtual_grf_array_size
;
296 int first_non_payload_grf
;
297 unsigned int max_grf
;
298 int *virtual_grf_start
;
299 int *virtual_grf_end
;
300 dst_reg userplane
[MAX_CLIP_PLANES
];
303 * This is the size to be used for an array with an element per
306 int virtual_grf_reg_count
;
307 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
308 int *virtual_grf_reg_map
;
310 bool live_intervals_valid
;
312 dst_reg
*variable_storage(ir_variable
*var
);
314 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
316 bool need_all_constants_in_pull_buffer
;
319 * \name Visit methods
321 * As typical for the visitor pattern, there must be one \c visit method for
322 * each concrete subclass of \c ir_instruction. Virtual base classes within
323 * the hierarchy should not have \c visit methods.
326 virtual void visit(ir_variable
*);
327 virtual void visit(ir_loop
*);
328 virtual void visit(ir_loop_jump
*);
329 virtual void visit(ir_function_signature
*);
330 virtual void visit(ir_function
*);
331 virtual void visit(ir_expression
*);
332 virtual void visit(ir_swizzle
*);
333 virtual void visit(ir_dereference_variable
*);
334 virtual void visit(ir_dereference_array
*);
335 virtual void visit(ir_dereference_record
*);
336 virtual void visit(ir_assignment
*);
337 virtual void visit(ir_constant
*);
338 virtual void visit(ir_call
*);
339 virtual void visit(ir_return
*);
340 virtual void visit(ir_discard
*);
341 virtual void visit(ir_texture
*);
342 virtual void visit(ir_if
*);
343 virtual void visit(ir_emit_vertex
*);
344 virtual void visit(ir_end_primitive
*);
349 /* Regs for vertex results. Generated at ir_variable visiting time
350 * for the ir->location's used.
352 dst_reg output_reg
[BRW_VARYING_SLOT_COUNT
];
353 const char *output_reg_annotation
[BRW_VARYING_SLOT_COUNT
];
354 int uniform_size
[MAX_UNIFORMS
];
355 int uniform_vector_size
[MAX_UNIFORMS
];
358 src_reg shader_start_time
;
360 struct hash_table
*variable_ht
;
363 void fail(const char *msg
, ...);
365 int virtual_grf_alloc(int size
);
366 void setup_uniform_clipplane_values();
367 void setup_uniform_values(ir_variable
*ir
);
368 void setup_builtin_uniform_values(ir_variable
*ir
);
369 int setup_uniforms(int payload_reg
);
370 bool reg_allocate_trivial();
372 void evaluate_spill_costs(float *spill_costs
, bool *no_spill
);
373 int choose_spill_reg(struct ra_graph
*g
);
374 void spill_reg(int spill_reg
);
375 void move_grf_array_access_to_scratch();
376 void move_uniform_array_access_to_pull_constants();
377 void move_push_constants_to_pull_constants();
378 void split_uniform_registers();
379 void pack_uniform_registers();
380 void calculate_live_intervals();
381 void split_virtual_grfs();
382 bool dead_code_eliminate();
383 bool virtual_grf_interferes(int a
, int b
);
384 bool opt_copy_propagation();
385 bool opt_algebraic();
386 bool opt_register_coalesce();
387 void opt_set_dependency_control();
388 void opt_schedule_instructions();
390 bool can_do_source_mods(vec4_instruction
*inst
);
392 vec4_instruction
*emit(vec4_instruction
*inst
);
394 vec4_instruction
*emit(enum opcode opcode
);
396 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
, src_reg src0
);
398 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
399 src_reg src0
, src_reg src1
);
401 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
402 src_reg src0
, src_reg src1
, src_reg src2
);
404 vec4_instruction
*emit_before(vec4_instruction
*inst
,
405 vec4_instruction
*new_inst
);
407 vec4_instruction
*MOV(dst_reg dst
, src_reg src0
);
408 vec4_instruction
*NOT(dst_reg dst
, src_reg src0
);
409 vec4_instruction
*RNDD(dst_reg dst
, src_reg src0
);
410 vec4_instruction
*RNDE(dst_reg dst
, src_reg src0
);
411 vec4_instruction
*RNDZ(dst_reg dst
, src_reg src0
);
412 vec4_instruction
*FRC(dst_reg dst
, src_reg src0
);
413 vec4_instruction
*F32TO16(dst_reg dst
, src_reg src0
);
414 vec4_instruction
*F16TO32(dst_reg dst
, src_reg src0
);
415 vec4_instruction
*ADD(dst_reg dst
, src_reg src0
, src_reg src1
);
416 vec4_instruction
*MUL(dst_reg dst
, src_reg src0
, src_reg src1
);
417 vec4_instruction
*MACH(dst_reg dst
, src_reg src0
, src_reg src1
);
418 vec4_instruction
*MAC(dst_reg dst
, src_reg src0
, src_reg src1
);
419 vec4_instruction
*AND(dst_reg dst
, src_reg src0
, src_reg src1
);
420 vec4_instruction
*OR(dst_reg dst
, src_reg src0
, src_reg src1
);
421 vec4_instruction
*XOR(dst_reg dst
, src_reg src0
, src_reg src1
);
422 vec4_instruction
*DP3(dst_reg dst
, src_reg src0
, src_reg src1
);
423 vec4_instruction
*DP4(dst_reg dst
, src_reg src0
, src_reg src1
);
424 vec4_instruction
*DPH(dst_reg dst
, src_reg src0
, src_reg src1
);
425 vec4_instruction
*SHL(dst_reg dst
, src_reg src0
, src_reg src1
);
426 vec4_instruction
*SHR(dst_reg dst
, src_reg src0
, src_reg src1
);
427 vec4_instruction
*ASR(dst_reg dst
, src_reg src0
, src_reg src1
);
428 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
430 vec4_instruction
*IF(src_reg src0
, src_reg src1
, uint32_t condition
);
431 vec4_instruction
*IF(uint32_t predicate
);
432 vec4_instruction
*PULL_CONSTANT_LOAD(dst_reg dst
, src_reg index
);
433 vec4_instruction
*SCRATCH_READ(dst_reg dst
, src_reg index
);
434 vec4_instruction
*SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
);
435 vec4_instruction
*LRP(dst_reg dst
, src_reg a
, src_reg y
, src_reg x
);
436 vec4_instruction
*BFREV(dst_reg dst
, src_reg value
);
437 vec4_instruction
*BFE(dst_reg dst
, src_reg bits
, src_reg offset
, src_reg value
);
438 vec4_instruction
*BFI1(dst_reg dst
, src_reg bits
, src_reg offset
);
439 vec4_instruction
*BFI2(dst_reg dst
, src_reg bfi1_dst
, src_reg insert
, src_reg base
);
440 vec4_instruction
*FBH(dst_reg dst
, src_reg value
);
441 vec4_instruction
*FBL(dst_reg dst
, src_reg value
);
442 vec4_instruction
*CBIT(dst_reg dst
, src_reg value
);
444 int implied_mrf_writes(vec4_instruction
*inst
);
446 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
449 vec4_instruction
*pre_rhs_inst
,
450 vec4_instruction
*last_rhs_inst
);
452 bool try_copy_propagation(vec4_instruction
*inst
, int arg
,
455 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
456 void visit_instructions(const exec_list
*list
);
458 void emit_vp_sop(uint32_t condmod
, dst_reg dst
,
459 src_reg src0
, src_reg src1
, src_reg one
);
461 void emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
);
462 void emit_bool_comparison(unsigned int op
, dst_reg dst
, src_reg src0
, src_reg src1
);
463 void emit_if_gen6(ir_if
*ir
);
465 void emit_minmax(uint32_t condmod
, dst_reg dst
, src_reg src0
, src_reg src1
);
467 void emit_block_move(dst_reg
*dst
, src_reg
*src
,
468 const struct glsl_type
*type
, uint32_t predicate
);
470 void emit_constant_values(dst_reg
*dst
, ir_constant
*value
);
473 * Emit the correct dot-product instruction for the type of arguments
475 void emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
);
477 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
478 dst_reg dst
, src_reg src0
);
480 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
481 dst_reg dst
, src_reg src0
, src_reg src1
);
483 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
484 dst_reg dst
, const src_reg
&src
);
486 src_reg
fix_3src_operand(src_reg src
);
488 void emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
);
489 void emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
);
490 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src
);
491 void emit_math2_gen6(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
492 void emit_math2_gen4(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
493 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
494 src_reg
fix_math_operand(src_reg src
);
496 void emit_pack_half_2x16(dst_reg dst
, src_reg src0
);
497 void emit_unpack_half_2x16(dst_reg dst
, src_reg src0
);
499 void swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
);
501 void emit_ndc_computation();
502 void emit_psiz_and_flags(struct brw_reg reg
);
503 void emit_clip_distances(dst_reg reg
, int offset
);
504 void emit_generic_urb_slot(dst_reg reg
, int varying
);
505 void emit_urb_slot(int mrf
, int varying
);
507 void emit_shader_time_begin();
508 void emit_shader_time_end();
509 void emit_shader_time_write(enum shader_time_shader_type type
,
512 src_reg
get_scratch_offset(vec4_instruction
*inst
,
513 src_reg
*reladdr
, int reg_offset
);
514 src_reg
get_pull_constant_offset(vec4_instruction
*inst
,
515 src_reg
*reladdr
, int reg_offset
);
516 void emit_scratch_read(vec4_instruction
*inst
,
520 void emit_scratch_write(vec4_instruction
*inst
,
522 void emit_pull_constant_load(vec4_instruction
*inst
,
527 bool try_emit_sat(ir_expression
*ir
);
528 bool try_emit_mad(ir_expression
*ir
, int mul_arg
);
529 void resolve_ud_negate(src_reg
*reg
);
531 src_reg
get_timestamp();
533 bool process_move_condition(ir_rvalue
*ir
);
535 void dump_instruction(backend_instruction
*inst
);
539 void lower_attributes_to_hw_regs(const int *attribute_map
);
540 virtual dst_reg
*make_reg_for_system_value(ir_variable
*ir
) = 0;
541 virtual void setup_payload() = 0;
542 virtual void emit_prolog() = 0;
543 virtual void emit_program_code() = 0;
544 virtual void emit_thread_end() = 0;
545 virtual void emit_urb_write_header(int mrf
) = 0;
546 virtual vec4_instruction
*emit_urb_write_opcode(bool complete
) = 0;
547 virtual int compute_array_stride(ir_dereference_array
*ir
);
549 const bool debug_flag
;
552 class vec4_vs_visitor
: public vec4_visitor
555 vec4_vs_visitor(struct brw_context
*brw
,
556 struct brw_vs_compile
*vs_compile
,
557 struct brw_vs_prog_data
*vs_prog_data
,
558 struct gl_shader_program
*prog
,
559 struct brw_shader
*shader
,
563 virtual dst_reg
*make_reg_for_system_value(ir_variable
*ir
);
564 virtual void setup_payload();
565 virtual void emit_prolog();
566 virtual void emit_program_code();
567 virtual void emit_thread_end();
568 virtual void emit_urb_write_header(int mrf
);
569 virtual vec4_instruction
*emit_urb_write_opcode(bool complete
);
572 int setup_attributes(int payload_reg
);
573 void setup_vp_regs();
574 dst_reg
get_vp_dst_reg(const prog_dst_register
&dst
);
575 src_reg
get_vp_src_reg(const prog_src_register
&src
);
577 struct brw_vs_compile
* const vs_compile
;
578 struct brw_vs_prog_data
* const vs_prog_data
;
579 src_reg
*vp_temp_regs
;
584 * The vertex shader code generator.
586 * Translates VS IR to actual i965 assembly code.
591 vec4_generator(struct brw_context
*brw
,
592 struct gl_shader_program
*shader_prog
,
593 struct gl_program
*prog
,
594 struct brw_vec4_prog_data
*prog_data
,
599 const unsigned *generate_assembly(exec_list
*insts
, unsigned *asm_size
);
602 void generate_code(exec_list
*instructions
);
603 void generate_vec4_instruction(vec4_instruction
*inst
,
605 struct brw_reg
*src
);
607 void generate_math1_gen4(vec4_instruction
*inst
,
610 void generate_math1_gen6(vec4_instruction
*inst
,
613 void generate_math2_gen4(vec4_instruction
*inst
,
616 struct brw_reg src1
);
617 void generate_math2_gen6(vec4_instruction
*inst
,
620 struct brw_reg src1
);
621 void generate_math2_gen7(vec4_instruction
*inst
,
624 struct brw_reg src1
);
626 void generate_tex(vec4_instruction
*inst
,
630 void generate_urb_write(vec4_instruction
*inst
);
631 void generate_oword_dual_block_offsets(struct brw_reg m1
,
632 struct brw_reg index
);
633 void generate_scratch_write(vec4_instruction
*inst
,
636 struct brw_reg index
);
637 void generate_scratch_read(vec4_instruction
*inst
,
639 struct brw_reg index
);
640 void generate_pull_constant_load(vec4_instruction
*inst
,
642 struct brw_reg index
,
643 struct brw_reg offset
);
644 void generate_pull_constant_load_gen7(vec4_instruction
*inst
,
646 struct brw_reg surf_index
,
647 struct brw_reg offset
);
648 void generate_unpack_flags(vec4_instruction
*inst
,
651 void mark_surface_used(unsigned surf_index
);
653 struct brw_context
*brw
;
654 struct gl_context
*ctx
;
656 struct brw_compile
*p
;
658 struct gl_shader_program
*shader_prog
;
659 struct gl_shader
*shader
;
660 const struct gl_program
*prog
;
662 struct brw_vec4_prog_data
*prog_data
;
665 const bool debug_flag
;
668 } /* namespace brw */
669 #endif /* __cplusplus */
671 #endif /* BRW_VEC4_H */