2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
34 #include "brw_context.h"
45 * Common helper for constructing swizzles. When only a subset of
46 * channels of a vec4 are used, we don't want to reference the other
47 * channels, as that will tell optimization passes that those other
51 swizzle_for_size(int size
)
53 static const unsigned size_swizzles
[4] = {
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
56 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
57 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
60 assert((size
>= 1) && (size
<= 4));
61 return size_swizzles
[size
- 1];
65 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
66 GRF
= BRW_GENERAL_REGISTER_FILE
,
67 MRF
= BRW_MESSAGE_REGISTER_FILE
,
68 IMM
= BRW_IMMEDIATE_VALUE
,
69 HW_REG
, /* a struct brw_reg */
71 UNIFORM
, /* prog_data->params[hw_reg] */
78 /** Register file: ARF, GRF, MRF, IMM. */
79 enum register_file file
;
80 /** virtual register number. 0 = fixed hw reg */
82 /** Offset within the virtual register. */
84 /** Register type. BRW_REGISTER_TYPE_* */
86 struct brw_reg fixed_hw_reg
;
88 /** Value for file == BRW_IMMMEDIATE_FILE */
96 class src_reg
: public reg
99 /* Callers of this ralloc-based new need not call delete. It's
100 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
101 static void* operator new(size_t size
, void *ctx
)
105 node
= ralloc_size(ctx
, size
);
106 assert(node
!= NULL
);
113 memset(this, 0, sizeof(*this));
115 this->file
= BAD_FILE
;
118 src_reg(register_file file
, int reg
, const glsl_type
*type
)
124 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
125 this->swizzle
= swizzle_for_size(type
->vector_elements
);
127 this->swizzle
= SWIZZLE_XYZW
;
130 /** Generic unset register constructor. */
141 this->type
= BRW_REGISTER_TYPE_F
;
150 this->type
= BRW_REGISTER_TYPE_UD
;
159 this->type
= BRW_REGISTER_TYPE_D
;
163 bool equals(src_reg
*r
);
164 bool is_zero() const;
167 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
169 explicit src_reg(dst_reg reg
);
171 GLuint swizzle
; /**< SWIZZLE_XYZW swizzles from Mesa. */
178 class dst_reg
: public reg
181 /* Callers of this ralloc-based new need not call delete. It's
182 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
183 static void* operator new(size_t size
, void *ctx
)
187 node
= ralloc_size(ctx
, size
);
188 assert(node
!= NULL
);
195 memset(this, 0, sizeof(*this));
196 this->file
= BAD_FILE
;
197 this->writemask
= WRITEMASK_XYZW
;
205 dst_reg(register_file file
, int reg
)
213 dst_reg(register_file file
, int reg
, const glsl_type
*type
, int writemask
)
219 this->type
= brw_type_for_base_type(type
);
220 this->writemask
= writemask
;
223 dst_reg(struct brw_reg reg
)
228 this->fixed_hw_reg
= reg
;
231 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
233 explicit dst_reg(src_reg reg
);
235 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
240 class vec4_instruction
: public exec_node
{
242 /* Callers of this ralloc-based new need not call delete. It's
243 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
244 static void* operator new(size_t size
, void *ctx
)
248 node
= rzalloc_size(ctx
, size
);
249 assert(node
!= NULL
);
254 vec4_instruction(vec4_visitor
*v
, enum opcode opcode
,
255 dst_reg dst
= dst_reg(),
256 src_reg src0
= src_reg(),
257 src_reg src1
= src_reg(),
258 src_reg src2
= src_reg());
260 struct brw_reg
get_dst(void);
261 struct brw_reg
get_src(int i
);
263 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
268 bool predicate_inverse
;
271 int conditional_mod
; /**< BRW_CONDITIONAL_* */
274 uint32_t texture_offset
; /**< Texture Offset bitfield */
275 int target
; /**< MRT target. */
280 int mlen
; /**< SEND message length */
281 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
283 uint32_t offset
; /* spill/unspill offset */
285 * Annotation for the generated IR. One of the two can be set.
288 const char *annotation
;
294 class vec4_visitor
: public ir_visitor
297 vec4_visitor(struct brw_vs_compile
*c
,
298 struct gl_shader_program
*prog
, struct brw_shader
*shader
);
303 return dst_reg(brw_null_reg());
308 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
311 struct brw_context
*brw
;
312 const struct gl_vertex_program
*vp
;
313 struct intel_context
*intel
;
314 struct gl_context
*ctx
;
315 struct brw_vs_compile
*c
;
316 struct brw_vs_prog_data
*prog_data
;
317 struct brw_compile
*p
;
318 struct brw_shader
*shader
;
319 struct gl_shader_program
*prog
;
321 exec_list instructions
;
327 * GLSL IR currently being processed, which is associated with our
328 * driver IR instructions for debugging purposes.
330 ir_instruction
*base_ir
;
331 const char *current_annotation
;
333 int *virtual_grf_sizes
;
334 int virtual_grf_count
;
335 int virtual_grf_array_size
;
336 int first_non_payload_grf
;
337 int *virtual_grf_def
;
338 int *virtual_grf_use
;
339 dst_reg userplane
[MAX_CLIP_PLANES
];
342 * This is the size to be used for an array with an element per
345 int virtual_grf_reg_count
;
346 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
347 int *virtual_grf_reg_map
;
349 bool live_intervals_valid
;
351 dst_reg
*variable_storage(ir_variable
*var
);
353 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
355 src_reg
src_reg_for_float(float val
);
358 * \name Visit methods
360 * As typical for the visitor pattern, there must be one \c visit method for
361 * each concrete subclass of \c ir_instruction. Virtual base classes within
362 * the hierarchy should not have \c visit methods.
365 virtual void visit(ir_variable
*);
366 virtual void visit(ir_loop
*);
367 virtual void visit(ir_loop_jump
*);
368 virtual void visit(ir_function_signature
*);
369 virtual void visit(ir_function
*);
370 virtual void visit(ir_expression
*);
371 virtual void visit(ir_swizzle
*);
372 virtual void visit(ir_dereference_variable
*);
373 virtual void visit(ir_dereference_array
*);
374 virtual void visit(ir_dereference_record
*);
375 virtual void visit(ir_assignment
*);
376 virtual void visit(ir_constant
*);
377 virtual void visit(ir_call
*);
378 virtual void visit(ir_return
*);
379 virtual void visit(ir_discard
*);
380 virtual void visit(ir_texture
*);
381 virtual void visit(ir_if
*);
386 /* Regs for vertex results. Generated at ir_variable visiting time
387 * for the ir->location's used.
389 dst_reg output_reg
[BRW_VERT_RESULT_MAX
];
390 const char *output_reg_annotation
[BRW_VERT_RESULT_MAX
];
391 int uniform_size
[MAX_UNIFORMS
];
392 int uniform_vector_size
[MAX_UNIFORMS
];
395 struct hash_table
*variable_ht
;
398 void fail(const char *msg
, ...);
400 int virtual_grf_alloc(int size
);
401 void setup_uniform_clipplane_values();
402 int setup_uniform_values(int loc
, const glsl_type
*type
);
403 void setup_builtin_uniform_values(ir_variable
*ir
);
404 int setup_attributes(int payload_reg
);
405 int setup_uniforms(int payload_reg
);
406 void setup_payload();
407 void reg_allocate_trivial();
409 void move_grf_array_access_to_scratch();
410 void move_uniform_array_access_to_pull_constants();
411 void move_push_constants_to_pull_constants();
412 void split_uniform_registers();
413 void pack_uniform_registers();
414 void calculate_live_intervals();
415 bool dead_code_eliminate();
416 bool virtual_grf_interferes(int a
, int b
);
417 bool opt_copy_propagation();
418 bool opt_algebraic();
419 bool opt_compute_to_mrf();
421 vec4_instruction
*emit(vec4_instruction
*inst
);
423 vec4_instruction
*emit(enum opcode opcode
);
425 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
, src_reg src0
);
427 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
428 src_reg src0
, src_reg src1
);
430 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
431 src_reg src0
, src_reg src1
, src_reg src2
);
433 vec4_instruction
*emit_before(vec4_instruction
*inst
,
434 vec4_instruction
*new_inst
);
436 vec4_instruction
*MOV(dst_reg dst
, src_reg src0
);
437 vec4_instruction
*NOT(dst_reg dst
, src_reg src0
);
438 vec4_instruction
*RNDD(dst_reg dst
, src_reg src0
);
439 vec4_instruction
*RNDE(dst_reg dst
, src_reg src0
);
440 vec4_instruction
*RNDZ(dst_reg dst
, src_reg src0
);
441 vec4_instruction
*FRC(dst_reg dst
, src_reg src0
);
442 vec4_instruction
*ADD(dst_reg dst
, src_reg src0
, src_reg src1
);
443 vec4_instruction
*MUL(dst_reg dst
, src_reg src0
, src_reg src1
);
444 vec4_instruction
*MACH(dst_reg dst
, src_reg src0
, src_reg src1
);
445 vec4_instruction
*MAC(dst_reg dst
, src_reg src0
, src_reg src1
);
446 vec4_instruction
*AND(dst_reg dst
, src_reg src0
, src_reg src1
);
447 vec4_instruction
*OR(dst_reg dst
, src_reg src0
, src_reg src1
);
448 vec4_instruction
*XOR(dst_reg dst
, src_reg src0
, src_reg src1
);
449 vec4_instruction
*DP3(dst_reg dst
, src_reg src0
, src_reg src1
);
450 vec4_instruction
*DP4(dst_reg dst
, src_reg src0
, src_reg src1
);
451 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
453 vec4_instruction
*IF(src_reg src0
, src_reg src1
, uint32_t condition
);
454 vec4_instruction
*IF(uint32_t predicate
);
455 vec4_instruction
*PULL_CONSTANT_LOAD(dst_reg dst
, src_reg index
);
456 vec4_instruction
*SCRATCH_READ(dst_reg dst
, src_reg index
);
457 vec4_instruction
*SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
);
459 int implied_mrf_writes(vec4_instruction
*inst
);
461 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
464 vec4_instruction
*pre_rhs_inst
,
465 vec4_instruction
*last_rhs_inst
);
467 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
468 void visit_instructions(const exec_list
*list
);
470 void emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
);
471 void emit_bool_comparison(unsigned int op
, dst_reg dst
, src_reg src0
, src_reg src1
);
472 void emit_if_gen6(ir_if
*ir
);
474 void emit_block_move(dst_reg
*dst
, src_reg
*src
,
475 const struct glsl_type
*type
, uint32_t predicate
);
477 void emit_constant_values(dst_reg
*dst
, ir_constant
*value
);
480 * Emit the correct dot-product instruction for the type of arguments
482 void emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
);
484 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
485 dst_reg dst
, src_reg src0
);
487 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
488 dst_reg dst
, src_reg src0
, src_reg src1
);
490 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
491 dst_reg dst
, const src_reg
&src
);
493 void emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
);
494 void emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
);
495 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src
);
496 void emit_math2_gen6(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
497 void emit_math2_gen4(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
498 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
500 void swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
);
502 void emit_ndc_computation();
503 void emit_psiz_and_flags(struct brw_reg reg
);
504 void emit_clip_distances(struct brw_reg reg
, int offset
);
505 void emit_generic_urb_slot(dst_reg reg
, int vert_result
);
506 void emit_urb_slot(int mrf
, int vert_result
);
507 void emit_urb_writes(void);
509 src_reg
get_scratch_offset(vec4_instruction
*inst
,
510 src_reg
*reladdr
, int reg_offset
);
511 src_reg
get_pull_constant_offset(vec4_instruction
*inst
,
512 src_reg
*reladdr
, int reg_offset
);
513 void emit_scratch_read(vec4_instruction
*inst
,
517 void emit_scratch_write(vec4_instruction
*inst
,
521 void emit_pull_constant_load(vec4_instruction
*inst
,
526 bool try_emit_sat(ir_expression
*ir
);
527 void resolve_ud_negate(src_reg
*reg
);
529 bool process_move_condition(ir_rvalue
*ir
);
531 void generate_code();
532 void generate_vs_instruction(vec4_instruction
*inst
,
534 struct brw_reg
*src
);
536 void generate_math1_gen4(vec4_instruction
*inst
,
539 void generate_math1_gen6(vec4_instruction
*inst
,
542 void generate_math2_gen4(vec4_instruction
*inst
,
545 struct brw_reg src1
);
546 void generate_math2_gen6(vec4_instruction
*inst
,
549 struct brw_reg src1
);
550 void generate_math2_gen7(vec4_instruction
*inst
,
553 struct brw_reg src1
);
555 void generate_tex(vec4_instruction
*inst
,
559 void generate_urb_write(vec4_instruction
*inst
);
560 void generate_oword_dual_block_offsets(struct brw_reg m1
,
561 struct brw_reg index
);
562 void generate_scratch_write(vec4_instruction
*inst
,
565 struct brw_reg index
);
566 void generate_scratch_read(vec4_instruction
*inst
,
568 struct brw_reg index
);
569 void generate_pull_constant_load(vec4_instruction
*inst
,
571 struct brw_reg index
);
574 } /* namespace brw */
576 #endif /* BRW_VEC4_H */