2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_shader.h"
28 #include "brw_program.h"
31 #include "brw_ir_vec4.h"
34 #include "compiler/glsl/ir.h"
35 #include "compiler/nir/nir.h"
43 brw_vec4_generate_assembly(const struct brw_compiler
*compiler
,
46 const nir_shader
*nir
,
47 struct brw_vue_prog_data
*prog_data
,
48 const struct cfg_t
*cfg
,
49 unsigned *out_assembly_size
);
56 class vec4_live_variables
;
59 * The vertex shader front-end.
61 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
62 * fixed-function) into VS IR.
64 class vec4_visitor
: public backend_shader
67 vec4_visitor(const struct brw_compiler
*compiler
,
69 const struct brw_sampler_prog_key_data
*key
,
70 struct brw_vue_prog_data
*prog_data
,
71 const nir_shader
*shader
,
74 int shader_time_index
);
75 virtual ~vec4_visitor();
79 return dst_reg(brw_null_reg());
84 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF
));
89 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
94 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
97 const struct brw_sampler_prog_key_data
* const key_tex
;
98 struct brw_vue_prog_data
* const prog_data
;
103 * GLSL IR currently being processed, which is associated with our
104 * driver IR instructions for debugging purposes.
107 const char *current_annotation
;
109 int first_non_payload_grf
;
110 unsigned int max_grf
;
111 int *virtual_grf_start
;
112 int *virtual_grf_end
;
113 brw::vec4_live_variables
*live_intervals
;
114 dst_reg userplane
[MAX_CLIP_PLANES
];
116 bool need_all_constants_in_pull_buffer
;
118 /* Regs for vertex results. Generated at ir_variable visiting time
119 * for the ir->location's used.
121 dst_reg output_reg
[VARYING_SLOT_TESS_MAX
][4];
122 unsigned output_num_components
[VARYING_SLOT_TESS_MAX
][4];
123 const char *output_reg_annotation
[VARYING_SLOT_TESS_MAX
];
126 src_reg shader_start_time
;
129 void fail(const char *msg
, ...);
131 int setup_uniforms(int payload_reg
);
133 bool reg_allocate_trivial();
135 void evaluate_spill_costs(float *spill_costs
, bool *no_spill
);
136 int choose_spill_reg(struct ra_graph
*g
);
137 void spill_reg(int spill_reg
);
138 void move_grf_array_access_to_scratch();
139 void move_uniform_array_access_to_pull_constants();
140 void move_push_constants_to_pull_constants();
141 void split_uniform_registers();
142 void pack_uniform_registers();
143 void calculate_live_intervals();
144 void invalidate_live_intervals();
145 void split_virtual_grfs();
146 bool opt_vector_float();
147 bool opt_reduce_swizzle();
148 bool dead_code_eliminate();
149 int var_range_start(unsigned v
, unsigned n
) const;
150 int var_range_end(unsigned v
, unsigned n
) const;
151 bool virtual_grf_interferes(int a
, int b
);
152 bool opt_cmod_propagation();
153 bool opt_copy_propagation(bool do_constant_prop
= true);
154 bool opt_cse_local(bblock_t
*block
);
156 bool opt_algebraic();
157 bool opt_register_coalesce();
158 bool eliminate_find_live_channel();
159 bool is_dep_ctrl_unsafe(const vec4_instruction
*inst
);
160 void opt_set_dependency_control();
161 void opt_schedule_instructions();
162 void convert_to_hw_regs();
164 bool is_supported_64bit_region(vec4_instruction
*inst
, unsigned arg
);
165 bool lower_simd_width();
167 bool lower_64bit_mad_to_mul_add();
168 void apply_logical_swizzle(struct brw_reg
*hw_reg
,
169 vec4_instruction
*inst
, int arg
);
171 vec4_instruction
*emit(vec4_instruction
*inst
);
173 vec4_instruction
*emit(enum opcode opcode
);
174 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
);
175 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
,
176 const src_reg
&src0
);
177 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
,
178 const src_reg
&src0
, const src_reg
&src1
);
179 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
,
180 const src_reg
&src0
, const src_reg
&src1
,
181 const src_reg
&src2
);
183 vec4_instruction
*emit_before(bblock_t
*block
,
184 vec4_instruction
*inst
,
185 vec4_instruction
*new_inst
);
187 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
188 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
189 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
211 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
212 enum brw_conditional_mod condition
);
213 vec4_instruction
*IF(src_reg src0
, src_reg src1
,
214 enum brw_conditional_mod condition
);
215 vec4_instruction
*IF(enum brw_predicate predicate
);
235 int implied_mrf_writes(vec4_instruction
*inst
);
237 vec4_instruction
*emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
238 src_reg src0
, src_reg src1
);
240 vec4_instruction
*emit_lrp(const dst_reg
&dst
, const src_reg
&x
,
241 const src_reg
&y
, const src_reg
&a
);
244 * Copy any live channel from \p src to the first channel of the
247 src_reg
emit_uniformize(const src_reg
&src
);
249 src_reg
fix_3src_operand(const src_reg
&src
);
250 src_reg
resolve_source_modifiers(const src_reg
&src
);
252 vec4_instruction
*emit_math(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
253 const src_reg
&src1
= src_reg());
255 src_reg
fix_math_operand(const src_reg
&src
);
257 void emit_pack_half_2x16(dst_reg dst
, src_reg src0
);
258 void emit_unpack_half_2x16(dst_reg dst
, src_reg src0
);
259 void emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
);
260 void emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
);
261 void emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
);
262 void emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
);
264 void emit_texture(ir_texture_opcode op
,
266 const glsl_type
*dest_type
,
268 int coord_components
,
269 src_reg shadow_comparator
,
270 src_reg lod
, src_reg lod2
,
271 src_reg sample_index
,
272 uint32_t constant_offset
,
273 src_reg offset_value
,
275 uint32_t surface
, src_reg surface_reg
,
276 src_reg sampler_reg
);
278 src_reg
emit_mcs_fetch(const glsl_type
*coordinate_type
, src_reg coordinate
,
280 void emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
);
282 void emit_ndc_computation();
283 void emit_psiz_and_flags(dst_reg reg
);
284 vec4_instruction
*emit_generic_urb_slot(dst_reg reg
, int varying
, int comp
);
285 virtual void emit_urb_slot(dst_reg reg
, int varying
);
287 void emit_shader_time_begin();
288 void emit_shader_time_end();
289 void emit_shader_time_write(int shader_time_subindex
, src_reg value
);
291 src_reg
get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
292 src_reg
*reladdr
, int reg_offset
);
293 void emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
297 void emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
299 void emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
304 void emit_pull_constant_load_reg(dst_reg dst
,
307 bblock_t
*before_block
,
308 vec4_instruction
*before_inst
);
309 src_reg
emit_resolve_reladdr(int scratch_loc
[], bblock_t
*block
,
310 vec4_instruction
*inst
, src_reg src
);
312 void resolve_ud_negate(src_reg
*reg
);
316 src_reg
get_timestamp();
318 void dump_instruction(backend_instruction
*inst
);
319 void dump_instruction(backend_instruction
*inst
, FILE *file
);
321 bool is_high_sampler(src_reg sampler
);
323 bool optimize_predicate(nir_alu_instr
*instr
, enum brw_predicate
*predicate
);
325 void emit_conversion_from_double(dst_reg dst
, src_reg src
, bool saturate
,
326 brw_reg_type single_type
);
327 void emit_conversion_to_double(dst_reg dst
, src_reg src
, bool saturate
,
328 brw_reg_type single_type
);
330 src_reg
setup_imm_df(double v
);
332 vec4_instruction
*shuffle_64bit_data(dst_reg dst
, src_reg src
,
334 bblock_t
*block
= NULL
,
335 vec4_instruction
*ref
= NULL
);
337 virtual void emit_nir_code();
338 virtual void nir_setup_uniforms();
339 virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
);
340 virtual void nir_setup_system_values();
341 virtual void nir_emit_impl(nir_function_impl
*impl
);
342 virtual void nir_emit_cf_list(exec_list
*list
);
343 virtual void nir_emit_if(nir_if
*if_stmt
);
344 virtual void nir_emit_loop(nir_loop
*loop
);
345 virtual void nir_emit_block(nir_block
*block
);
346 virtual void nir_emit_instr(nir_instr
*instr
);
347 virtual void nir_emit_load_const(nir_load_const_instr
*instr
);
348 virtual void nir_emit_intrinsic(nir_intrinsic_instr
*instr
);
349 virtual void nir_emit_alu(nir_alu_instr
*instr
);
350 virtual void nir_emit_jump(nir_jump_instr
*instr
);
351 virtual void nir_emit_texture(nir_tex_instr
*instr
);
352 virtual void nir_emit_undef(nir_ssa_undef_instr
*instr
);
353 virtual void nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
);
355 dst_reg
get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
);
356 dst_reg
get_nir_dest(const nir_dest
&dest
, nir_alu_type type
);
357 dst_reg
get_nir_dest(const nir_dest
&dest
);
358 src_reg
get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
359 unsigned num_components
= 4);
360 src_reg
get_nir_src(const nir_src
&src
, nir_alu_type type
,
361 unsigned num_components
= 4);
362 src_reg
get_nir_src(const nir_src
&src
,
363 unsigned num_components
= 4);
364 src_reg
get_indirect_offset(nir_intrinsic_instr
*instr
);
366 virtual dst_reg
*make_reg_for_system_value(int location
) = 0;
369 dst_reg
*nir_ssa_values
;
370 dst_reg
*nir_system_values
;
374 void lower_attributes_to_hw_regs(const int *attribute_map
,
376 void setup_payload_interference(struct ra_graph
*g
, int first_payload_node
,
378 virtual void setup_payload() = 0;
379 virtual void emit_prolog() = 0;
380 virtual void emit_thread_end() = 0;
381 virtual void emit_urb_write_header(int mrf
) = 0;
382 virtual vec4_instruction
*emit_urb_write_opcode(bool complete
) = 0;
383 virtual void gs_emit_vertex(int stream_id
);
384 virtual void gs_end_primitive();
388 * If true, then register allocation should fail instead of spilling.
390 const bool no_spills
;
392 int shader_time_index
;
394 unsigned last_scratch
; /**< measured in 32-byte (register size) units */
397 } /* namespace brw */
398 #endif /* __cplusplus */
400 #endif /* BRW_VEC4_H */