src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31
  32 extern "C" {
  33 #include "brw_vs.h"
  34 #include "brw_context.h"
  35 #include "brw_eu.h"
  36 };
  37
  38 #include "../glsl/ir.h"
  39
  40 namespace brw {
  41
  42 class dst_reg;
  43
  44 /**
  45  * Common helper for constructing swizzles.  When only a subset of
  46  * channels of a vec4 are used, we don't want to reference the other
  47  * channels, as that will tell optimization passes that those other
  48  * channels are used.
  49  */
  50 static int
  51 swizzle_for_size(int size)
  52 {
  53    int size_swizzles[4] = {
  54       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
  55       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
  56       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
  57       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
  58    };
  59
  60    assert((size >= 1) && (size <= 4));
  61    return size_swizzles[size - 1];
  62 }
  63
  64 enum register_file {
  65    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
  66    GRF = BRW_GENERAL_REGISTER_FILE,
  67    MRF = BRW_MESSAGE_REGISTER_FILE,
  68    IMM = BRW_IMMEDIATE_VALUE,
  69    HW_REG, /* a struct brw_reg */
  70    ATTR,
  71    UNIFORM, /* prog_data->params[hw_reg] */
  72    BAD_FILE
  73 };
  74
  75 class reg
  76 {
  77 public:
  78    /** Register file: ARF, GRF, MRF, IMM. */
  79    enum register_file file;
  80    /** virtual register number.  0 = fixed hw reg */
  81    int reg;
  82    /** Offset within the virtual register. */
  83    int reg_offset;
  84    /** Register type.  BRW_REGISTER_TYPE_* */
  85    int type;
  86    bool sechalf;
  87    struct brw_reg fixed_hw_reg;
  88    int smear; /* -1, or a channel of the reg to smear to all channels. */
  89
  90    /** Value for file == BRW_IMMMEDIATE_FILE */
  91    union {
  92       int32_t i;
  93       uint32_t u;
  94       float f;
  95    } imm;
  96 };
  97
  98 class src_reg : public reg
  99 {
 100 public:
 101    /* Callers of this ralloc-based new need not call delete. It's
 102     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 103    static void* operator new(size_t size, void *ctx)
 104    {
 105       void *node;
 106
 107       node = ralloc_size(ctx, size);
 108       assert(node != NULL);
 109
 110       return node;
 111    }
 112
 113    void init()
 114    {
 115       memset(this, 0, sizeof(*this));
 116
 117       this->file = BAD_FILE;
 118    }
 119
 120    src_reg(register_file file, int reg, const glsl_type *type)
 121    {
 122       init();
 123
 124       this->file = file;
 125       this->reg = reg;
 126       if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
 127          this->swizzle = swizzle_for_size(type->vector_elements);
 128       else
 129          this->swizzle = SWIZZLE_XYZW;
 130    }
 131
 132    /** Generic unset register constructor. */
 133    src_reg()
 134    {
 135       init();
 136    }
 137
 138    src_reg(float f)
 139    {
 140       init();
 141
 142       this->file = IMM;
 143       this->type = BRW_REGISTER_TYPE_F;
 144       this->imm.f = f;
 145    }
 146
 147    src_reg(uint32_t u)
 148    {
 149       init();
 150
 151       this->file = IMM;
 152       this->type = BRW_REGISTER_TYPE_UD;
 153       this->imm.f = u;
 154    }
 155
 156    src_reg(int32_t i)
 157    {
 158       init();
 159
 160       this->file = IMM;
 161       this->type = BRW_REGISTER_TYPE_D;
 162       this->imm.i = i;
 163    }
 164
 165    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 166
 167    explicit src_reg(dst_reg reg);
 168
 169    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 170    bool negate;
 171    bool abs;
 172
 173    src_reg *reladdr;
 174 };
 175
 176 class dst_reg : public reg
 177 {
 178 public:
 179    /* Callers of this ralloc-based new need not call delete. It's
 180     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 181    static void* operator new(size_t size, void *ctx)
 182    {
 183       void *node;
 184
 185       node = ralloc_size(ctx, size);
 186       assert(node != NULL);
 187
 188       return node;
 189    }
 190
 191    void init()
 192    {
 193       memset(this, 0, sizeof(*this));
 194       this->file = BAD_FILE;
 195       this->writemask = WRITEMASK_XYZW;
 196    }
 197
 198    dst_reg()
 199    {
 200       init();
 201    }
 202
 203    dst_reg(register_file file, int reg)
 204    {
 205       init();
 206
 207       this->file = file;
 208       this->reg = reg;
 209    }
 210
 211    dst_reg(struct brw_reg reg)
 212    {
 213       init();
 214
 215       this->file = HW_REG;
 216       this->fixed_hw_reg = reg;
 217    }
 218
 219    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 220
 221    explicit dst_reg(src_reg reg);
 222
 223    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 224
 225    src_reg *reladdr;
 226 };
 227
 228 class vec4_instruction : public exec_node {
 229 public:
 230    /* Callers of this ralloc-based new need not call delete. It's
 231     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 232    static void* operator new(size_t size, void *ctx)
 233    {
 234       void *node;
 235
 236       node = rzalloc_size(ctx, size);
 237       assert(node != NULL);
 238
 239       return node;
 240    }
 241
 242    struct brw_reg get_dst(void);
 243    struct brw_reg get_src(int i);
 244
 245    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 246    dst_reg dst;
 247    src_reg src[3];
 248
 249    bool saturate;
 250    bool predicate_inverse;
 251    uint32_t predicate;
 252
 253    int conditional_mod; /**< BRW_CONDITIONAL_* */
 254
 255    int sampler;
 256    int target; /**< MRT target. */
 257    bool shadow_compare;
 258
 259    bool eot;
 260    bool header_present;
 261    int mlen; /**< SEND message length */
 262    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 263
 264    uint32_t offset; /* spill/unspill offset */
 265    /** @{
 266     * Annotation for the generated IR.  One of the two can be set.
 267     */
 268    ir_instruction *ir;
 269    const char *annotation;
 270 };
 271
 272 class vec4_visitor : public ir_visitor
 273 {
 274 public:
 275    vec4_visitor(struct brw_vs_compile *c,
 276                 struct gl_shader_program *prog, struct brw_shader *shader);
 277    ~vec4_visitor();
 278
 279    dst_reg dst_null_f()
 280    {
 281       return dst_reg(brw_null_reg());
 282    }
 283
 284    dst_reg dst_null_d()
 285    {
 286       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 287    }
 288
 289    dst_reg dst_null_cmp()
 290    {
 291       if (intel->gen > 4)
 292          return dst_null_d();
 293       else
 294          return dst_null_f();
 295    }
 296
 297    struct brw_context *brw;
 298    const struct gl_vertex_program *vp;
 299    struct intel_context *intel;
 300    struct gl_context *ctx;
 301    struct brw_vs_compile *c;
 302    struct brw_vs_prog_data *prog_data;
 303    struct brw_compile *p;
 304    struct brw_shader *shader;
 305    struct gl_shader_program *prog;
 306    void *mem_ctx;
 307    exec_list instructions;
 308
 309    char *fail_msg;
 310    bool failed;
 311
 312    /**
 313     * GLSL IR currently being processed, which is associated with our
 314     * driver IR instructions for debugging purposes.
 315     */
 316    ir_instruction *base_ir;
 317    const char *current_annotation;
 318
 319    int *virtual_grf_sizes;
 320    int virtual_grf_count;
 321    int virtual_grf_array_size;
 322    int first_non_payload_grf;
 323
 324    dst_reg *variable_storage(ir_variable *var);
 325
 326    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 327
 328    src_reg src_reg_for_float(float val);
 329
 330    /**
 331     * \name Visit methods
 332     *
 333     * As typical for the visitor pattern, there must be one \c visit method for
 334     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 335     * the hierarchy should not have \c visit methods.
 336     */
 337    /*@{*/
 338    virtual void visit(ir_variable *);
 339    virtual void visit(ir_loop *);
 340    virtual void visit(ir_loop_jump *);
 341    virtual void visit(ir_function_signature *);
 342    virtual void visit(ir_function *);
 343    virtual void visit(ir_expression *);
 344    virtual void visit(ir_swizzle *);
 345    virtual void visit(ir_dereference_variable  *);
 346    virtual void visit(ir_dereference_array *);
 347    virtual void visit(ir_dereference_record *);
 348    virtual void visit(ir_assignment *);
 349    virtual void visit(ir_constant *);
 350    virtual void visit(ir_call *);
 351    virtual void visit(ir_return *);
 352    virtual void visit(ir_discard *);
 353    virtual void visit(ir_texture *);
 354    virtual void visit(ir_if *);
 355    /*@}*/
 356
 357    src_reg result;
 358
 359    /* Regs for vertex results.  Generated at ir_variable visiting time
 360     * for the ir->location's used.
 361     */
 362    dst_reg output_reg[VERT_RESULT_MAX];
 363    int uniform_size[MAX_UNIFORMS];
 364    int uniforms;
 365
 366    struct hash_table *variable_ht;
 367
 368    bool run(void);
 369    void fail(const char *msg, ...);
 370
 371    int virtual_grf_alloc(int size);
 372    int setup_uniform_values(int loc, const glsl_type *type);
 373    void setup_builtin_uniform_values(ir_variable *ir);
 374    int setup_attributes(int payload_reg);
 375    int setup_uniforms(int payload_reg);
 376    void setup_payload();
 377    void reg_allocate_trivial();
 378    void reg_allocate();
 379    void move_grf_array_access_to_scratch();
 380
 381    vec4_instruction *emit(enum opcode opcode);
 382
 383    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 384
 385    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 386                           src_reg src0, src_reg src1);
 387
 388    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 389                           src_reg src0, src_reg src1, src_reg src2);
 390
 391    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 392    void visit_instructions(const exec_list *list);
 393
 394    void emit_bool_to_cond_code(ir_rvalue *ir);
 395    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 396    void emit_if_gen6(ir_if *ir);
 397
 398    void emit_block_move(dst_reg *dst, src_reg *src,
 399                         const struct glsl_type *type, bool predicated);
 400
 401    void emit_constant_values(dst_reg *dst, ir_constant *value);
 402
 403    /**
 404     * Emit the correct dot-product instruction for the type of arguments
 405     */
 406    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 407
 408    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 409                     dst_reg dst, src_reg src0);
 410
 411    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 412                     dst_reg dst, src_reg src0, src_reg src1);
 413
 414    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 415                  dst_reg dst, const src_reg &src);
 416
 417    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 418    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 419    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 420    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 421    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 422    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 423
 424    int emit_vue_header_gen6(int header_mrf);
 425    int emit_vue_header_gen4(int header_mrf);
 426    void emit_urb_writes(void);
 427
 428    src_reg get_scratch_offset(vec4_instruction *inst,
 429                               src_reg *reladdr, int reg_offset);
 430    void emit_scratch_read(vec4_instruction *inst,
 431                           dst_reg dst,
 432                           src_reg orig_src,
 433                           int base_offset);
 434    void emit_scratch_write(vec4_instruction *inst,
 435                            src_reg temp,
 436                            dst_reg orig_dst,
 437                            int base_offset);
 438
 439    GLboolean try_emit_sat(ir_expression *ir);
 440
 441    bool process_move_condition(ir_rvalue *ir);
 442
 443    void generate_code();
 444    void generate_vs_instruction(vec4_instruction *inst,
 445                                 struct brw_reg dst,
 446                                 struct brw_reg *src);
 447    void generate_math1_gen4(vec4_instruction *inst,
 448                             struct brw_reg dst,
 449                             struct brw_reg src);
 450    void generate_math1_gen6(vec4_instruction *inst,
 451                             struct brw_reg dst,
 452                             struct brw_reg src);
 453    void generate_urb_write(vec4_instruction *inst);
 454 };
 455
 456 } /* namespace brw */
 457
 458 #endif /* BRW_VEC4_H */