src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39
  40 #ifdef __cplusplus
  41 }; /* extern "C" */
  42 #endif
  43
  44 #include "glsl/ir.h"
  45
  46
  47 struct brw_vec4_compile {
  48    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  49 };
  50
  51
  52 struct brw_vec4_prog_key {
  53    GLuint program_string_id;
  54
  55    /**
  56     * True if at least one clip flag is enabled, regardless of whether the
  57     * shader uses clip planes or gl_ClipDistance.
  58     */
  59    GLuint userclip_active:1;
  60
  61    /**
  62     * How many user clipping planes are being uploaded to the vertex shader as
  63     * push constants.
  64     */
  65    GLuint nr_userclip_plane_consts:4;
  66
  67    /**
  68     * True if the shader uses gl_ClipDistance, regardless of whether any clip
  69     * flags are enabled.
  70     */
  71    GLuint uses_clip_distance:1;
  72
  73    GLuint clamp_vertex_color:1;
  74
  75    struct brw_sampler_prog_key_data tex;
  76 };
  77
  78
  79 #ifdef __cplusplus
  80 extern "C" {
  81 #endif
  82
  83 bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
  84                                 const struct brw_vec4_prog_data *b);
  85 void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data);
  86
  87 #ifdef __cplusplus
  88 } /* extern "C" */
  89
  90 namespace brw {
  91
  92 class dst_reg;
  93
  94 unsigned
  95 swizzle_for_size(int size);
  96
  97 class reg
  98 {
  99 public:
 100    /** Register file: GRF, MRF, IMM. */
 101    enum register_file file;
 102    /** virtual register number.  0 = fixed hw reg */
 103    int reg;
 104    /** Offset within the virtual register. */
 105    int reg_offset;
 106    /** Register type.  BRW_REGISTER_TYPE_* */
 107    int type;
 108    struct brw_reg fixed_hw_reg;
 109
 110    /** Value for file == BRW_IMMMEDIATE_FILE */
 111    union {
 112       int32_t i;
 113       uint32_t u;
 114       float f;
 115    } imm;
 116 };
 117
 118 class src_reg : public reg
 119 {
 120 public:
 121    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
 122
 123    void init();
 124
 125    src_reg(register_file file, int reg, const glsl_type *type);
 126    src_reg();
 127    src_reg(float f);
 128    src_reg(uint32_t u);
 129    src_reg(int32_t i);
 130
 131    bool equals(src_reg *r);
 132    bool is_zero() const;
 133    bool is_one() const;
 134
 135    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 136
 137    explicit src_reg(dst_reg reg);
 138
 139    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 140    bool negate;
 141    bool abs;
 142
 143    src_reg *reladdr;
 144 };
 145
 146 class dst_reg : public reg
 147 {
 148 public:
 149    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 150
 151    void init();
 152
 153    dst_reg();
 154    dst_reg(register_file file, int reg);
 155    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 156    dst_reg(struct brw_reg reg);
 157    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 158
 159    explicit dst_reg(src_reg reg);
 160
 161    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 162
 163    src_reg *reladdr;
 164 };
 165
 166 dst_reg
 167 with_writemask(dst_reg const &r, int mask);
 168
 169 class vec4_instruction : public backend_instruction {
 170 public:
 171    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 172
 173    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 174                     dst_reg dst = dst_reg(),
 175                     src_reg src0 = src_reg(),
 176                     src_reg src1 = src_reg(),
 177                     src_reg src2 = src_reg());
 178
 179    struct brw_reg get_dst(void);
 180    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 181
 182    dst_reg dst;
 183    src_reg src[3];
 184
 185    bool saturate;
 186    bool force_writemask_all;
 187    bool no_dd_clear, no_dd_check;
 188
 189    int conditional_mod; /**< BRW_CONDITIONAL_* */
 190
 191    int sampler;
 192    uint32_t texture_offset; /**< Texture Offset bitfield */
 193    int target; /**< MRT target. */
 194    bool shadow_compare;
 195
 196    enum brw_urb_write_flags urb_write_flags;
 197    bool header_present;
 198    int mlen; /**< SEND message length */
 199    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 200
 201    uint32_t offset; /* spill/unspill offset */
 202    /** @{
 203     * Annotation for the generated IR.  One of the two can be set.
 204     */
 205    const void *ir;
 206    const char *annotation;
 207
 208    bool is_send_from_grf();
 209    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 210    void reswizzle_dst(int dst_writemask, int swizzle);
 211
 212    bool depends_on_flags()
 213    {
 214       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 215    }
 216 };
 217
 218 /**
 219  * The vertex shader front-end.
 220  *
 221  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 222  * fixed-function) into VS IR.
 223  */
 224 class vec4_visitor : public backend_visitor
 225 {
 226 public:
 227    vec4_visitor(struct brw_context *brw,
 228                 struct brw_vec4_compile *c,
 229                 struct gl_program *prog,
 230                 const struct brw_vec4_prog_key *key,
 231                 struct brw_vec4_prog_data *prog_data,
 232                 struct gl_shader_program *shader_prog,
 233                 struct brw_shader *shader,
 234                 void *mem_ctx,
 235                 bool debug_flag);
 236    ~vec4_visitor();
 237
 238    dst_reg dst_null_f()
 239    {
 240       return dst_reg(brw_null_reg());
 241    }
 242
 243    dst_reg dst_null_d()
 244    {
 245       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 246    }
 247
 248    dst_reg dst_null_ud()
 249    {
 250       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 251    }
 252
 253    struct brw_vec4_compile *c;
 254    const struct brw_vec4_prog_key *key;
 255    struct brw_vec4_prog_data *prog_data;
 256    unsigned int sanity_param_count;
 257
 258    char *fail_msg;
 259    bool failed;
 260
 261    /**
 262     * GLSL IR currently being processed, which is associated with our
 263     * driver IR instructions for debugging purposes.
 264     */
 265    const void *base_ir;
 266    const char *current_annotation;
 267
 268    int *virtual_grf_sizes;
 269    int virtual_grf_count;
 270    int virtual_grf_array_size;
 271    int first_non_payload_grf;
 272    unsigned int max_grf;
 273    int *virtual_grf_start;
 274    int *virtual_grf_end;
 275    dst_reg userplane[MAX_CLIP_PLANES];
 276
 277    /**
 278     * This is the size to be used for an array with an element per
 279     * reg_offset
 280     */
 281    int virtual_grf_reg_count;
 282    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 283    int *virtual_grf_reg_map;
 284
 285    bool live_intervals_valid;
 286
 287    dst_reg *variable_storage(ir_variable *var);
 288
 289    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 290
 291    bool need_all_constants_in_pull_buffer;
 292
 293    /**
 294     * \name Visit methods
 295     *
 296     * As typical for the visitor pattern, there must be one \c visit method for
 297     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 298     * the hierarchy should not have \c visit methods.
 299     */
 300    /*@{*/
 301    virtual void visit(ir_variable *);
 302    virtual void visit(ir_loop *);
 303    virtual void visit(ir_loop_jump *);
 304    virtual void visit(ir_function_signature *);
 305    virtual void visit(ir_function *);
 306    virtual void visit(ir_expression *);
 307    virtual void visit(ir_swizzle *);
 308    virtual void visit(ir_dereference_variable  *);
 309    virtual void visit(ir_dereference_array *);
 310    virtual void visit(ir_dereference_record *);
 311    virtual void visit(ir_assignment *);
 312    virtual void visit(ir_constant *);
 313    virtual void visit(ir_call *);
 314    virtual void visit(ir_return *);
 315    virtual void visit(ir_discard *);
 316    virtual void visit(ir_texture *);
 317    virtual void visit(ir_if *);
 318    virtual void visit(ir_emit_vertex *);
 319    virtual void visit(ir_end_primitive *);
 320    /*@}*/
 321
 322    src_reg result;
 323
 324    /* Regs for vertex results.  Generated at ir_variable visiting time
 325     * for the ir->location's used.
 326     */
 327    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 328    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 329    int uniform_size[MAX_UNIFORMS];
 330    int uniform_vector_size[MAX_UNIFORMS];
 331    int uniforms;
 332
 333    src_reg shader_start_time;
 334
 335    struct hash_table *variable_ht;
 336
 337    bool run(void);
 338    void fail(const char *msg, ...);
 339
 340    int virtual_grf_alloc(int size);
 341    void setup_uniform_clipplane_values();
 342    void setup_uniform_values(ir_variable *ir);
 343    void setup_builtin_uniform_values(ir_variable *ir);
 344    int setup_uniforms(int payload_reg);
 345    bool reg_allocate_trivial();
 346    bool reg_allocate();
 347    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 348    int choose_spill_reg(struct ra_graph *g);
 349    void spill_reg(int spill_reg);
 350    void move_grf_array_access_to_scratch();
 351    void move_uniform_array_access_to_pull_constants();
 352    void move_push_constants_to_pull_constants();
 353    void split_uniform_registers();
 354    void pack_uniform_registers();
 355    void calculate_live_intervals();
 356    void split_virtual_grfs();
 357    bool dead_code_eliminate();
 358    bool virtual_grf_interferes(int a, int b);
 359    bool opt_copy_propagation();
 360    bool opt_algebraic();
 361    bool opt_register_coalesce();
 362    void opt_set_dependency_control();
 363    void opt_schedule_instructions();
 364
 365    bool can_do_source_mods(vec4_instruction *inst);
 366
 367    vec4_instruction *emit(vec4_instruction *inst);
 368
 369    vec4_instruction *emit(enum opcode opcode);
 370
 371    vec4_instruction *emit(enum opcode opcode, dst_reg dst);
 372
 373    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 374
 375    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 376                           src_reg src0, src_reg src1);
 377
 378    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 379                           src_reg src0, src_reg src1, src_reg src2);
 380
 381    vec4_instruction *emit_before(vec4_instruction *inst,
 382                                  vec4_instruction *new_inst);
 383
 384    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 385    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 386    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 387    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 388    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 389    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 390    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 391    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 392    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 393    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 394    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 395    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 396    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 397    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 398    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 399    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 400    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 401    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 402    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 403    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 404    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 405    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 406                          uint32_t condition);
 407    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 408    vec4_instruction *IF(uint32_t predicate);
 409    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 410    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 411    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 412    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 413    vec4_instruction *BFREV(dst_reg dst, src_reg value);
 414    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
 415    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
 416    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
 417    vec4_instruction *FBH(dst_reg dst, src_reg value);
 418    vec4_instruction *FBL(dst_reg dst, src_reg value);
 419    vec4_instruction *CBIT(dst_reg dst, src_reg value);
 420    vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
 421    vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1);
 422    vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1);
 423
 424    int implied_mrf_writes(vec4_instruction *inst);
 425
 426    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 427                                dst_reg dst,
 428                                src_reg src,
 429                                vec4_instruction *pre_rhs_inst,
 430                                vec4_instruction *last_rhs_inst);
 431
 432    bool try_copy_propagation(vec4_instruction *inst, int arg,
 433                              src_reg *values[4]);
 434
 435    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 436    void visit_instructions(const exec_list *list);
 437
 438    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 439                     src_reg src0, src_reg src1, src_reg one);
 440
 441    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 442    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 443    void emit_if_gen6(ir_if *ir);
 444
 445    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 446
 447    void emit_block_move(dst_reg *dst, src_reg *src,
 448                         const struct glsl_type *type, uint32_t predicate);
 449
 450    void emit_constant_values(dst_reg *dst, ir_constant *value);
 451
 452    /**
 453     * Emit the correct dot-product instruction for the type of arguments
 454     */
 455    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 456
 457    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 458                     dst_reg dst, src_reg src0);
 459
 460    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 461                     dst_reg dst, src_reg src0, src_reg src1);
 462
 463    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 464                  dst_reg dst, const src_reg &src);
 465
 466    src_reg fix_3src_operand(src_reg src);
 467
 468    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 469    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 470    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 471    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 472    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 473    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 474    src_reg fix_math_operand(src_reg src);
 475
 476    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 477    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 478
 479    uint32_t gather_channel(ir_texture *ir, int sampler);
 480    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 481
 482    void emit_ndc_computation();
 483    void emit_psiz_and_flags(struct brw_reg reg);
 484    void emit_clip_distances(dst_reg reg, int offset);
 485    void emit_generic_urb_slot(dst_reg reg, int varying);
 486    void emit_urb_slot(int mrf, int varying);
 487
 488    void emit_shader_time_begin();
 489    void emit_shader_time_end();
 490    void emit_shader_time_write(enum shader_time_shader_type type,
 491                                src_reg value);
 492
 493    src_reg get_scratch_offset(vec4_instruction *inst,
 494                               src_reg *reladdr, int reg_offset);
 495    src_reg get_pull_constant_offset(vec4_instruction *inst,
 496                                     src_reg *reladdr, int reg_offset);
 497    void emit_scratch_read(vec4_instruction *inst,
 498                           dst_reg dst,
 499                           src_reg orig_src,
 500                           int base_offset);
 501    void emit_scratch_write(vec4_instruction *inst,
 502                            int base_offset);
 503    void emit_pull_constant_load(vec4_instruction *inst,
 504                                 dst_reg dst,
 505                                 src_reg orig_src,
 506                                 int base_offset);
 507
 508    bool try_emit_sat(ir_expression *ir);
 509    bool try_emit_mad(ir_expression *ir, int mul_arg);
 510    void resolve_ud_negate(src_reg *reg);
 511
 512    src_reg get_timestamp();
 513
 514    bool process_move_condition(ir_rvalue *ir);
 515
 516    void dump_instruction(backend_instruction *inst);
 517
 518 protected:
 519    void emit_vertex();
 520    void lower_attributes_to_hw_regs(const int *attribute_map);
 521    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 522                                    int reg_node_count);
 523    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 524    virtual void setup_payload() = 0;
 525    virtual void emit_prolog() = 0;
 526    virtual void emit_program_code() = 0;
 527    virtual void emit_thread_end() = 0;
 528    virtual void emit_urb_write_header(int mrf) = 0;
 529    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 530    virtual int compute_array_stride(ir_dereference_array *ir);
 531
 532    const bool debug_flag;
 533 };
 534
 535
 536 /**
 537  * The vertex shader code generator.
 538  *
 539  * Translates VS IR to actual i965 assembly code.
 540  */
 541 class vec4_generator
 542 {
 543 public:
 544    vec4_generator(struct brw_context *brw,
 545                   struct gl_shader_program *shader_prog,
 546                   struct gl_program *prog,
 547                   struct brw_vec4_prog_data *prog_data,
 548                   void *mem_ctx,
 549                   bool debug_flag);
 550    ~vec4_generator();
 551
 552    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 553
 554 private:
 555    void generate_code(exec_list *instructions);
 556    void generate_vec4_instruction(vec4_instruction *inst,
 557                                   struct brw_reg dst,
 558                                   struct brw_reg *src);
 559
 560    void generate_math1_gen4(vec4_instruction *inst,
 561                             struct brw_reg dst,
 562                             struct brw_reg src);
 563    void generate_math1_gen6(vec4_instruction *inst,
 564                             struct brw_reg dst,
 565                             struct brw_reg src);
 566    void generate_math2_gen4(vec4_instruction *inst,
 567                             struct brw_reg dst,
 568                             struct brw_reg src0,
 569                             struct brw_reg src1);
 570    void generate_math2_gen6(vec4_instruction *inst,
 571                             struct brw_reg dst,
 572                             struct brw_reg src0,
 573                             struct brw_reg src1);
 574    void generate_math2_gen7(vec4_instruction *inst,
 575                             struct brw_reg dst,
 576                             struct brw_reg src0,
 577                             struct brw_reg src1);
 578
 579    void generate_tex(vec4_instruction *inst,
 580                      struct brw_reg dst,
 581                      struct brw_reg src);
 582
 583    void generate_vs_urb_write(vec4_instruction *inst);
 584    void generate_gs_urb_write(vec4_instruction *inst);
 585    void generate_gs_thread_end(vec4_instruction *inst);
 586    void generate_gs_set_write_offset(struct brw_reg dst,
 587                                      struct brw_reg src0,
 588                                      struct brw_reg src1);
 589    void generate_gs_set_vertex_count(struct brw_reg dst,
 590                                      struct brw_reg src);
 591    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 592    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 593    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 594    void generate_oword_dual_block_offsets(struct brw_reg m1,
 595                                           struct brw_reg index);
 596    void generate_scratch_write(vec4_instruction *inst,
 597                                struct brw_reg dst,
 598                                struct brw_reg src,
 599                                struct brw_reg index);
 600    void generate_scratch_read(vec4_instruction *inst,
 601                               struct brw_reg dst,
 602                               struct brw_reg index);
 603    void generate_pull_constant_load(vec4_instruction *inst,
 604                                     struct brw_reg dst,
 605                                     struct brw_reg index,
 606                                     struct brw_reg offset);
 607    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 608                                          struct brw_reg dst,
 609                                          struct brw_reg surf_index,
 610                                          struct brw_reg offset);
 611    void generate_unpack_flags(vec4_instruction *inst,
 612                               struct brw_reg dst);
 613
 614    void mark_surface_used(unsigned surf_index);
 615
 616    struct brw_context *brw;
 617
 618    struct brw_compile *p;
 619
 620    struct gl_shader_program *shader_prog;
 621    struct gl_shader *shader;
 622    const struct gl_program *prog;
 623
 624    struct brw_vec4_prog_data *prog_data;
 625
 626    void *mem_ctx;
 627    const bool debug_flag;
 628 };
 629
 630 } /* namespace brw */
 631 #endif /* __cplusplus */
 632
 633 #endif /* BRW_VEC4_H */