src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39
  40 #ifdef __cplusplus
  41 }; /* extern "C" */
  42 #include "gen8_generator.h"
  43 #endif
  44
  45 #include "glsl/ir.h"
  46
  47
  48 struct brw_vec4_compile {
  49    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  50 };
  51
  52
  53 struct brw_vec4_prog_key {
  54    GLuint program_string_id;
  55
  56    /**
  57     * True if at least one clip flag is enabled, regardless of whether the
  58     * shader uses clip planes or gl_ClipDistance.
  59     */
  60    GLuint userclip_active:1;
  61
  62    /**
  63     * How many user clipping planes are being uploaded to the vertex shader as
  64     * push constants.
  65     */
  66    GLuint nr_userclip_plane_consts:4;
  67
  68    GLuint clamp_vertex_color:1;
  69
  70    struct brw_sampler_prog_key_data tex;
  71 };
  72
  73
  74 #ifdef __cplusplus
  75 extern "C" {
  76 #endif
  77
  78 void
  79 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
  80                                        struct brw_vec4_prog_key *key,
  81                                        GLuint id, struct gl_program *prog);
  82 bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
  83                                 const struct brw_vec4_prog_data *b);
  84 void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data);
  85
  86 #ifdef __cplusplus
  87 } /* extern "C" */
  88
  89 namespace brw {
  90
  91 class dst_reg;
  92
  93 unsigned
  94 swizzle_for_size(int size);
  95
  96 class reg
  97 {
  98 public:
  99    /** Register file: GRF, MRF, IMM. */
 100    enum register_file file;
 101    /** virtual register number.  0 = fixed hw reg */
 102    int reg;
 103    /** Offset within the virtual register. */
 104    int reg_offset;
 105    /** Register type.  BRW_REGISTER_TYPE_* */
 106    int type;
 107    struct brw_reg fixed_hw_reg;
 108
 109    /** Value for file == BRW_IMMMEDIATE_FILE */
 110    union {
 111       int32_t i;
 112       uint32_t u;
 113       float f;
 114    } imm;
 115 };
 116
 117 class src_reg : public reg
 118 {
 119 public:
 120    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
 121
 122    void init();
 123
 124    src_reg(register_file file, int reg, const glsl_type *type);
 125    src_reg();
 126    src_reg(float f);
 127    src_reg(uint32_t u);
 128    src_reg(int32_t i);
 129
 130    bool equals(src_reg *r);
 131    bool is_zero() const;
 132    bool is_one() const;
 133
 134    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 135
 136    explicit src_reg(dst_reg reg);
 137
 138    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 139    bool negate;
 140    bool abs;
 141
 142    src_reg *reladdr;
 143 };
 144
 145 class dst_reg : public reg
 146 {
 147 public:
 148    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 149
 150    void init();
 151
 152    dst_reg();
 153    dst_reg(register_file file, int reg);
 154    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 155    dst_reg(struct brw_reg reg);
 156    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 157
 158    explicit dst_reg(src_reg reg);
 159
 160    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 161
 162    src_reg *reladdr;
 163 };
 164
 165 dst_reg
 166 with_writemask(dst_reg const &r, int mask);
 167
 168 class vec4_instruction : public backend_instruction {
 169 public:
 170    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 171
 172    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 173                     dst_reg dst = dst_reg(),
 174                     src_reg src0 = src_reg(),
 175                     src_reg src1 = src_reg(),
 176                     src_reg src2 = src_reg());
 177
 178    struct brw_reg get_dst(void);
 179    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 180
 181    dst_reg dst;
 182    src_reg src[3];
 183
 184    bool saturate;
 185    bool force_writemask_all;
 186    bool no_dd_clear, no_dd_check;
 187
 188    int conditional_mod; /**< BRW_CONDITIONAL_* */
 189
 190    int sampler;
 191    uint32_t texture_offset; /**< Texture Offset bitfield */
 192    int target; /**< MRT target. */
 193    bool shadow_compare;
 194
 195    enum brw_urb_write_flags urb_write_flags;
 196    bool header_present;
 197    int mlen; /**< SEND message length */
 198    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 199
 200    uint32_t offset; /* spill/unspill offset */
 201    /** @{
 202     * Annotation for the generated IR.  One of the two can be set.
 203     */
 204    const void *ir;
 205    const char *annotation;
 206
 207    bool is_send_from_grf();
 208    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 209    void reswizzle_dst(int dst_writemask, int swizzle);
 210
 211    bool depends_on_flags()
 212    {
 213       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 214    }
 215 };
 216
 217 /**
 218  * The vertex shader front-end.
 219  *
 220  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 221  * fixed-function) into VS IR.
 222  */
 223 class vec4_visitor : public backend_visitor
 224 {
 225 public:
 226    vec4_visitor(struct brw_context *brw,
 227                 struct brw_vec4_compile *c,
 228                 struct gl_program *prog,
 229                 const struct brw_vec4_prog_key *key,
 230                 struct brw_vec4_prog_data *prog_data,
 231                 struct gl_shader_program *shader_prog,
 232                 struct brw_shader *shader,
 233                 void *mem_ctx,
 234                 bool debug_flag,
 235                 bool no_spills,
 236                 shader_time_shader_type st_base,
 237                 shader_time_shader_type st_written,
 238                 shader_time_shader_type st_reset);
 239    ~vec4_visitor();
 240
 241    dst_reg dst_null_f()
 242    {
 243       return dst_reg(brw_null_reg());
 244    }
 245
 246    dst_reg dst_null_d()
 247    {
 248       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 249    }
 250
 251    dst_reg dst_null_ud()
 252    {
 253       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 254    }
 255
 256    struct brw_vec4_compile *c;
 257    const struct brw_vec4_prog_key *key;
 258    struct brw_vec4_prog_data *prog_data;
 259    unsigned int sanity_param_count;
 260
 261    char *fail_msg;
 262    bool failed;
 263
 264    /**
 265     * GLSL IR currently being processed, which is associated with our
 266     * driver IR instructions for debugging purposes.
 267     */
 268    const void *base_ir;
 269    const char *current_annotation;
 270
 271    int *virtual_grf_sizes;
 272    int virtual_grf_count;
 273    int virtual_grf_array_size;
 274    int first_non_payload_grf;
 275    unsigned int max_grf;
 276    int *virtual_grf_start;
 277    int *virtual_grf_end;
 278    dst_reg userplane[MAX_CLIP_PLANES];
 279
 280    /**
 281     * This is the size to be used for an array with an element per
 282     * reg_offset
 283     */
 284    int virtual_grf_reg_count;
 285    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 286    int *virtual_grf_reg_map;
 287
 288    bool live_intervals_valid;
 289
 290    dst_reg *variable_storage(ir_variable *var);
 291
 292    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 293
 294    bool need_all_constants_in_pull_buffer;
 295
 296    /**
 297     * \name Visit methods
 298     *
 299     * As typical for the visitor pattern, there must be one \c visit method for
 300     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 301     * the hierarchy should not have \c visit methods.
 302     */
 303    /*@{*/
 304    virtual void visit(ir_variable *);
 305    virtual void visit(ir_loop *);
 306    virtual void visit(ir_loop_jump *);
 307    virtual void visit(ir_function_signature *);
 308    virtual void visit(ir_function *);
 309    virtual void visit(ir_expression *);
 310    virtual void visit(ir_swizzle *);
 311    virtual void visit(ir_dereference_variable  *);
 312    virtual void visit(ir_dereference_array *);
 313    virtual void visit(ir_dereference_record *);
 314    virtual void visit(ir_assignment *);
 315    virtual void visit(ir_constant *);
 316    virtual void visit(ir_call *);
 317    virtual void visit(ir_return *);
 318    virtual void visit(ir_discard *);
 319    virtual void visit(ir_texture *);
 320    virtual void visit(ir_if *);
 321    virtual void visit(ir_emit_vertex *);
 322    virtual void visit(ir_end_primitive *);
 323    /*@}*/
 324
 325    src_reg result;
 326
 327    /* Regs for vertex results.  Generated at ir_variable visiting time
 328     * for the ir->location's used.
 329     */
 330    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 331    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 332    int uniform_size[MAX_UNIFORMS];
 333    int uniform_vector_size[MAX_UNIFORMS];
 334    int uniforms;
 335
 336    src_reg shader_start_time;
 337
 338    struct hash_table *variable_ht;
 339
 340    bool run(void);
 341    void fail(const char *msg, ...);
 342
 343    int virtual_grf_alloc(int size);
 344    void setup_uniform_clipplane_values();
 345    void setup_uniform_values(ir_variable *ir);
 346    void setup_builtin_uniform_values(ir_variable *ir);
 347    int setup_uniforms(int payload_reg);
 348    bool reg_allocate_trivial();
 349    bool reg_allocate();
 350    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 351    int choose_spill_reg(struct ra_graph *g);
 352    void spill_reg(int spill_reg);
 353    void move_grf_array_access_to_scratch();
 354    void move_uniform_array_access_to_pull_constants();
 355    void move_push_constants_to_pull_constants();
 356    void split_uniform_registers();
 357    void pack_uniform_registers();
 358    void calculate_live_intervals();
 359    void invalidate_live_intervals();
 360    void split_virtual_grfs();
 361    bool dead_code_eliminate();
 362    bool virtual_grf_interferes(int a, int b);
 363    bool opt_copy_propagation();
 364    bool opt_algebraic();
 365    bool opt_register_coalesce();
 366    void opt_set_dependency_control();
 367    void opt_schedule_instructions();
 368
 369    bool can_do_source_mods(vec4_instruction *inst);
 370
 371    vec4_instruction *emit(vec4_instruction *inst);
 372
 373    vec4_instruction *emit(enum opcode opcode);
 374
 375    vec4_instruction *emit(enum opcode opcode, dst_reg dst);
 376
 377    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 378
 379    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 380                           src_reg src0, src_reg src1);
 381
 382    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 383                           src_reg src0, src_reg src1, src_reg src2);
 384
 385    vec4_instruction *emit_before(vec4_instruction *inst,
 386                                  vec4_instruction *new_inst);
 387
 388    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 389    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 390    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 391    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 392    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 393    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 394    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 395    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 396    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 397    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 398    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 399    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 400    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 401    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 402    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 403    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 404    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 405    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 406    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 407    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 408    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 409    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 410                          uint32_t condition);
 411    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 412    vec4_instruction *IF(uint32_t predicate);
 413    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 414    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 415    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 416    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 417    vec4_instruction *BFREV(dst_reg dst, src_reg value);
 418    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
 419    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
 420    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
 421    vec4_instruction *FBH(dst_reg dst, src_reg value);
 422    vec4_instruction *FBL(dst_reg dst, src_reg value);
 423    vec4_instruction *CBIT(dst_reg dst, src_reg value);
 424    vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
 425    vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1);
 426    vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1);
 427
 428    int implied_mrf_writes(vec4_instruction *inst);
 429
 430    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 431                                dst_reg dst,
 432                                src_reg src,
 433                                vec4_instruction *pre_rhs_inst,
 434                                vec4_instruction *last_rhs_inst);
 435
 436    bool try_copy_propagation(vec4_instruction *inst, int arg,
 437                              src_reg *values[4]);
 438
 439    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 440    void visit_instructions(const exec_list *list);
 441
 442    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 443                     src_reg src0, src_reg src1, src_reg one);
 444
 445    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 446    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 447    void emit_if_gen6(ir_if *ir);
 448
 449    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 450
 451    void emit_block_move(dst_reg *dst, src_reg *src,
 452                         const struct glsl_type *type, uint32_t predicate);
 453
 454    void emit_constant_values(dst_reg *dst, ir_constant *value);
 455
 456    /**
 457     * Emit the correct dot-product instruction for the type of arguments
 458     */
 459    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 460
 461    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 462                     dst_reg dst, src_reg src0);
 463
 464    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 465                     dst_reg dst, src_reg src0, src_reg src1);
 466
 467    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 468                  dst_reg dst, const src_reg &src);
 469
 470    src_reg fix_3src_operand(src_reg src);
 471
 472    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 473    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 474    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 475    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 476    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 477    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 478    src_reg fix_math_operand(src_reg src);
 479
 480    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 481    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 482
 483    uint32_t gather_channel(ir_texture *ir, int sampler);
 484    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
 485    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 486
 487    void emit_ndc_computation();
 488    void emit_psiz_and_flags(struct brw_reg reg);
 489    void emit_clip_distances(dst_reg reg, int offset);
 490    void emit_generic_urb_slot(dst_reg reg, int varying);
 491    void emit_urb_slot(int mrf, int varying);
 492
 493    void emit_shader_time_begin();
 494    void emit_shader_time_end();
 495    void emit_shader_time_write(enum shader_time_shader_type type,
 496                                src_reg value);
 497
 498    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 499                             dst_reg dst, src_reg offset, src_reg src0,
 500                             src_reg src1);
 501
 502    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 503                                   src_reg offset);
 504
 505    src_reg get_scratch_offset(vec4_instruction *inst,
 506                               src_reg *reladdr, int reg_offset);
 507    src_reg get_pull_constant_offset(vec4_instruction *inst,
 508                                     src_reg *reladdr, int reg_offset);
 509    void emit_scratch_read(vec4_instruction *inst,
 510                           dst_reg dst,
 511                           src_reg orig_src,
 512                           int base_offset);
 513    void emit_scratch_write(vec4_instruction *inst,
 514                            int base_offset);
 515    void emit_pull_constant_load(vec4_instruction *inst,
 516                                 dst_reg dst,
 517                                 src_reg orig_src,
 518                                 int base_offset);
 519
 520    bool try_emit_sat(ir_expression *ir);
 521    bool try_emit_mad(ir_expression *ir, int mul_arg);
 522    void resolve_ud_negate(src_reg *reg);
 523
 524    src_reg get_timestamp();
 525
 526    bool process_move_condition(ir_rvalue *ir);
 527
 528    void dump_instruction(backend_instruction *inst);
 529
 530    void visit_atomic_counter_intrinsic(ir_call *ir);
 531
 532 protected:
 533    void emit_vertex();
 534    void lower_attributes_to_hw_regs(const int *attribute_map,
 535                                     bool interleaved);
 536    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 537                                    int reg_node_count);
 538    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 539    virtual void setup_payload() = 0;
 540    virtual void emit_prolog() = 0;
 541    virtual void emit_program_code() = 0;
 542    virtual void emit_thread_end() = 0;
 543    virtual void emit_urb_write_header(int mrf) = 0;
 544    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 545    virtual int compute_array_stride(ir_dereference_array *ir);
 546
 547    const bool debug_flag;
 548
 549 private:
 550    /**
 551     * If true, then register allocation should fail instead of spilling.
 552     */
 553    const bool no_spills;
 554
 555    const shader_time_shader_type st_base;
 556    const shader_time_shader_type st_written;
 557    const shader_time_shader_type st_reset;
 558 };
 559
 560
 561 /**
 562  * The vertex shader code generator.
 563  *
 564  * Translates VS IR to actual i965 assembly code.
 565  */
 566 class vec4_generator
 567 {
 568 public:
 569    vec4_generator(struct brw_context *brw,
 570                   struct gl_shader_program *shader_prog,
 571                   struct gl_program *prog,
 572                   struct brw_vec4_prog_data *prog_data,
 573                   void *mem_ctx,
 574                   bool debug_flag);
 575    ~vec4_generator();
 576
 577    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 578
 579 private:
 580    void generate_code(exec_list *instructions);
 581    void generate_vec4_instruction(vec4_instruction *inst,
 582                                   struct brw_reg dst,
 583                                   struct brw_reg *src);
 584
 585    void generate_math1_gen4(vec4_instruction *inst,
 586                             struct brw_reg dst,
 587                             struct brw_reg src);
 588    void generate_math1_gen6(vec4_instruction *inst,
 589                             struct brw_reg dst,
 590                             struct brw_reg src);
 591    void generate_math2_gen4(vec4_instruction *inst,
 592                             struct brw_reg dst,
 593                             struct brw_reg src0,
 594                             struct brw_reg src1);
 595    void generate_math2_gen6(vec4_instruction *inst,
 596                             struct brw_reg dst,
 597                             struct brw_reg src0,
 598                             struct brw_reg src1);
 599    void generate_math2_gen7(vec4_instruction *inst,
 600                             struct brw_reg dst,
 601                             struct brw_reg src0,
 602                             struct brw_reg src1);
 603
 604    void generate_tex(vec4_instruction *inst,
 605                      struct brw_reg dst,
 606                      struct brw_reg src);
 607
 608    void generate_vs_urb_write(vec4_instruction *inst);
 609    void generate_gs_urb_write(vec4_instruction *inst);
 610    void generate_gs_thread_end(vec4_instruction *inst);
 611    void generate_gs_set_write_offset(struct brw_reg dst,
 612                                      struct brw_reg src0,
 613                                      struct brw_reg src1);
 614    void generate_gs_set_vertex_count(struct brw_reg dst,
 615                                      struct brw_reg src);
 616    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 617    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 618    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 619    void generate_oword_dual_block_offsets(struct brw_reg m1,
 620                                           struct brw_reg index);
 621    void generate_scratch_write(vec4_instruction *inst,
 622                                struct brw_reg dst,
 623                                struct brw_reg src,
 624                                struct brw_reg index);
 625    void generate_scratch_read(vec4_instruction *inst,
 626                               struct brw_reg dst,
 627                               struct brw_reg index);
 628    void generate_pull_constant_load(vec4_instruction *inst,
 629                                     struct brw_reg dst,
 630                                     struct brw_reg index,
 631                                     struct brw_reg offset);
 632    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 633                                          struct brw_reg dst,
 634                                          struct brw_reg surf_index,
 635                                          struct brw_reg offset);
 636    void generate_unpack_flags(vec4_instruction *inst,
 637                               struct brw_reg dst);
 638
 639    void generate_untyped_atomic(vec4_instruction *inst,
 640                                 struct brw_reg dst,
 641                                 struct brw_reg atomic_op,
 642                                 struct brw_reg surf_index);
 643
 644    void generate_untyped_surface_read(vec4_instruction *inst,
 645                                       struct brw_reg dst,
 646                                       struct brw_reg surf_index);
 647
 648    void mark_surface_used(unsigned surf_index);
 649
 650    struct brw_context *brw;
 651
 652    struct brw_compile *p;
 653
 654    struct gl_shader_program *shader_prog;
 655    struct gl_shader *shader;
 656    const struct gl_program *prog;
 657
 658    struct brw_vec4_prog_data *prog_data;
 659
 660    void *mem_ctx;
 661    const bool debug_flag;
 662 };
 663
 664 /**
 665  * The vertex shader code generator.
 666  *
 667  * Translates VS IR to actual i965 assembly code.
 668  */
 669 class gen8_vec4_generator : public gen8_generator
 670 {
 671 public:
 672    gen8_vec4_generator(struct brw_context *brw,
 673                        struct gl_shader_program *shader_prog,
 674                        struct gl_program *prog,
 675                        struct brw_vec4_prog_data *prog_data,
 676                        void *mem_ctx,
 677                        bool debug_flag);
 678    ~gen8_vec4_generator();
 679
 680    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 681
 682 private:
 683    void generate_code(exec_list *instructions);
 684    void generate_vec4_instruction(vec4_instruction *inst,
 685                                   struct brw_reg dst,
 686                                   struct brw_reg *src);
 687
 688    void generate_tex(vec4_instruction *inst,
 689                      struct brw_reg dst);
 690
 691    void generate_urb_write(vec4_instruction *ir, bool copy_g0);
 692    void generate_gs_thread_end(vec4_instruction *ir);
 693    void generate_gs_set_write_offset(struct brw_reg dst,
 694                                      struct brw_reg src0,
 695                                      struct brw_reg src1);
 696    void generate_gs_set_vertex_count(struct brw_reg dst,
 697                                      struct brw_reg src);
 698    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 699    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 700    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 701
 702    void generate_oword_dual_block_offsets(struct brw_reg m1,
 703                                           struct brw_reg index);
 704    void generate_scratch_write(vec4_instruction *inst,
 705                                struct brw_reg dst,
 706                                struct brw_reg src,
 707                                struct brw_reg index);
 708    void generate_scratch_read(vec4_instruction *inst,
 709                               struct brw_reg dst,
 710                               struct brw_reg index);
 711    void generate_pull_constant_load(vec4_instruction *inst,
 712                                     struct brw_reg dst,
 713                                     struct brw_reg index,
 714                                     struct brw_reg offset);
 715
 716    void mark_surface_used(unsigned surf_index);
 717
 718    struct brw_vec4_prog_data *prog_data;
 719
 720    const bool debug_flag;
 721 };
 722
 723
 724 } /* namespace brw */
 725 #endif /* __cplusplus */
 726
 727 #endif /* BRW_VEC4_H */