2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
31 #include "brw_program.h"
37 #include "brw_context.h"
39 #include "intel_asm_annotation.h"
48 struct brw_vec4_compile
{
49 GLuint last_scratch
; /**< measured in 32-byte (register size) units */
53 struct brw_vec4_prog_key
{
54 GLuint program_string_id
;
57 * True if at least one clip flag is enabled, regardless of whether the
58 * shader uses clip planes or gl_ClipDistance.
60 GLuint userclip_active
:1;
63 * How many user clipping planes are being uploaded to the vertex shader as
66 GLuint nr_userclip_plane_consts
:4;
68 GLuint clamp_vertex_color
:1;
70 struct brw_sampler_prog_key_data tex
;
79 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
80 struct brw_vec4_prog_key
*key
,
81 GLuint id
, struct gl_program
*prog
);
91 swizzle_for_size(int size
);
93 class src_reg
: public backend_reg
96 DECLARE_RALLOC_CXX_OPERATORS(src_reg
)
100 src_reg(register_file file
, int reg
, const glsl_type
*type
);
105 src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
);
106 src_reg(struct brw_reg reg
);
108 bool equals(const src_reg
&r
) const;
110 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
111 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
);
113 explicit src_reg(dst_reg reg
);
115 GLuint swizzle
; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
120 static inline src_reg
121 retype(src_reg reg
, enum brw_reg_type type
)
123 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
127 static inline src_reg
128 offset(src_reg reg
, unsigned delta
)
130 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
131 reg
.reg_offset
+= delta
;
136 * Reswizzle a given source register.
139 static inline src_reg
140 swizzle(src_reg reg
, unsigned swizzle
)
142 assert(reg
.file
!= HW_REG
);
143 reg
.swizzle
= BRW_SWIZZLE4(
144 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 0)),
145 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 1)),
146 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 2)),
147 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 3)));
151 static inline src_reg
154 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
155 reg
.negate
= !reg
.negate
;
159 class dst_reg
: public backend_reg
162 DECLARE_RALLOC_CXX_OPERATORS(dst_reg
)
167 dst_reg(register_file file
, int reg
);
168 dst_reg(register_file file
, int reg
, const glsl_type
*type
, int writemask
);
169 dst_reg(struct brw_reg reg
);
170 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
172 explicit dst_reg(src_reg reg
);
174 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
179 static inline dst_reg
180 retype(dst_reg reg
, enum brw_reg_type type
)
182 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
186 static inline dst_reg
187 offset(dst_reg reg
, unsigned delta
)
189 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
190 reg
.reg_offset
+= delta
;
194 static inline dst_reg
195 writemask(dst_reg reg
, unsigned mask
)
197 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
198 assert((reg
.writemask
& mask
) != 0);
199 reg
.writemask
&= mask
;
203 class vec4_instruction
: public backend_instruction
{
205 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction
)
207 vec4_instruction(vec4_visitor
*v
, enum opcode opcode
,
208 const dst_reg
&dst
= dst_reg(),
209 const src_reg
&src0
= src_reg(),
210 const src_reg
&src1
= src_reg(),
211 const src_reg
&src2
= src_reg());
213 struct brw_reg
get_dst(void);
214 struct brw_reg
get_src(const struct brw_vec4_prog_data
*prog_data
, int i
);
219 enum brw_urb_write_flags urb_write_flags
;
221 unsigned sol_binding
; /**< gen6: SOL binding table index */
222 bool sol_final_write
; /**< gen6: send commit message */
223 unsigned sol_vertex
; /**< gen6: used for setting dst index in SVB header */
225 bool is_send_from_grf();
226 bool can_reswizzle(int dst_writemask
, int swizzle
, int swizzle_mask
);
227 void reswizzle(int dst_writemask
, int swizzle
);
228 bool can_do_source_mods(struct brw_context
*brw
);
232 return predicate
|| opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
;
237 return conditional_mod
&& opcode
!= BRW_OPCODE_SEL
;
242 * The vertex shader front-end.
244 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
245 * fixed-function) into VS IR.
247 class vec4_visitor
: public backend_visitor
250 vec4_visitor(struct brw_context
*brw
,
251 struct brw_vec4_compile
*c
,
252 struct gl_program
*prog
,
253 const struct brw_vec4_prog_key
*key
,
254 struct brw_vec4_prog_data
*prog_data
,
255 struct gl_shader_program
*shader_prog
,
256 gl_shader_stage stage
,
260 shader_time_shader_type st_base
,
261 shader_time_shader_type st_written
,
262 shader_time_shader_type st_reset
);
267 return dst_reg(brw_null_reg());
272 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
275 dst_reg
dst_null_ud()
277 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
280 struct brw_vec4_compile
* const c
;
281 const struct brw_vec4_prog_key
* const key
;
282 struct brw_vec4_prog_data
* const prog_data
;
283 unsigned int sanity_param_count
;
289 * GLSL IR currently being processed, which is associated with our
290 * driver IR instructions for debugging purposes.
293 const char *current_annotation
;
295 int *virtual_grf_sizes
;
296 int virtual_grf_count
;
297 int virtual_grf_array_size
;
298 int first_non_payload_grf
;
299 unsigned int max_grf
;
300 int *virtual_grf_start
;
301 int *virtual_grf_end
;
302 dst_reg userplane
[MAX_CLIP_PLANES
];
305 * This is the size to be used for an array with an element per
308 int virtual_grf_reg_count
;
309 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
310 int *virtual_grf_reg_map
;
312 bool live_intervals_valid
;
314 dst_reg
*variable_storage(ir_variable
*var
);
316 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
318 bool need_all_constants_in_pull_buffer
;
321 * \name Visit methods
323 * As typical for the visitor pattern, there must be one \c visit method for
324 * each concrete subclass of \c ir_instruction. Virtual base classes within
325 * the hierarchy should not have \c visit methods.
328 virtual void visit(ir_variable
*);
329 virtual void visit(ir_loop
*);
330 virtual void visit(ir_loop_jump
*);
331 virtual void visit(ir_function_signature
*);
332 virtual void visit(ir_function
*);
333 virtual void visit(ir_expression
*);
334 virtual void visit(ir_swizzle
*);
335 virtual void visit(ir_dereference_variable
*);
336 virtual void visit(ir_dereference_array
*);
337 virtual void visit(ir_dereference_record
*);
338 virtual void visit(ir_assignment
*);
339 virtual void visit(ir_constant
*);
340 virtual void visit(ir_call
*);
341 virtual void visit(ir_return
*);
342 virtual void visit(ir_discard
*);
343 virtual void visit(ir_texture
*);
344 virtual void visit(ir_if
*);
345 virtual void visit(ir_emit_vertex
*);
346 virtual void visit(ir_end_primitive
*);
351 /* Regs for vertex results. Generated at ir_variable visiting time
352 * for the ir->location's used.
354 dst_reg output_reg
[BRW_VARYING_SLOT_COUNT
];
355 const char *output_reg_annotation
[BRW_VARYING_SLOT_COUNT
];
357 int *uniform_vector_size
;
358 int uniform_array_size
; /*< Size of uniform_[vector_]size arrays */
361 src_reg shader_start_time
;
363 struct hash_table
*variable_ht
;
366 void fail(const char *msg
, ...);
368 int virtual_grf_alloc(int size
);
369 void setup_uniform_clipplane_values();
370 void setup_uniform_values(ir_variable
*ir
);
371 void setup_builtin_uniform_values(ir_variable
*ir
);
372 int setup_uniforms(int payload_reg
);
373 bool reg_allocate_trivial();
375 void evaluate_spill_costs(float *spill_costs
, bool *no_spill
);
376 int choose_spill_reg(struct ra_graph
*g
);
377 void spill_reg(int spill_reg
);
378 void move_grf_array_access_to_scratch();
379 void move_uniform_array_access_to_pull_constants();
380 void move_push_constants_to_pull_constants();
381 void split_uniform_registers();
382 void pack_uniform_registers();
383 void calculate_live_intervals();
384 void invalidate_live_intervals();
385 void split_virtual_grfs();
386 bool opt_reduce_swizzle();
387 bool dead_code_eliminate();
388 bool virtual_grf_interferes(int a
, int b
);
389 bool opt_copy_propagation();
390 bool opt_cse_local(bblock_t
*block
);
392 bool opt_algebraic();
393 bool opt_register_coalesce();
394 bool is_dep_ctrl_unsafe(const vec4_instruction
*inst
);
395 void opt_set_dependency_control();
396 void opt_schedule_instructions();
398 vec4_instruction
*emit(vec4_instruction
*inst
);
400 vec4_instruction
*emit(enum opcode opcode
);
401 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
);
402 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
,
403 const src_reg
&src0
);
404 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
,
405 const src_reg
&src0
, const src_reg
&src1
);
406 vec4_instruction
*emit(enum opcode opcode
, const dst_reg
&dst
,
407 const src_reg
&src0
, const src_reg
&src1
,
408 const src_reg
&src2
);
410 vec4_instruction
*emit_before(bblock_t
*block
,
411 vec4_instruction
*inst
,
412 vec4_instruction
*new_inst
);
414 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
415 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
416 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
438 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
439 enum brw_conditional_mod condition
);
440 vec4_instruction
*IF(src_reg src0
, src_reg src1
,
441 enum brw_conditional_mod condition
);
442 vec4_instruction
*IF(enum brw_predicate predicate
);
443 EMIT1(PULL_CONSTANT_LOAD
)
461 int implied_mrf_writes(vec4_instruction
*inst
);
463 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
466 vec4_instruction
*pre_rhs_inst
,
467 vec4_instruction
*last_rhs_inst
);
469 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
470 void visit_instructions(const exec_list
*list
);
472 void emit_vp_sop(enum brw_conditional_mod condmod
, dst_reg dst
,
473 src_reg src0
, src_reg src1
, src_reg one
);
475 void emit_bool_to_cond_code(ir_rvalue
*ir
, enum brw_predicate
*predicate
);
476 void emit_if_gen6(ir_if
*ir
);
478 void emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
479 src_reg src0
, src_reg src1
);
481 void emit_lrp(const dst_reg
&dst
,
482 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
);
484 void emit_block_move(dst_reg
*dst
, src_reg
*src
,
485 const struct glsl_type
*type
, brw_predicate predicate
);
487 void emit_constant_values(dst_reg
*dst
, ir_constant
*value
);
490 * Emit the correct dot-product instruction for the type of arguments
492 void emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
);
494 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
495 dst_reg dst
, src_reg src0
);
497 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
498 dst_reg dst
, src_reg src0
, src_reg src1
);
500 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
501 dst_reg dst
, const src_reg
&src
);
503 src_reg
fix_3src_operand(src_reg src
);
505 void emit_math(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
506 const src_reg
&src1
= src_reg());
507 src_reg
fix_math_operand(src_reg src
);
509 void emit_pack_half_2x16(dst_reg dst
, src_reg src0
);
510 void emit_unpack_half_2x16(dst_reg dst
, src_reg src0
);
511 void emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
);
512 void emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
);
513 void emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
);
514 void emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
);
516 uint32_t gather_channel(ir_texture
*ir
, uint32_t sampler
);
517 src_reg
emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
);
518 void emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
);
519 void swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
);
521 void emit_ndc_computation();
522 void emit_psiz_and_flags(dst_reg reg
);
523 void emit_clip_distances(dst_reg reg
, int offset
);
524 void emit_generic_urb_slot(dst_reg reg
, int varying
);
525 void emit_urb_slot(dst_reg reg
, int varying
);
527 void emit_shader_time_begin();
528 void emit_shader_time_end();
529 void emit_shader_time_write(enum shader_time_shader_type type
,
532 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
533 dst_reg dst
, src_reg offset
, src_reg src0
,
536 void emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
539 src_reg
get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
540 src_reg
*reladdr
, int reg_offset
);
541 src_reg
get_pull_constant_offset(bblock_t
*block
, vec4_instruction
*inst
,
542 src_reg
*reladdr
, int reg_offset
);
543 void emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
547 void emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
549 void emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
554 bool try_emit_mad(ir_expression
*ir
);
555 bool try_emit_b2f_of_compare(ir_expression
*ir
);
556 void resolve_ud_negate(src_reg
*reg
);
558 src_reg
get_timestamp();
560 bool process_move_condition(ir_rvalue
*ir
);
562 void dump_instruction(backend_instruction
*inst
);
563 void dump_instruction(backend_instruction
*inst
, FILE *file
);
565 void visit_atomic_counter_intrinsic(ir_call
*ir
);
569 void lower_attributes_to_hw_regs(const int *attribute_map
,
571 void setup_payload_interference(struct ra_graph
*g
, int first_payload_node
,
573 virtual dst_reg
*make_reg_for_system_value(ir_variable
*ir
) = 0;
574 virtual void assign_binding_table_offsets();
575 virtual void setup_payload() = 0;
576 virtual void emit_prolog() = 0;
577 virtual void emit_program_code() = 0;
578 virtual void emit_thread_end() = 0;
579 virtual void emit_urb_write_header(int mrf
) = 0;
580 virtual vec4_instruction
*emit_urb_write_opcode(bool complete
) = 0;
581 virtual int compute_array_stride(ir_dereference_array
*ir
);
583 const bool debug_flag
;
587 * If true, then register allocation should fail instead of spilling.
589 const bool no_spills
;
591 const shader_time_shader_type st_base
;
592 const shader_time_shader_type st_written
;
593 const shader_time_shader_type st_reset
;
598 * The vertex shader code generator.
600 * Translates VS IR to actual i965 assembly code.
605 vec4_generator(struct brw_context
*brw
,
606 struct gl_shader_program
*shader_prog
,
607 struct gl_program
*prog
,
608 struct brw_vec4_prog_data
*prog_data
,
613 const unsigned *generate_assembly(const cfg_t
*cfg
, unsigned *asm_size
);
616 void generate_code(const cfg_t
*cfg
);
618 void generate_math1_gen4(vec4_instruction
*inst
,
621 void generate_math2_gen4(vec4_instruction
*inst
,
624 struct brw_reg src1
);
625 void generate_math_gen6(vec4_instruction
*inst
,
628 struct brw_reg src1
);
630 void generate_tex(vec4_instruction
*inst
,
633 struct brw_reg sampler_index
);
635 void generate_vs_urb_write(vec4_instruction
*inst
);
636 void generate_gs_urb_write(vec4_instruction
*inst
);
637 void generate_gs_urb_write_allocate(vec4_instruction
*inst
);
638 void generate_gs_thread_end(vec4_instruction
*inst
);
639 void generate_gs_set_write_offset(struct brw_reg dst
,
641 struct brw_reg src1
);
642 void generate_gs_set_vertex_count(struct brw_reg dst
,
644 void generate_gs_svb_write(vec4_instruction
*inst
,
647 struct brw_reg src1
);
648 void generate_gs_svb_set_destination_index(vec4_instruction
*inst
,
651 void generate_gs_set_dword_2(struct brw_reg dst
, struct brw_reg src
);
652 void generate_gs_prepare_channel_masks(struct brw_reg dst
);
653 void generate_gs_set_channel_masks(struct brw_reg dst
, struct brw_reg src
);
654 void generate_gs_get_instance_id(struct brw_reg dst
);
655 void generate_gs_ff_sync_set_primitives(struct brw_reg dst
,
658 struct brw_reg src2
);
659 void generate_gs_ff_sync(vec4_instruction
*inst
,
662 struct brw_reg src1
);
663 void generate_gs_set_primitive_id(struct brw_reg dst
);
664 void generate_oword_dual_block_offsets(struct brw_reg m1
,
665 struct brw_reg index
);
666 void generate_scratch_write(vec4_instruction
*inst
,
669 struct brw_reg index
);
670 void generate_scratch_read(vec4_instruction
*inst
,
672 struct brw_reg index
);
673 void generate_pull_constant_load(vec4_instruction
*inst
,
675 struct brw_reg index
,
676 struct brw_reg offset
);
677 void generate_pull_constant_load_gen7(vec4_instruction
*inst
,
679 struct brw_reg surf_index
,
680 struct brw_reg offset
);
681 void generate_unpack_flags(vec4_instruction
*inst
,
684 void generate_untyped_atomic(vec4_instruction
*inst
,
686 struct brw_reg atomic_op
,
687 struct brw_reg surf_index
);
689 void generate_untyped_surface_read(vec4_instruction
*inst
,
691 struct brw_reg surf_index
);
693 struct brw_context
*brw
;
695 struct brw_compile
*p
;
697 struct gl_shader_program
*shader_prog
;
698 const struct gl_program
*prog
;
700 struct brw_vec4_prog_data
*prog_data
;
703 const bool debug_flag
;
706 } /* namespace brw */
707 #endif /* __cplusplus */
709 #endif /* BRW_VEC4_H */