src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39
  40 #ifdef __cplusplus
  41 }; /* extern "C" */
  42 #include "gen8_generator.h"
  43 #endif
  44
  45 #include "glsl/ir.h"
  46
  47
  48 struct brw_vec4_compile {
  49    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  50 };
  51
  52
  53 struct brw_vec4_prog_key {
  54    GLuint program_string_id;
  55
  56    /**
  57     * True if at least one clip flag is enabled, regardless of whether the
  58     * shader uses clip planes or gl_ClipDistance.
  59     */
  60    GLuint userclip_active:1;
  61
  62    /**
  63     * How many user clipping planes are being uploaded to the vertex shader as
  64     * push constants.
  65     */
  66    GLuint nr_userclip_plane_consts:4;
  67
  68    GLuint clamp_vertex_color:1;
  69
  70    struct brw_sampler_prog_key_data tex;
  71 };
  72
  73
  74 #ifdef __cplusplus
  75 extern "C" {
  76 #endif
  77
  78 void
  79 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
  80                                        struct brw_vec4_prog_key *key,
  81                                        GLuint id, struct gl_program *prog);
  82
  83 #ifdef __cplusplus
  84 } /* extern "C" */
  85
  86 namespace brw {
  87
  88 class dst_reg;
  89
  90 unsigned
  91 swizzle_for_size(int size);
  92
  93 class reg
  94 {
  95 public:
  96    /** Register file: GRF, MRF, IMM. */
  97    enum register_file file;
  98    /** virtual register number.  0 = fixed hw reg */
  99    int reg;
 100    /** Offset within the virtual register. */
 101    int reg_offset;
 102    /** Register type.  BRW_REGISTER_TYPE_* */
 103    int type;
 104    struct brw_reg fixed_hw_reg;
 105
 106    /** Value for file == BRW_IMMMEDIATE_FILE */
 107    union {
 108       int32_t i;
 109       uint32_t u;
 110       float f;
 111    } imm;
 112 };
 113
 114 class src_reg : public reg
 115 {
 116 public:
 117    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
 118
 119    void init();
 120
 121    src_reg(register_file file, int reg, const glsl_type *type);
 122    src_reg();
 123    src_reg(float f);
 124    src_reg(uint32_t u);
 125    src_reg(int32_t i);
 126    src_reg(struct brw_reg reg);
 127
 128    bool equals(src_reg *r);
 129    bool is_zero() const;
 130    bool is_one() const;
 131
 132    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 133
 134    explicit src_reg(dst_reg reg);
 135
 136    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 137    bool negate;
 138    bool abs;
 139
 140    src_reg *reladdr;
 141 };
 142
 143 class dst_reg : public reg
 144 {
 145 public:
 146    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 147
 148    void init();
 149
 150    dst_reg();
 151    dst_reg(register_file file, int reg);
 152    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 153    dst_reg(struct brw_reg reg);
 154    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 155
 156    explicit dst_reg(src_reg reg);
 157
 158    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 159
 160    src_reg *reladdr;
 161 };
 162
 163 dst_reg
 164 with_writemask(dst_reg const &r, int mask);
 165
 166 class vec4_instruction : public backend_instruction {
 167 public:
 168    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 169
 170    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 171                     dst_reg dst = dst_reg(),
 172                     src_reg src0 = src_reg(),
 173                     src_reg src1 = src_reg(),
 174                     src_reg src2 = src_reg());
 175
 176    struct brw_reg get_dst(void);
 177    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 178
 179    dst_reg dst;
 180    src_reg src[3];
 181
 182    bool saturate;
 183    bool force_writemask_all;
 184    bool no_dd_clear, no_dd_check;
 185
 186    int conditional_mod; /**< BRW_CONDITIONAL_* */
 187
 188    int sampler;
 189    uint32_t texture_offset; /**< Texture Offset bitfield */
 190    int target; /**< MRT target. */
 191    bool shadow_compare;
 192
 193    enum brw_urb_write_flags urb_write_flags;
 194    bool header_present;
 195    int mlen; /**< SEND message length */
 196    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 197
 198    uint32_t offset; /* spill/unspill offset */
 199    /** @{
 200     * Annotation for the generated IR.  One of the two can be set.
 201     */
 202    const void *ir;
 203    const char *annotation;
 204
 205    bool is_send_from_grf();
 206    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 207    void reswizzle_dst(int dst_writemask, int swizzle);
 208
 209    bool depends_on_flags()
 210    {
 211       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 212    }
 213 };
 214
 215 /**
 216  * The vertex shader front-end.
 217  *
 218  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 219  * fixed-function) into VS IR.
 220  */
 221 class vec4_visitor : public backend_visitor
 222 {
 223 public:
 224    vec4_visitor(struct brw_context *brw,
 225                 struct brw_vec4_compile *c,
 226                 struct gl_program *prog,
 227                 const struct brw_vec4_prog_key *key,
 228                 struct brw_vec4_prog_data *prog_data,
 229                 struct gl_shader_program *shader_prog,
 230                 struct brw_shader *shader,
 231                 void *mem_ctx,
 232                 bool debug_flag,
 233                 bool no_spills,
 234                 shader_time_shader_type st_base,
 235                 shader_time_shader_type st_written,
 236                 shader_time_shader_type st_reset);
 237    ~vec4_visitor();
 238
 239    dst_reg dst_null_f()
 240    {
 241       return dst_reg(brw_null_reg());
 242    }
 243
 244    dst_reg dst_null_d()
 245    {
 246       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 247    }
 248
 249    dst_reg dst_null_ud()
 250    {
 251       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 252    }
 253
 254    struct brw_vec4_compile *c;
 255    const struct brw_vec4_prog_key *key;
 256    struct brw_vec4_prog_data *prog_data;
 257    unsigned int sanity_param_count;
 258
 259    char *fail_msg;
 260    bool failed;
 261
 262    /**
 263     * GLSL IR currently being processed, which is associated with our
 264     * driver IR instructions for debugging purposes.
 265     */
 266    const void *base_ir;
 267    const char *current_annotation;
 268
 269    int *virtual_grf_sizes;
 270    int virtual_grf_count;
 271    int virtual_grf_array_size;
 272    int first_non_payload_grf;
 273    unsigned int max_grf;
 274    int *virtual_grf_start;
 275    int *virtual_grf_end;
 276    dst_reg userplane[MAX_CLIP_PLANES];
 277
 278    /**
 279     * This is the size to be used for an array with an element per
 280     * reg_offset
 281     */
 282    int virtual_grf_reg_count;
 283    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 284    int *virtual_grf_reg_map;
 285
 286    bool live_intervals_valid;
 287
 288    dst_reg *variable_storage(ir_variable *var);
 289
 290    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 291
 292    bool need_all_constants_in_pull_buffer;
 293
 294    /**
 295     * \name Visit methods
 296     *
 297     * As typical for the visitor pattern, there must be one \c visit method for
 298     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 299     * the hierarchy should not have \c visit methods.
 300     */
 301    /*@{*/
 302    virtual void visit(ir_variable *);
 303    virtual void visit(ir_loop *);
 304    virtual void visit(ir_loop_jump *);
 305    virtual void visit(ir_function_signature *);
 306    virtual void visit(ir_function *);
 307    virtual void visit(ir_expression *);
 308    virtual void visit(ir_swizzle *);
 309    virtual void visit(ir_dereference_variable  *);
 310    virtual void visit(ir_dereference_array *);
 311    virtual void visit(ir_dereference_record *);
 312    virtual void visit(ir_assignment *);
 313    virtual void visit(ir_constant *);
 314    virtual void visit(ir_call *);
 315    virtual void visit(ir_return *);
 316    virtual void visit(ir_discard *);
 317    virtual void visit(ir_texture *);
 318    virtual void visit(ir_if *);
 319    virtual void visit(ir_emit_vertex *);
 320    virtual void visit(ir_end_primitive *);
 321    /*@}*/
 322
 323    src_reg result;
 324
 325    /* Regs for vertex results.  Generated at ir_variable visiting time
 326     * for the ir->location's used.
 327     */
 328    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 329    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 330    int uniform_size[MAX_UNIFORMS];
 331    int uniform_vector_size[MAX_UNIFORMS];
 332    int uniforms;
 333
 334    src_reg shader_start_time;
 335
 336    struct hash_table *variable_ht;
 337
 338    bool run(void);
 339    void fail(const char *msg, ...);
 340
 341    int virtual_grf_alloc(int size);
 342    void setup_uniform_clipplane_values();
 343    void setup_uniform_values(ir_variable *ir);
 344    void setup_builtin_uniform_values(ir_variable *ir);
 345    int setup_uniforms(int payload_reg);
 346    bool reg_allocate_trivial();
 347    bool reg_allocate();
 348    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 349    int choose_spill_reg(struct ra_graph *g);
 350    void spill_reg(int spill_reg);
 351    void move_grf_array_access_to_scratch();
 352    void move_uniform_array_access_to_pull_constants();
 353    void move_push_constants_to_pull_constants();
 354    void split_uniform_registers();
 355    void pack_uniform_registers();
 356    void calculate_live_intervals();
 357    void invalidate_live_intervals();
 358    void split_virtual_grfs();
 359    bool dead_code_eliminate();
 360    bool virtual_grf_interferes(int a, int b);
 361    bool opt_copy_propagation();
 362    bool opt_algebraic();
 363    bool opt_register_coalesce();
 364    void opt_set_dependency_control();
 365    void opt_schedule_instructions();
 366
 367    bool can_do_source_mods(vec4_instruction *inst);
 368
 369    vec4_instruction *emit(vec4_instruction *inst);
 370
 371    vec4_instruction *emit(enum opcode opcode);
 372
 373    vec4_instruction *emit(enum opcode opcode, dst_reg dst);
 374
 375    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 376
 377    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 378                           src_reg src0, src_reg src1);
 379
 380    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 381                           src_reg src0, src_reg src1, src_reg src2);
 382
 383    vec4_instruction *emit_before(vec4_instruction *inst,
 384                                  vec4_instruction *new_inst);
 385
 386    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 387    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 388    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 389    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 390    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 391    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 392    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 393    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 394    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 395    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 396    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 397    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 398    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 399    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 400    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 401    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 402    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 403    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 404    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 405    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 406    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 407    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 408                          uint32_t condition);
 409    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 410    vec4_instruction *IF(uint32_t predicate);
 411    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 412    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 413    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 414    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 415    vec4_instruction *BFREV(dst_reg dst, src_reg value);
 416    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
 417    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
 418    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
 419    vec4_instruction *FBH(dst_reg dst, src_reg value);
 420    vec4_instruction *FBL(dst_reg dst, src_reg value);
 421    vec4_instruction *CBIT(dst_reg dst, src_reg value);
 422    vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
 423    vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1);
 424    vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1);
 425
 426    int implied_mrf_writes(vec4_instruction *inst);
 427
 428    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 429                                dst_reg dst,
 430                                src_reg src,
 431                                vec4_instruction *pre_rhs_inst,
 432                                vec4_instruction *last_rhs_inst);
 433
 434    bool try_copy_propagation(vec4_instruction *inst, int arg,
 435                              src_reg *values[4]);
 436
 437    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 438    void visit_instructions(const exec_list *list);
 439
 440    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 441                     src_reg src0, src_reg src1, src_reg one);
 442
 443    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 444    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 445    void emit_if_gen6(ir_if *ir);
 446
 447    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 448
 449    void emit_block_move(dst_reg *dst, src_reg *src,
 450                         const struct glsl_type *type, uint32_t predicate);
 451
 452    void emit_constant_values(dst_reg *dst, ir_constant *value);
 453
 454    /**
 455     * Emit the correct dot-product instruction for the type of arguments
 456     */
 457    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 458
 459    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 460                     dst_reg dst, src_reg src0);
 461
 462    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 463                     dst_reg dst, src_reg src0, src_reg src1);
 464
 465    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 466                  dst_reg dst, const src_reg &src);
 467
 468    src_reg fix_3src_operand(src_reg src);
 469
 470    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 471    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 472    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 473    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 474    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 475    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 476    src_reg fix_math_operand(src_reg src);
 477
 478    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 479    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 480
 481    uint32_t gather_channel(ir_texture *ir, int sampler);
 482    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
 483    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 484    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 485
 486    void emit_ndc_computation();
 487    void emit_psiz_and_flags(struct brw_reg reg);
 488    void emit_clip_distances(dst_reg reg, int offset);
 489    void emit_generic_urb_slot(dst_reg reg, int varying);
 490    void emit_urb_slot(int mrf, int varying);
 491
 492    void emit_shader_time_begin();
 493    void emit_shader_time_end();
 494    void emit_shader_time_write(enum shader_time_shader_type type,
 495                                src_reg value);
 496
 497    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 498                             dst_reg dst, src_reg offset, src_reg src0,
 499                             src_reg src1);
 500
 501    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 502                                   src_reg offset);
 503
 504    src_reg get_scratch_offset(vec4_instruction *inst,
 505                               src_reg *reladdr, int reg_offset);
 506    src_reg get_pull_constant_offset(vec4_instruction *inst,
 507                                     src_reg *reladdr, int reg_offset);
 508    void emit_scratch_read(vec4_instruction *inst,
 509                           dst_reg dst,
 510                           src_reg orig_src,
 511                           int base_offset);
 512    void emit_scratch_write(vec4_instruction *inst,
 513                            int base_offset);
 514    void emit_pull_constant_load(vec4_instruction *inst,
 515                                 dst_reg dst,
 516                                 src_reg orig_src,
 517                                 int base_offset);
 518
 519    bool try_emit_sat(ir_expression *ir);
 520    bool try_emit_mad(ir_expression *ir, int mul_arg);
 521    void resolve_ud_negate(src_reg *reg);
 522
 523    src_reg get_timestamp();
 524
 525    bool process_move_condition(ir_rvalue *ir);
 526
 527    void dump_instruction(backend_instruction *inst);
 528
 529    void visit_atomic_counter_intrinsic(ir_call *ir);
 530
 531 protected:
 532    void emit_vertex();
 533    void lower_attributes_to_hw_regs(const int *attribute_map,
 534                                     bool interleaved);
 535    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 536                                    int reg_node_count);
 537    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 538    virtual void setup_payload() = 0;
 539    virtual void emit_prolog() = 0;
 540    virtual void emit_program_code() = 0;
 541    virtual void emit_thread_end() = 0;
 542    virtual void emit_urb_write_header(int mrf) = 0;
 543    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 544    virtual int compute_array_stride(ir_dereference_array *ir);
 545
 546    const bool debug_flag;
 547
 548 private:
 549    /**
 550     * If true, then register allocation should fail instead of spilling.
 551     */
 552    const bool no_spills;
 553
 554    const shader_time_shader_type st_base;
 555    const shader_time_shader_type st_written;
 556    const shader_time_shader_type st_reset;
 557 };
 558
 559
 560 /**
 561  * The vertex shader code generator.
 562  *
 563  * Translates VS IR to actual i965 assembly code.
 564  */
 565 class vec4_generator
 566 {
 567 public:
 568    vec4_generator(struct brw_context *brw,
 569                   struct gl_shader_program *shader_prog,
 570                   struct gl_program *prog,
 571                   struct brw_vec4_prog_data *prog_data,
 572                   void *mem_ctx,
 573                   bool debug_flag);
 574    ~vec4_generator();
 575
 576    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 577
 578 private:
 579    void generate_code(exec_list *instructions);
 580    void generate_vec4_instruction(vec4_instruction *inst,
 581                                   struct brw_reg dst,
 582                                   struct brw_reg *src);
 583
 584    void generate_math1_gen4(vec4_instruction *inst,
 585                             struct brw_reg dst,
 586                             struct brw_reg src);
 587    void generate_math1_gen6(vec4_instruction *inst,
 588                             struct brw_reg dst,
 589                             struct brw_reg src);
 590    void generate_math2_gen4(vec4_instruction *inst,
 591                             struct brw_reg dst,
 592                             struct brw_reg src0,
 593                             struct brw_reg src1);
 594    void generate_math2_gen6(vec4_instruction *inst,
 595                             struct brw_reg dst,
 596                             struct brw_reg src0,
 597                             struct brw_reg src1);
 598    void generate_math2_gen7(vec4_instruction *inst,
 599                             struct brw_reg dst,
 600                             struct brw_reg src0,
 601                             struct brw_reg src1);
 602
 603    void generate_tex(vec4_instruction *inst,
 604                      struct brw_reg dst,
 605                      struct brw_reg src);
 606
 607    void generate_vs_urb_write(vec4_instruction *inst);
 608    void generate_gs_urb_write(vec4_instruction *inst);
 609    void generate_gs_thread_end(vec4_instruction *inst);
 610    void generate_gs_set_write_offset(struct brw_reg dst,
 611                                      struct brw_reg src0,
 612                                      struct brw_reg src1);
 613    void generate_gs_set_vertex_count(struct brw_reg dst,
 614                                      struct brw_reg src);
 615    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 616    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 617    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 618    void generate_oword_dual_block_offsets(struct brw_reg m1,
 619                                           struct brw_reg index);
 620    void generate_scratch_write(vec4_instruction *inst,
 621                                struct brw_reg dst,
 622                                struct brw_reg src,
 623                                struct brw_reg index);
 624    void generate_scratch_read(vec4_instruction *inst,
 625                               struct brw_reg dst,
 626                               struct brw_reg index);
 627    void generate_pull_constant_load(vec4_instruction *inst,
 628                                     struct brw_reg dst,
 629                                     struct brw_reg index,
 630                                     struct brw_reg offset);
 631    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 632                                          struct brw_reg dst,
 633                                          struct brw_reg surf_index,
 634                                          struct brw_reg offset);
 635    void generate_unpack_flags(vec4_instruction *inst,
 636                               struct brw_reg dst);
 637
 638    void generate_untyped_atomic(vec4_instruction *inst,
 639                                 struct brw_reg dst,
 640                                 struct brw_reg atomic_op,
 641                                 struct brw_reg surf_index);
 642
 643    void generate_untyped_surface_read(vec4_instruction *inst,
 644                                       struct brw_reg dst,
 645                                       struct brw_reg surf_index);
 646
 647    void mark_surface_used(unsigned surf_index);
 648
 649    struct brw_context *brw;
 650
 651    struct brw_compile *p;
 652
 653    struct gl_shader_program *shader_prog;
 654    const struct gl_program *prog;
 655
 656    struct brw_vec4_prog_data *prog_data;
 657
 658    void *mem_ctx;
 659    const bool debug_flag;
 660 };
 661
 662 /**
 663  * The vertex shader code generator.
 664  *
 665  * Translates VS IR to actual i965 assembly code.
 666  */
 667 class gen8_vec4_generator : public gen8_generator
 668 {
 669 public:
 670    gen8_vec4_generator(struct brw_context *brw,
 671                        struct gl_shader_program *shader_prog,
 672                        struct gl_program *prog,
 673                        struct brw_vec4_prog_data *prog_data,
 674                        void *mem_ctx,
 675                        bool debug_flag);
 676    ~gen8_vec4_generator();
 677
 678    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 679
 680 private:
 681    void generate_code(exec_list *instructions);
 682    void generate_vec4_instruction(vec4_instruction *inst,
 683                                   struct brw_reg dst,
 684                                   struct brw_reg *src);
 685
 686    void generate_tex(vec4_instruction *inst,
 687                      struct brw_reg dst);
 688
 689    void generate_urb_write(vec4_instruction *ir, bool copy_g0);
 690    void generate_gs_thread_end(vec4_instruction *ir);
 691    void generate_gs_set_write_offset(struct brw_reg dst,
 692                                      struct brw_reg src0,
 693                                      struct brw_reg src1);
 694    void generate_gs_set_vertex_count(struct brw_reg dst,
 695                                      struct brw_reg src);
 696    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 697    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 698    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 699
 700    void generate_oword_dual_block_offsets(struct brw_reg m1,
 701                                           struct brw_reg index);
 702    void generate_scratch_write(vec4_instruction *inst,
 703                                struct brw_reg dst,
 704                                struct brw_reg src,
 705                                struct brw_reg index);
 706    void generate_scratch_read(vec4_instruction *inst,
 707                               struct brw_reg dst,
 708                               struct brw_reg index);
 709    void generate_pull_constant_load(vec4_instruction *inst,
 710                                     struct brw_reg dst,
 711                                     struct brw_reg index,
 712                                     struct brw_reg offset);
 713
 714    void mark_surface_used(unsigned surf_index);
 715
 716    struct brw_vec4_prog_data *prog_data;
 717
 718    const bool debug_flag;
 719 };
 720
 721
 722 } /* namespace brw */
 723 #endif /* __cplusplus */
 724
 725 #endif /* BRW_VEC4_H */