src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39
  40 #ifdef __cplusplus
  41 }; /* extern "C" */
  42 #endif
  43
  44 #include "glsl/ir.h"
  45
  46
  47 struct brw_vec4_compile {
  48    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  49 };
  50
  51
  52 struct brw_vec4_prog_key {
  53    GLuint program_string_id;
  54
  55    /**
  56     * True if at least one clip flag is enabled, regardless of whether the
  57     * shader uses clip planes or gl_ClipDistance.
  58     */
  59    GLuint userclip_active:1;
  60
  61    /**
  62     * How many user clipping planes are being uploaded to the vertex shader as
  63     * push constants.
  64     */
  65    GLuint nr_userclip_plane_consts:4;
  66
  67    GLuint clamp_vertex_color:1;
  68
  69    struct brw_sampler_prog_key_data tex;
  70 };
  71
  72
  73 #ifdef __cplusplus
  74 extern "C" {
  75 #endif
  76
  77 void
  78 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
  79                                        struct brw_vec4_prog_key *key,
  80                                        GLuint id, struct gl_program *prog);
  81 bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
  82                                 const struct brw_vec4_prog_data *b);
  83 void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data);
  84
  85 #ifdef __cplusplus
  86 } /* extern "C" */
  87
  88 namespace brw {
  89
  90 class dst_reg;
  91
  92 unsigned
  93 swizzle_for_size(int size);
  94
  95 class reg
  96 {
  97 public:
  98    /** Register file: GRF, MRF, IMM. */
  99    enum register_file file;
 100    /** virtual register number.  0 = fixed hw reg */
 101    int reg;
 102    /** Offset within the virtual register. */
 103    int reg_offset;
 104    /** Register type.  BRW_REGISTER_TYPE_* */
 105    int type;
 106    struct brw_reg fixed_hw_reg;
 107
 108    /** Value for file == BRW_IMMMEDIATE_FILE */
 109    union {
 110       int32_t i;
 111       uint32_t u;
 112       float f;
 113    } imm;
 114 };
 115
 116 class src_reg : public reg
 117 {
 118 public:
 119    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
 120
 121    void init();
 122
 123    src_reg(register_file file, int reg, const glsl_type *type);
 124    src_reg();
 125    src_reg(float f);
 126    src_reg(uint32_t u);
 127    src_reg(int32_t i);
 128
 129    bool equals(src_reg *r);
 130    bool is_zero() const;
 131    bool is_one() const;
 132
 133    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 134
 135    explicit src_reg(dst_reg reg);
 136
 137    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 138    bool negate;
 139    bool abs;
 140
 141    src_reg *reladdr;
 142 };
 143
 144 class dst_reg : public reg
 145 {
 146 public:
 147    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 148
 149    void init();
 150
 151    dst_reg();
 152    dst_reg(register_file file, int reg);
 153    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 154    dst_reg(struct brw_reg reg);
 155    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 156
 157    explicit dst_reg(src_reg reg);
 158
 159    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 160
 161    src_reg *reladdr;
 162 };
 163
 164 dst_reg
 165 with_writemask(dst_reg const &r, int mask);
 166
 167 class vec4_instruction : public backend_instruction {
 168 public:
 169    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 170
 171    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 172                     dst_reg dst = dst_reg(),
 173                     src_reg src0 = src_reg(),
 174                     src_reg src1 = src_reg(),
 175                     src_reg src2 = src_reg());
 176
 177    struct brw_reg get_dst(void);
 178    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 179
 180    dst_reg dst;
 181    src_reg src[3];
 182
 183    bool saturate;
 184    bool force_writemask_all;
 185    bool no_dd_clear, no_dd_check;
 186
 187    int conditional_mod; /**< BRW_CONDITIONAL_* */
 188
 189    int sampler;
 190    uint32_t texture_offset; /**< Texture Offset bitfield */
 191    int target; /**< MRT target. */
 192    bool shadow_compare;
 193
 194    enum brw_urb_write_flags urb_write_flags;
 195    bool header_present;
 196    int mlen; /**< SEND message length */
 197    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 198
 199    uint32_t offset; /* spill/unspill offset */
 200    /** @{
 201     * Annotation for the generated IR.  One of the two can be set.
 202     */
 203    const void *ir;
 204    const char *annotation;
 205
 206    bool is_send_from_grf();
 207    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 208    void reswizzle_dst(int dst_writemask, int swizzle);
 209
 210    bool depends_on_flags()
 211    {
 212       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 213    }
 214 };
 215
 216 /**
 217  * The vertex shader front-end.
 218  *
 219  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 220  * fixed-function) into VS IR.
 221  */
 222 class vec4_visitor : public backend_visitor
 223 {
 224 public:
 225    vec4_visitor(struct brw_context *brw,
 226                 struct brw_vec4_compile *c,
 227                 struct gl_program *prog,
 228                 const struct brw_vec4_prog_key *key,
 229                 struct brw_vec4_prog_data *prog_data,
 230                 struct gl_shader_program *shader_prog,
 231                 struct brw_shader *shader,
 232                 void *mem_ctx,
 233                 bool debug_flag,
 234                 bool no_spills);
 235    ~vec4_visitor();
 236
 237    dst_reg dst_null_f()
 238    {
 239       return dst_reg(brw_null_reg());
 240    }
 241
 242    dst_reg dst_null_d()
 243    {
 244       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 245    }
 246
 247    dst_reg dst_null_ud()
 248    {
 249       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 250    }
 251
 252    struct brw_vec4_compile *c;
 253    const struct brw_vec4_prog_key *key;
 254    struct brw_vec4_prog_data *prog_data;
 255    unsigned int sanity_param_count;
 256
 257    char *fail_msg;
 258    bool failed;
 259
 260    /**
 261     * GLSL IR currently being processed, which is associated with our
 262     * driver IR instructions for debugging purposes.
 263     */
 264    const void *base_ir;
 265    const char *current_annotation;
 266
 267    int *virtual_grf_sizes;
 268    int virtual_grf_count;
 269    int virtual_grf_array_size;
 270    int first_non_payload_grf;
 271    unsigned int max_grf;
 272    int *virtual_grf_start;
 273    int *virtual_grf_end;
 274    dst_reg userplane[MAX_CLIP_PLANES];
 275
 276    /**
 277     * This is the size to be used for an array with an element per
 278     * reg_offset
 279     */
 280    int virtual_grf_reg_count;
 281    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 282    int *virtual_grf_reg_map;
 283
 284    bool live_intervals_valid;
 285
 286    dst_reg *variable_storage(ir_variable *var);
 287
 288    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 289
 290    bool need_all_constants_in_pull_buffer;
 291
 292    /**
 293     * \name Visit methods
 294     *
 295     * As typical for the visitor pattern, there must be one \c visit method for
 296     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 297     * the hierarchy should not have \c visit methods.
 298     */
 299    /*@{*/
 300    virtual void visit(ir_variable *);
 301    virtual void visit(ir_loop *);
 302    virtual void visit(ir_loop_jump *);
 303    virtual void visit(ir_function_signature *);
 304    virtual void visit(ir_function *);
 305    virtual void visit(ir_expression *);
 306    virtual void visit(ir_swizzle *);
 307    virtual void visit(ir_dereference_variable  *);
 308    virtual void visit(ir_dereference_array *);
 309    virtual void visit(ir_dereference_record *);
 310    virtual void visit(ir_assignment *);
 311    virtual void visit(ir_constant *);
 312    virtual void visit(ir_call *);
 313    virtual void visit(ir_return *);
 314    virtual void visit(ir_discard *);
 315    virtual void visit(ir_texture *);
 316    virtual void visit(ir_if *);
 317    virtual void visit(ir_emit_vertex *);
 318    virtual void visit(ir_end_primitive *);
 319    /*@}*/
 320
 321    src_reg result;
 322
 323    /* Regs for vertex results.  Generated at ir_variable visiting time
 324     * for the ir->location's used.
 325     */
 326    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 327    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 328    int uniform_size[MAX_UNIFORMS];
 329    int uniform_vector_size[MAX_UNIFORMS];
 330    int uniforms;
 331
 332    src_reg shader_start_time;
 333
 334    struct hash_table *variable_ht;
 335
 336    bool run(void);
 337    void fail(const char *msg, ...);
 338
 339    int virtual_grf_alloc(int size);
 340    void setup_uniform_clipplane_values();
 341    void setup_uniform_values(ir_variable *ir);
 342    void setup_builtin_uniform_values(ir_variable *ir);
 343    int setup_uniforms(int payload_reg);
 344    bool reg_allocate_trivial();
 345    bool reg_allocate();
 346    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 347    int choose_spill_reg(struct ra_graph *g);
 348    void spill_reg(int spill_reg);
 349    void move_grf_array_access_to_scratch();
 350    void move_uniform_array_access_to_pull_constants();
 351    void move_push_constants_to_pull_constants();
 352    void split_uniform_registers();
 353    void pack_uniform_registers();
 354    void calculate_live_intervals();
 355    void split_virtual_grfs();
 356    bool dead_code_eliminate();
 357    bool virtual_grf_interferes(int a, int b);
 358    bool opt_copy_propagation();
 359    bool opt_algebraic();
 360    bool opt_register_coalesce();
 361    void opt_set_dependency_control();
 362    void opt_schedule_instructions();
 363
 364    bool can_do_source_mods(vec4_instruction *inst);
 365
 366    vec4_instruction *emit(vec4_instruction *inst);
 367
 368    vec4_instruction *emit(enum opcode opcode);
 369
 370    vec4_instruction *emit(enum opcode opcode, dst_reg dst);
 371
 372    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 373
 374    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 375                           src_reg src0, src_reg src1);
 376
 377    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 378                           src_reg src0, src_reg src1, src_reg src2);
 379
 380    vec4_instruction *emit_before(vec4_instruction *inst,
 381                                  vec4_instruction *new_inst);
 382
 383    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 384    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 385    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 386    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 387    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 388    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 389    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 390    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 391    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 392    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 393    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 394    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 395    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 396    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 397    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 398    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 399    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 400    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 401    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 402    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 403    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 404    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 405                          uint32_t condition);
 406    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 407    vec4_instruction *IF(uint32_t predicate);
 408    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 409    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 410    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 411    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 412    vec4_instruction *BFREV(dst_reg dst, src_reg value);
 413    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
 414    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
 415    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
 416    vec4_instruction *FBH(dst_reg dst, src_reg value);
 417    vec4_instruction *FBL(dst_reg dst, src_reg value);
 418    vec4_instruction *CBIT(dst_reg dst, src_reg value);
 419    vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
 420    vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1);
 421    vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1);
 422
 423    int implied_mrf_writes(vec4_instruction *inst);
 424
 425    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 426                                dst_reg dst,
 427                                src_reg src,
 428                                vec4_instruction *pre_rhs_inst,
 429                                vec4_instruction *last_rhs_inst);
 430
 431    bool try_copy_propagation(vec4_instruction *inst, int arg,
 432                              src_reg *values[4]);
 433
 434    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 435    void visit_instructions(const exec_list *list);
 436
 437    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 438                     src_reg src0, src_reg src1, src_reg one);
 439
 440    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 441    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 442    void emit_if_gen6(ir_if *ir);
 443
 444    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 445
 446    void emit_block_move(dst_reg *dst, src_reg *src,
 447                         const struct glsl_type *type, uint32_t predicate);
 448
 449    void emit_constant_values(dst_reg *dst, ir_constant *value);
 450
 451    /**
 452     * Emit the correct dot-product instruction for the type of arguments
 453     */
 454    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 455
 456    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 457                     dst_reg dst, src_reg src0);
 458
 459    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 460                     dst_reg dst, src_reg src0, src_reg src1);
 461
 462    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 463                  dst_reg dst, const src_reg &src);
 464
 465    src_reg fix_3src_operand(src_reg src);
 466
 467    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 468    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 469    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 470    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 471    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 472    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 473    src_reg fix_math_operand(src_reg src);
 474
 475    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 476    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 477
 478    uint32_t gather_channel(ir_texture *ir, int sampler);
 479    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 480
 481    void emit_ndc_computation();
 482    void emit_psiz_and_flags(struct brw_reg reg);
 483    void emit_clip_distances(dst_reg reg, int offset);
 484    void emit_generic_urb_slot(dst_reg reg, int varying);
 485    void emit_urb_slot(int mrf, int varying);
 486
 487    void emit_shader_time_begin();
 488    void emit_shader_time_end();
 489    void emit_shader_time_write(enum shader_time_shader_type type,
 490                                src_reg value);
 491
 492    src_reg get_scratch_offset(vec4_instruction *inst,
 493                               src_reg *reladdr, int reg_offset);
 494    src_reg get_pull_constant_offset(vec4_instruction *inst,
 495                                     src_reg *reladdr, int reg_offset);
 496    void emit_scratch_read(vec4_instruction *inst,
 497                           dst_reg dst,
 498                           src_reg orig_src,
 499                           int base_offset);
 500    void emit_scratch_write(vec4_instruction *inst,
 501                            int base_offset);
 502    void emit_pull_constant_load(vec4_instruction *inst,
 503                                 dst_reg dst,
 504                                 src_reg orig_src,
 505                                 int base_offset);
 506
 507    bool try_emit_sat(ir_expression *ir);
 508    bool try_emit_mad(ir_expression *ir, int mul_arg);
 509    void resolve_ud_negate(src_reg *reg);
 510
 511    src_reg get_timestamp();
 512
 513    bool process_move_condition(ir_rvalue *ir);
 514
 515    void dump_instruction(backend_instruction *inst);
 516
 517 protected:
 518    void emit_vertex();
 519    void lower_attributes_to_hw_regs(const int *attribute_map,
 520                                     bool interleaved);
 521    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 522                                    int reg_node_count);
 523    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 524    virtual void setup_payload() = 0;
 525    virtual void emit_prolog() = 0;
 526    virtual void emit_program_code() = 0;
 527    virtual void emit_thread_end() = 0;
 528    virtual void emit_urb_write_header(int mrf) = 0;
 529    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 530    virtual int compute_array_stride(ir_dereference_array *ir);
 531
 532    const bool debug_flag;
 533
 534 private:
 535    /**
 536     * If true, then register allocation should fail instead of spilling.
 537     */
 538    const bool no_spills;
 539 };
 540
 541
 542 /**
 543  * The vertex shader code generator.
 544  *
 545  * Translates VS IR to actual i965 assembly code.
 546  */
 547 class vec4_generator
 548 {
 549 public:
 550    vec4_generator(struct brw_context *brw,
 551                   struct gl_shader_program *shader_prog,
 552                   struct gl_program *prog,
 553                   struct brw_vec4_prog_data *prog_data,
 554                   void *mem_ctx,
 555                   bool debug_flag);
 556    ~vec4_generator();
 557
 558    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 559
 560 private:
 561    void generate_code(exec_list *instructions);
 562    void generate_vec4_instruction(vec4_instruction *inst,
 563                                   struct brw_reg dst,
 564                                   struct brw_reg *src);
 565
 566    void generate_math1_gen4(vec4_instruction *inst,
 567                             struct brw_reg dst,
 568                             struct brw_reg src);
 569    void generate_math1_gen6(vec4_instruction *inst,
 570                             struct brw_reg dst,
 571                             struct brw_reg src);
 572    void generate_math2_gen4(vec4_instruction *inst,
 573                             struct brw_reg dst,
 574                             struct brw_reg src0,
 575                             struct brw_reg src1);
 576    void generate_math2_gen6(vec4_instruction *inst,
 577                             struct brw_reg dst,
 578                             struct brw_reg src0,
 579                             struct brw_reg src1);
 580    void generate_math2_gen7(vec4_instruction *inst,
 581                             struct brw_reg dst,
 582                             struct brw_reg src0,
 583                             struct brw_reg src1);
 584
 585    void generate_tex(vec4_instruction *inst,
 586                      struct brw_reg dst,
 587                      struct brw_reg src);
 588
 589    void generate_vs_urb_write(vec4_instruction *inst);
 590    void generate_gs_urb_write(vec4_instruction *inst);
 591    void generate_gs_thread_end(vec4_instruction *inst);
 592    void generate_gs_set_write_offset(struct brw_reg dst,
 593                                      struct brw_reg src0,
 594                                      struct brw_reg src1);
 595    void generate_gs_set_vertex_count(struct brw_reg dst,
 596                                      struct brw_reg src);
 597    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 598    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 599    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 600    void generate_oword_dual_block_offsets(struct brw_reg m1,
 601                                           struct brw_reg index);
 602    void generate_scratch_write(vec4_instruction *inst,
 603                                struct brw_reg dst,
 604                                struct brw_reg src,
 605                                struct brw_reg index);
 606    void generate_scratch_read(vec4_instruction *inst,
 607                               struct brw_reg dst,
 608                               struct brw_reg index);
 609    void generate_pull_constant_load(vec4_instruction *inst,
 610                                     struct brw_reg dst,
 611                                     struct brw_reg index,
 612                                     struct brw_reg offset);
 613    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 614                                          struct brw_reg dst,
 615                                          struct brw_reg surf_index,
 616                                          struct brw_reg offset);
 617    void generate_unpack_flags(vec4_instruction *inst,
 618                               struct brw_reg dst);
 619
 620    void generate_untyped_atomic(vec4_instruction *inst,
 621                                 struct brw_reg dst,
 622                                 struct brw_reg atomic_op,
 623                                 struct brw_reg surf_index);
 624
 625    void generate_untyped_surface_read(vec4_instruction *inst,
 626                                       struct brw_reg dst,
 627                                       struct brw_reg surf_index);
 628
 629    void mark_surface_used(unsigned surf_index);
 630
 631    struct brw_context *brw;
 632
 633    struct brw_compile *p;
 634
 635    struct gl_shader_program *shader_prog;
 636    struct gl_shader *shader;
 637    const struct gl_program *prog;
 638
 639    struct brw_vec4_prog_data *prog_data;
 640
 641    void *mem_ctx;
 642    const bool debug_flag;
 643 };
 644
 645 } /* namespace brw */
 646 #endif /* __cplusplus */
 647
 648 #endif /* BRW_VEC4_H */