src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 #include "brw_ir_vec4.h"
  35
  36 extern "C" {
  37 #endif
  38
  39 #include "brw_context.h"
  40 #include "brw_eu.h"
  41 #include "intel_asm_annotation.h"
  42
  43 #ifdef __cplusplus
  44 }; /* extern "C" */
  45 #endif
  46
  47 #include "glsl/ir.h"
  48 #include "glsl/nir/nir.h"
  49
  50
  51 #ifdef __cplusplus
  52 extern "C" {
  53 #endif
  54
  55 void
  56 brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx,
  57                                       struct brw_vue_prog_key *key,
  58                                       GLuint id, struct gl_program *prog);
  59
  60 #ifdef __cplusplus
  61 } /* extern "C" */
  62
  63 namespace brw {
  64
  65 class vec4_live_variables;
  66
  67 /**
  68  * The vertex shader front-end.
  69  *
  70  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
  71  * fixed-function) into VS IR.
  72  */
  73 class vec4_visitor : public backend_shader, public ir_visitor
  74 {
  75 public:
  76    vec4_visitor(const struct brw_compiler *compiler,
  77                 void *log_data,
  78                 struct gl_program *prog,
  79                 const struct brw_vue_prog_key *key,
  80                 struct brw_vue_prog_data *prog_data,
  81                 struct gl_shader_program *shader_prog,
  82                 gl_shader_stage stage,
  83                 void *mem_ctx,
  84                 bool no_spills,
  85                 int shader_time_index);
  86    ~vec4_visitor();
  87
  88    dst_reg dst_null_f()
  89    {
  90       return dst_reg(brw_null_reg());
  91    }
  92
  93    dst_reg dst_null_d()
  94    {
  95       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
  96    }
  97
  98    dst_reg dst_null_ud()
  99    {
 100       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 101    }
 102
 103    const struct brw_vue_prog_key * const key;
 104    struct brw_vue_prog_data * const prog_data;
 105    unsigned int sanity_param_count;
 106
 107    char *fail_msg;
 108    bool failed;
 109
 110    /**
 111     * GLSL IR currently being processed, which is associated with our
 112     * driver IR instructions for debugging purposes.
 113     */
 114    const void *base_ir;
 115    const char *current_annotation;
 116
 117    int first_non_payload_grf;
 118    unsigned int max_grf;
 119    int *virtual_grf_start;
 120    int *virtual_grf_end;
 121    brw::vec4_live_variables *live_intervals;
 122    dst_reg userplane[MAX_CLIP_PLANES];
 123
 124    dst_reg *variable_storage(ir_variable *var);
 125
 126    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 127
 128    bool need_all_constants_in_pull_buffer;
 129
 130    /**
 131     * \name Visit methods
 132     *
 133     * As typical for the visitor pattern, there must be one \c visit method for
 134     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 135     * the hierarchy should not have \c visit methods.
 136     */
 137    /*@{*/
 138    virtual void visit(ir_variable *);
 139    virtual void visit(ir_loop *);
 140    virtual void visit(ir_loop_jump *);
 141    virtual void visit(ir_function_signature *);
 142    virtual void visit(ir_function *);
 143    virtual void visit(ir_expression *);
 144    virtual void visit(ir_swizzle *);
 145    virtual void visit(ir_dereference_variable  *);
 146    virtual void visit(ir_dereference_array *);
 147    virtual void visit(ir_dereference_record *);
 148    virtual void visit(ir_assignment *);
 149    virtual void visit(ir_constant *);
 150    virtual void visit(ir_call *);
 151    virtual void visit(ir_return *);
 152    virtual void visit(ir_discard *);
 153    virtual void visit(ir_texture *);
 154    virtual void visit(ir_if *);
 155    virtual void visit(ir_emit_vertex *);
 156    virtual void visit(ir_end_primitive *);
 157    virtual void visit(ir_barrier *);
 158    /*@}*/
 159
 160    src_reg result;
 161
 162    /* Regs for vertex results.  Generated at ir_variable visiting time
 163     * for the ir->location's used.
 164     */
 165    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 166    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 167    int *uniform_size;
 168    int *uniform_vector_size;
 169    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 170    int uniforms;
 171
 172    src_reg shader_start_time;
 173
 174    struct hash_table *variable_ht;
 175
 176    bool run(gl_clip_plane *clip_planes);
 177    void fail(const char *msg, ...);
 178
 179    void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
 180    virtual void setup_vector_uniform_values(const gl_constant_value *values,
 181                                             unsigned n);
 182    void setup_uniform_values(ir_variable *ir);
 183    void setup_builtin_uniform_values(ir_variable *ir);
 184    int setup_uniforms(int payload_reg);
 185
 186    bool reg_allocate_trivial();
 187    bool reg_allocate();
 188    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 189    int choose_spill_reg(struct ra_graph *g);
 190    void spill_reg(int spill_reg);
 191    void move_grf_array_access_to_scratch();
 192    void move_uniform_array_access_to_pull_constants();
 193    void move_push_constants_to_pull_constants();
 194    void split_uniform_registers();
 195    void pack_uniform_registers();
 196    void calculate_live_intervals();
 197    void invalidate_live_intervals();
 198    void split_virtual_grfs();
 199    bool opt_vector_float();
 200    bool opt_reduce_swizzle();
 201    bool dead_code_eliminate();
 202    int var_range_start(unsigned v, unsigned n) const;
 203    int var_range_end(unsigned v, unsigned n) const;
 204    bool virtual_grf_interferes(int a, int b);
 205    bool opt_copy_propagation(bool do_constant_prop = true);
 206    bool opt_cse_local(bblock_t *block);
 207    bool opt_cse();
 208    bool opt_algebraic();
 209    bool opt_register_coalesce();
 210    bool eliminate_find_live_channel();
 211    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 212    void opt_set_dependency_control();
 213    void opt_schedule_instructions();
 214
 215    vec4_instruction *emit(vec4_instruction *inst);
 216
 217    vec4_instruction *emit(enum opcode opcode);
 218    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 219    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 220                           const src_reg &src0);
 221    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 222                           const src_reg &src0, const src_reg &src1);
 223    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 224                           const src_reg &src0, const src_reg &src1,
 225                           const src_reg &src2);
 226
 227    vec4_instruction *emit_before(bblock_t *block,
 228                                  vec4_instruction *inst,
 229                                  vec4_instruction *new_inst);
 230
 231 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 232 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 233 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 234    EMIT1(MOV)
 235    EMIT1(NOT)
 236    EMIT1(RNDD)
 237    EMIT1(RNDE)
 238    EMIT1(RNDZ)
 239    EMIT1(FRC)
 240    EMIT1(F32TO16)
 241    EMIT1(F16TO32)
 242    EMIT2(ADD)
 243    EMIT2(MUL)
 244    EMIT2(MACH)
 245    EMIT2(MAC)
 246    EMIT2(AND)
 247    EMIT2(OR)
 248    EMIT2(XOR)
 249    EMIT2(DP3)
 250    EMIT2(DP4)
 251    EMIT2(DPH)
 252    EMIT2(SHL)
 253    EMIT2(SHR)
 254    EMIT2(ASR)
 255    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 256                          enum brw_conditional_mod condition);
 257    vec4_instruction *IF(src_reg src0, src_reg src1,
 258                         enum brw_conditional_mod condition);
 259    vec4_instruction *IF(enum brw_predicate predicate);
 260    EMIT1(SCRATCH_READ)
 261    EMIT2(SCRATCH_WRITE)
 262    EMIT3(LRP)
 263    EMIT1(BFREV)
 264    EMIT3(BFE)
 265    EMIT2(BFI1)
 266    EMIT3(BFI2)
 267    EMIT1(FBH)
 268    EMIT1(FBL)
 269    EMIT1(CBIT)
 270    EMIT3(MAD)
 271    EMIT2(ADDC)
 272    EMIT2(SUBB)
 273 #undef EMIT1
 274 #undef EMIT2
 275 #undef EMIT3
 276
 277    int implied_mrf_writes(vec4_instruction *inst);
 278
 279    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 280                                dst_reg dst,
 281                                src_reg src,
 282                                vec4_instruction *pre_rhs_inst,
 283                                vec4_instruction *last_rhs_inst);
 284
 285    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 286    void visit_instructions(const exec_list *list);
 287
 288    void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 289                     src_reg src0, src_reg src1, src_reg one);
 290
 291    void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
 292    void emit_if_gen6(ir_if *ir);
 293
 294    vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 295                                  src_reg src0, src_reg src1);
 296
 297    vec4_instruction *emit_lrp(const dst_reg &dst, const src_reg &x,
 298                               const src_reg &y, const src_reg &a);
 299
 300    /**
 301     * Copy any live channel from \p src to the first channel of the
 302     * result.
 303     */
 304    src_reg emit_uniformize(const src_reg &src);
 305
 306    void emit_block_move(dst_reg *dst, src_reg *src,
 307                         const struct glsl_type *type, brw_predicate predicate);
 308
 309    void emit_constant_values(dst_reg *dst, ir_constant *value);
 310
 311    /**
 312     * Emit the correct dot-product instruction for the type of arguments
 313     */
 314    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 315
 316    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 317                     dst_reg dst, src_reg src0);
 318
 319    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 320                     dst_reg dst, src_reg src0, src_reg src1);
 321
 322    src_reg fix_3src_operand(src_reg src);
 323
 324    vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 325                                const src_reg &src1 = src_reg());
 326
 327    src_reg fix_math_operand(src_reg src);
 328
 329    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 330    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 331    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 332    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 333    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 334    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 335
 336    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 337    src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
 338                           src_reg sampler);
 339    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 340    void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 341
 342    void emit_ndc_computation();
 343    void emit_psiz_and_flags(dst_reg reg);
 344    void emit_clip_distances(dst_reg reg, int offset);
 345    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
 346    void emit_urb_slot(dst_reg reg, int varying);
 347
 348    void emit_shader_time_begin();
 349    void emit_shader_time_end();
 350    void emit_shader_time_write(int shader_time_subindex, src_reg value);
 351
 352    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 353                             dst_reg dst, src_reg offset, src_reg src0,
 354                             src_reg src1);
 355
 356    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 357                                   src_reg offset);
 358
 359    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 360                               src_reg *reladdr, int reg_offset);
 361    src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
 362                                     src_reg *reladdr, int reg_offset);
 363    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 364                           dst_reg dst,
 365                           src_reg orig_src,
 366                           int base_offset);
 367    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 368                            int base_offset);
 369    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 370                                 dst_reg dst,
 371                                 src_reg orig_src,
 372                                 int base_offset);
 373    void emit_pull_constant_load_reg(dst_reg dst,
 374                                     src_reg surf_index,
 375                                     src_reg offset,
 376                                     bblock_t *before_block,
 377                                     vec4_instruction *before_inst);
 378    src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
 379                                 vec4_instruction *inst, src_reg src);
 380
 381    bool try_emit_mad(ir_expression *ir);
 382    bool try_emit_b2f_of_compare(ir_expression *ir);
 383    void resolve_ud_negate(src_reg *reg);
 384    void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
 385
 386    src_reg get_timestamp();
 387
 388    bool process_move_condition(ir_rvalue *ir);
 389
 390    void dump_instruction(backend_instruction *inst);
 391    void dump_instruction(backend_instruction *inst, FILE *file);
 392
 393    void visit_atomic_counter_intrinsic(ir_call *ir);
 394
 395    int type_size(const struct glsl_type *type);
 396    bool is_high_sampler(src_reg sampler);
 397
 398    virtual void emit_nir_code();
 399    virtual void nir_setup_inputs(nir_shader *shader);
 400    virtual void nir_setup_uniforms(nir_shader *shader);
 401    virtual void nir_setup_uniform(nir_variable *var);
 402    virtual void nir_setup_builtin_uniform(nir_variable *var);
 403    virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr);
 404    virtual void nir_setup_system_values(nir_shader *shader);
 405    virtual void nir_emit_impl(nir_function_impl *impl);
 406    virtual void nir_emit_cf_list(exec_list *list);
 407    virtual void nir_emit_if(nir_if *if_stmt);
 408    virtual void nir_emit_loop(nir_loop *loop);
 409    virtual void nir_emit_block(nir_block *block);
 410    virtual void nir_emit_instr(nir_instr *instr);
 411    virtual void nir_emit_load_const(nir_load_const_instr *instr);
 412    virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
 413    virtual void nir_emit_alu(nir_alu_instr *instr);
 414    virtual void nir_emit_jump(nir_jump_instr *instr);
 415    virtual void nir_emit_texture(nir_tex_instr *instr);
 416
 417    dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);
 418    dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);
 419    dst_reg get_nir_dest(nir_dest dest);
 420    src_reg get_nir_src(nir_src src, enum brw_reg_type type,
 421                        unsigned num_components = 4);
 422    src_reg get_nir_src(nir_src src, nir_alu_type type,
 423                        unsigned num_components = 4);
 424    src_reg get_nir_src(nir_src src,
 425                        unsigned num_components = 4);
 426
 427    virtual dst_reg *make_reg_for_system_value(int location,
 428                                               const glsl_type *type) = 0;
 429
 430    dst_reg *nir_locals;
 431    dst_reg *nir_ssa_values;
 432    src_reg *nir_inputs;
 433    unsigned *nir_uniform_driver_location;
 434    dst_reg *nir_system_values;
 435
 436 protected:
 437    void emit_vertex();
 438    void lower_attributes_to_hw_regs(const int *attribute_map,
 439                                     bool interleaved);
 440    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 441                                    int reg_node_count);
 442    virtual void assign_binding_table_offsets();
 443    virtual void setup_payload() = 0;
 444    virtual void emit_prolog() = 0;
 445    virtual void emit_program_code() = 0;
 446    virtual void emit_thread_end() = 0;
 447    virtual void emit_urb_write_header(int mrf) = 0;
 448    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 449    virtual int compute_array_stride(ir_dereference_array *ir);
 450
 451 private:
 452    /**
 453     * If true, then register allocation should fail instead of spilling.
 454     */
 455    const bool no_spills;
 456
 457    int shader_time_index;
 458
 459    unsigned last_scratch; /**< measured in 32-byte (register size) units */
 460 };
 461
 462
 463 /**
 464  * The vertex shader code generator.
 465  *
 466  * Translates VS IR to actual i965 assembly code.
 467  */
 468 class vec4_generator
 469 {
 470 public:
 471    vec4_generator(const struct brw_compiler *compiler, void *log_data,
 472                   struct gl_shader_program *shader_prog,
 473                   struct gl_program *prog,
 474                   struct brw_vue_prog_data *prog_data,
 475                   void *mem_ctx,
 476                   bool debug_flag,
 477                   const char *stage_name,
 478                   const char *stage_abbrev);
 479    ~vec4_generator();
 480
 481    const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 482
 483 private:
 484    void generate_code(const cfg_t *cfg);
 485
 486    void generate_math1_gen4(vec4_instruction *inst,
 487                             struct brw_reg dst,
 488                             struct brw_reg src);
 489    void generate_math2_gen4(vec4_instruction *inst,
 490                             struct brw_reg dst,
 491                             struct brw_reg src0,
 492                             struct brw_reg src1);
 493    void generate_math_gen6(vec4_instruction *inst,
 494                            struct brw_reg dst,
 495                            struct brw_reg src0,
 496                            struct brw_reg src1);
 497
 498    void generate_tex(vec4_instruction *inst,
 499                      struct brw_reg dst,
 500                      struct brw_reg src,
 501                      struct brw_reg sampler_index);
 502
 503    void generate_vs_urb_write(vec4_instruction *inst);
 504    void generate_gs_urb_write(vec4_instruction *inst);
 505    void generate_gs_urb_write_allocate(vec4_instruction *inst);
 506    void generate_gs_thread_end(vec4_instruction *inst);
 507    void generate_gs_set_write_offset(struct brw_reg dst,
 508                                      struct brw_reg src0,
 509                                      struct brw_reg src1);
 510    void generate_gs_set_vertex_count(struct brw_reg dst,
 511                                      struct brw_reg src);
 512    void generate_gs_svb_write(vec4_instruction *inst,
 513                               struct brw_reg dst,
 514                               struct brw_reg src0,
 515                               struct brw_reg src1);
 516    void generate_gs_svb_set_destination_index(vec4_instruction *inst,
 517                                               struct brw_reg dst,
 518                                               struct brw_reg src);
 519    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
 520    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 521    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 522    void generate_gs_get_instance_id(struct brw_reg dst);
 523    void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
 524                                            struct brw_reg src0,
 525                                            struct brw_reg src1,
 526                                            struct brw_reg src2);
 527    void generate_gs_ff_sync(vec4_instruction *inst,
 528                             struct brw_reg dst,
 529                             struct brw_reg src0,
 530                             struct brw_reg src1);
 531    void generate_gs_set_primitive_id(struct brw_reg dst);
 532    void generate_oword_dual_block_offsets(struct brw_reg m1,
 533                                           struct brw_reg index);
 534    void generate_scratch_write(vec4_instruction *inst,
 535                                struct brw_reg dst,
 536                                struct brw_reg src,
 537                                struct brw_reg index);
 538    void generate_scratch_read(vec4_instruction *inst,
 539                               struct brw_reg dst,
 540                               struct brw_reg index);
 541    void generate_pull_constant_load(vec4_instruction *inst,
 542                                     struct brw_reg dst,
 543                                     struct brw_reg index,
 544                                     struct brw_reg offset);
 545    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 546                                          struct brw_reg dst,
 547                                          struct brw_reg surf_index,
 548                                          struct brw_reg offset);
 549    void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
 550                                          struct brw_reg dst);
 551    void generate_unpack_flags(struct brw_reg dst);
 552
 553    const struct brw_compiler *compiler;
 554    void *log_data; /* Passed to compiler->*_log functions */
 555
 556    const struct brw_device_info *devinfo;
 557
 558    struct brw_codegen *p;
 559
 560    struct gl_shader_program *shader_prog;
 561    const struct gl_program *prog;
 562
 563    struct brw_vue_prog_data *prog_data;
 564
 565    void *mem_ctx;
 566    const char *stage_name;
 567    const char *stage_abbrev;
 568    const bool debug_flag;
 569 };
 570
 571 } /* namespace brw */
 572 #endif /* __cplusplus */
 573
 574 #endif /* BRW_VEC4_H */