src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39
  40 #ifdef __cplusplus
  41 }; /* extern "C" */
  42 #endif
  43
  44 #include "glsl/ir.h"
  45
  46
  47 struct brw_vec4_compile {
  48    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  49 };
  50
  51
  52 struct brw_vec4_prog_key {
  53    GLuint program_string_id;
  54
  55    /**
  56     * True if at least one clip flag is enabled, regardless of whether the
  57     * shader uses clip planes or gl_ClipDistance.
  58     */
  59    GLuint userclip_active:1;
  60
  61    /**
  62     * How many user clipping planes are being uploaded to the vertex shader as
  63     * push constants.
  64     */
  65    GLuint nr_userclip_plane_consts:4;
  66
  67    /**
  68     * True if the shader uses gl_ClipDistance, regardless of whether any clip
  69     * flags are enabled.
  70     */
  71    GLuint uses_clip_distance:1;
  72
  73    GLuint clamp_vertex_color:1;
  74
  75    struct brw_sampler_prog_key_data tex;
  76 };
  77
  78
  79 #ifdef __cplusplus
  80 extern "C" {
  81 #endif
  82
  83 bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
  84                                 const struct brw_vec4_prog_data *b);
  85 void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data);
  86
  87 #ifdef __cplusplus
  88 } /* extern "C" */
  89
  90 namespace brw {
  91
  92 class dst_reg;
  93
  94 unsigned
  95 swizzle_for_size(int size);
  96
  97 class reg
  98 {
  99 public:
 100    /** Register file: ARF, GRF, MRF, IMM. */
 101    enum register_file file;
 102    /** virtual register number.  0 = fixed hw reg */
 103    int reg;
 104    /** Offset within the virtual register. */
 105    int reg_offset;
 106    /** Register type.  BRW_REGISTER_TYPE_* */
 107    int type;
 108    struct brw_reg fixed_hw_reg;
 109
 110    /** Value for file == BRW_IMMMEDIATE_FILE */
 111    union {
 112       int32_t i;
 113       uint32_t u;
 114       float f;
 115    } imm;
 116 };
 117
 118 class src_reg : public reg
 119 {
 120 public:
 121    /* Callers of this ralloc-based new need not call delete. It's
 122     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 123    static void* operator new(size_t size, void *ctx)
 124    {
 125       void *node;
 126
 127       node = ralloc_size(ctx, size);
 128       assert(node != NULL);
 129
 130       return node;
 131    }
 132
 133    void init();
 134
 135    src_reg(register_file file, int reg, const glsl_type *type);
 136    src_reg();
 137    src_reg(float f);
 138    src_reg(uint32_t u);
 139    src_reg(int32_t i);
 140
 141    bool equals(src_reg *r);
 142    bool is_zero() const;
 143    bool is_one() const;
 144
 145    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 146
 147    explicit src_reg(dst_reg reg);
 148
 149    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 150    bool negate;
 151    bool abs;
 152
 153    src_reg *reladdr;
 154 };
 155
 156 class dst_reg : public reg
 157 {
 158 public:
 159    /* Callers of this ralloc-based new need not call delete. It's
 160     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 161    static void* operator new(size_t size, void *ctx)
 162    {
 163       void *node;
 164
 165       node = ralloc_size(ctx, size);
 166       assert(node != NULL);
 167
 168       return node;
 169    }
 170
 171    void init();
 172
 173    dst_reg();
 174    dst_reg(register_file file, int reg);
 175    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 176    dst_reg(struct brw_reg reg);
 177    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 178
 179    explicit dst_reg(src_reg reg);
 180
 181    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 182
 183    src_reg *reladdr;
 184 };
 185
 186 dst_reg
 187 with_writemask(dst_reg const &r, int mask);
 188
 189 class vec4_instruction : public backend_instruction {
 190 public:
 191    /* Callers of this ralloc-based new need not call delete. It's
 192     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 193    static void* operator new(size_t size, void *ctx)
 194    {
 195       void *node;
 196
 197       node = rzalloc_size(ctx, size);
 198       assert(node != NULL);
 199
 200       return node;
 201    }
 202
 203    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 204                     dst_reg dst = dst_reg(),
 205                     src_reg src0 = src_reg(),
 206                     src_reg src1 = src_reg(),
 207                     src_reg src2 = src_reg());
 208
 209    struct brw_reg get_dst(void);
 210    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 211
 212    dst_reg dst;
 213    src_reg src[3];
 214
 215    bool saturate;
 216    bool force_writemask_all;
 217    bool no_dd_clear, no_dd_check;
 218
 219    int conditional_mod; /**< BRW_CONDITIONAL_* */
 220
 221    int sampler;
 222    uint32_t texture_offset; /**< Texture Offset bitfield */
 223    int target; /**< MRT target. */
 224    bool shadow_compare;
 225
 226    enum brw_urb_write_flags urb_write_flags;
 227    bool header_present;
 228    int mlen; /**< SEND message length */
 229    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 230
 231    uint32_t offset; /* spill/unspill offset */
 232    /** @{
 233     * Annotation for the generated IR.  One of the two can be set.
 234     */
 235    const void *ir;
 236    const char *annotation;
 237
 238    bool is_send_from_grf();
 239    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 240    void reswizzle_dst(int dst_writemask, int swizzle);
 241
 242    bool depends_on_flags()
 243    {
 244       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 245    }
 246 };
 247
 248 /**
 249  * The vertex shader front-end.
 250  *
 251  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 252  * fixed-function) into VS IR.
 253  */
 254 class vec4_visitor : public backend_visitor
 255 {
 256 public:
 257    vec4_visitor(struct brw_context *brw,
 258                 struct brw_vec4_compile *c,
 259                 struct gl_program *prog,
 260                 const struct brw_vec4_prog_key *key,
 261                 struct brw_vec4_prog_data *prog_data,
 262                 struct gl_shader_program *shader_prog,
 263                 struct brw_shader *shader,
 264                 void *mem_ctx,
 265                 bool debug_flag);
 266    ~vec4_visitor();
 267
 268    dst_reg dst_null_f()
 269    {
 270       return dst_reg(brw_null_reg());
 271    }
 272
 273    dst_reg dst_null_d()
 274    {
 275       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 276    }
 277
 278    struct gl_program *prog;
 279    struct brw_vec4_compile *c;
 280    const struct brw_vec4_prog_key *key;
 281    struct brw_vec4_prog_data *prog_data;
 282    unsigned int sanity_param_count;
 283
 284    char *fail_msg;
 285    bool failed;
 286
 287    /**
 288     * GLSL IR currently being processed, which is associated with our
 289     * driver IR instructions for debugging purposes.
 290     */
 291    const void *base_ir;
 292    const char *current_annotation;
 293
 294    int *virtual_grf_sizes;
 295    int virtual_grf_count;
 296    int virtual_grf_array_size;
 297    int first_non_payload_grf;
 298    unsigned int max_grf;
 299    int *virtual_grf_start;
 300    int *virtual_grf_end;
 301    dst_reg userplane[MAX_CLIP_PLANES];
 302
 303    /**
 304     * This is the size to be used for an array with an element per
 305     * reg_offset
 306     */
 307    int virtual_grf_reg_count;
 308    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 309    int *virtual_grf_reg_map;
 310
 311    bool live_intervals_valid;
 312
 313    dst_reg *variable_storage(ir_variable *var);
 314
 315    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 316
 317    bool need_all_constants_in_pull_buffer;
 318
 319    /**
 320     * \name Visit methods
 321     *
 322     * As typical for the visitor pattern, there must be one \c visit method for
 323     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 324     * the hierarchy should not have \c visit methods.
 325     */
 326    /*@{*/
 327    virtual void visit(ir_variable *);
 328    virtual void visit(ir_loop *);
 329    virtual void visit(ir_loop_jump *);
 330    virtual void visit(ir_function_signature *);
 331    virtual void visit(ir_function *);
 332    virtual void visit(ir_expression *);
 333    virtual void visit(ir_swizzle *);
 334    virtual void visit(ir_dereference_variable  *);
 335    virtual void visit(ir_dereference_array *);
 336    virtual void visit(ir_dereference_record *);
 337    virtual void visit(ir_assignment *);
 338    virtual void visit(ir_constant *);
 339    virtual void visit(ir_call *);
 340    virtual void visit(ir_return *);
 341    virtual void visit(ir_discard *);
 342    virtual void visit(ir_texture *);
 343    virtual void visit(ir_if *);
 344    virtual void visit(ir_emit_vertex *);
 345    virtual void visit(ir_end_primitive *);
 346    /*@}*/
 347
 348    src_reg result;
 349
 350    /* Regs for vertex results.  Generated at ir_variable visiting time
 351     * for the ir->location's used.
 352     */
 353    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 354    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 355    int uniform_size[MAX_UNIFORMS];
 356    int uniform_vector_size[MAX_UNIFORMS];
 357    int uniforms;
 358
 359    src_reg shader_start_time;
 360
 361    struct hash_table *variable_ht;
 362
 363    bool run(void);
 364    void fail(const char *msg, ...);
 365
 366    int virtual_grf_alloc(int size);
 367    void setup_uniform_clipplane_values();
 368    void setup_uniform_values(ir_variable *ir);
 369    void setup_builtin_uniform_values(ir_variable *ir);
 370    int setup_uniforms(int payload_reg);
 371    bool reg_allocate_trivial();
 372    bool reg_allocate();
 373    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 374    int choose_spill_reg(struct ra_graph *g);
 375    void spill_reg(int spill_reg);
 376    void move_grf_array_access_to_scratch();
 377    void move_uniform_array_access_to_pull_constants();
 378    void move_push_constants_to_pull_constants();
 379    void split_uniform_registers();
 380    void pack_uniform_registers();
 381    void calculate_live_intervals();
 382    void split_virtual_grfs();
 383    bool dead_code_eliminate();
 384    bool virtual_grf_interferes(int a, int b);
 385    bool opt_copy_propagation();
 386    bool opt_algebraic();
 387    bool opt_register_coalesce();
 388    void opt_set_dependency_control();
 389    void opt_schedule_instructions();
 390
 391    bool can_do_source_mods(vec4_instruction *inst);
 392
 393    vec4_instruction *emit(vec4_instruction *inst);
 394
 395    vec4_instruction *emit(enum opcode opcode);
 396
 397    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 398
 399    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 400                           src_reg src0, src_reg src1);
 401
 402    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 403                           src_reg src0, src_reg src1, src_reg src2);
 404
 405    vec4_instruction *emit_before(vec4_instruction *inst,
 406                                  vec4_instruction *new_inst);
 407
 408    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 409    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 410    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 411    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 412    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 413    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 414    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 415    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 416    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 417    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 418    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 419    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 420    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 421    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 422    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 423    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 424    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 425    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 426    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 427    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 428    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 429    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 430                          uint32_t condition);
 431    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 432    vec4_instruction *IF(uint32_t predicate);
 433    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 434    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 435    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 436    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 437    vec4_instruction *BFREV(dst_reg dst, src_reg value);
 438    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
 439    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
 440    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
 441    vec4_instruction *FBH(dst_reg dst, src_reg value);
 442    vec4_instruction *FBL(dst_reg dst, src_reg value);
 443    vec4_instruction *CBIT(dst_reg dst, src_reg value);
 444    vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
 445
 446    int implied_mrf_writes(vec4_instruction *inst);
 447
 448    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 449                                dst_reg dst,
 450                                src_reg src,
 451                                vec4_instruction *pre_rhs_inst,
 452                                vec4_instruction *last_rhs_inst);
 453
 454    bool try_copy_propagation(vec4_instruction *inst, int arg,
 455                              src_reg *values[4]);
 456
 457    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 458    void visit_instructions(const exec_list *list);
 459
 460    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 461                     src_reg src0, src_reg src1, src_reg one);
 462
 463    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 464    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 465    void emit_if_gen6(ir_if *ir);
 466
 467    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 468
 469    void emit_block_move(dst_reg *dst, src_reg *src,
 470                         const struct glsl_type *type, uint32_t predicate);
 471
 472    void emit_constant_values(dst_reg *dst, ir_constant *value);
 473
 474    /**
 475     * Emit the correct dot-product instruction for the type of arguments
 476     */
 477    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 478
 479    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 480                     dst_reg dst, src_reg src0);
 481
 482    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 483                     dst_reg dst, src_reg src0, src_reg src1);
 484
 485    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 486                  dst_reg dst, const src_reg &src);
 487
 488    src_reg fix_3src_operand(src_reg src);
 489
 490    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 491    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 492    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 493    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 494    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 495    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 496    src_reg fix_math_operand(src_reg src);
 497
 498    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 499    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 500
 501    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 502
 503    void emit_ndc_computation();
 504    void emit_psiz_and_flags(struct brw_reg reg);
 505    void emit_clip_distances(dst_reg reg, int offset);
 506    void emit_generic_urb_slot(dst_reg reg, int varying);
 507    void emit_urb_slot(int mrf, int varying);
 508
 509    void emit_shader_time_begin();
 510    void emit_shader_time_end();
 511    void emit_shader_time_write(enum shader_time_shader_type type,
 512                                src_reg value);
 513
 514    src_reg get_scratch_offset(vec4_instruction *inst,
 515                               src_reg *reladdr, int reg_offset);
 516    src_reg get_pull_constant_offset(vec4_instruction *inst,
 517                                     src_reg *reladdr, int reg_offset);
 518    void emit_scratch_read(vec4_instruction *inst,
 519                           dst_reg dst,
 520                           src_reg orig_src,
 521                           int base_offset);
 522    void emit_scratch_write(vec4_instruction *inst,
 523                            int base_offset);
 524    void emit_pull_constant_load(vec4_instruction *inst,
 525                                 dst_reg dst,
 526                                 src_reg orig_src,
 527                                 int base_offset);
 528
 529    bool try_emit_sat(ir_expression *ir);
 530    bool try_emit_mad(ir_expression *ir, int mul_arg);
 531    void resolve_ud_negate(src_reg *reg);
 532
 533    src_reg get_timestamp();
 534
 535    bool process_move_condition(ir_rvalue *ir);
 536
 537    void dump_instruction(backend_instruction *inst);
 538
 539 protected:
 540    void emit_vertex();
 541    void lower_attributes_to_hw_regs(const int *attribute_map);
 542    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 543                                    int reg_node_count);
 544    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 545    virtual void setup_payload() = 0;
 546    virtual void emit_prolog() = 0;
 547    virtual void emit_program_code() = 0;
 548    virtual void emit_thread_end() = 0;
 549    virtual void emit_urb_write_header(int mrf) = 0;
 550    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 551    virtual int compute_array_stride(ir_dereference_array *ir);
 552
 553    const bool debug_flag;
 554 };
 555
 556
 557 /**
 558  * The vertex shader code generator.
 559  *
 560  * Translates VS IR to actual i965 assembly code.
 561  */
 562 class vec4_generator
 563 {
 564 public:
 565    vec4_generator(struct brw_context *brw,
 566                   struct gl_shader_program *shader_prog,
 567                   struct gl_program *prog,
 568                   struct brw_vec4_prog_data *prog_data,
 569                   void *mem_ctx,
 570                   bool debug_flag);
 571    ~vec4_generator();
 572
 573    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 574
 575 private:
 576    void generate_code(exec_list *instructions);
 577    void generate_vec4_instruction(vec4_instruction *inst,
 578                                   struct brw_reg dst,
 579                                   struct brw_reg *src);
 580
 581    void generate_math1_gen4(vec4_instruction *inst,
 582                             struct brw_reg dst,
 583                             struct brw_reg src);
 584    void generate_math1_gen6(vec4_instruction *inst,
 585                             struct brw_reg dst,
 586                             struct brw_reg src);
 587    void generate_math2_gen4(vec4_instruction *inst,
 588                             struct brw_reg dst,
 589                             struct brw_reg src0,
 590                             struct brw_reg src1);
 591    void generate_math2_gen6(vec4_instruction *inst,
 592                             struct brw_reg dst,
 593                             struct brw_reg src0,
 594                             struct brw_reg src1);
 595    void generate_math2_gen7(vec4_instruction *inst,
 596                             struct brw_reg dst,
 597                             struct brw_reg src0,
 598                             struct brw_reg src1);
 599
 600    void generate_tex(vec4_instruction *inst,
 601                      struct brw_reg dst,
 602                      struct brw_reg src);
 603
 604    void generate_vs_urb_write(vec4_instruction *inst);
 605    void generate_gs_urb_write(vec4_instruction *inst);
 606    void generate_gs_thread_end(vec4_instruction *inst);
 607    void generate_gs_set_write_offset(struct brw_reg dst,
 608                                      struct brw_reg src0,
 609                                      struct brw_reg src1);
 610    void generate_gs_set_vertex_count(struct brw_reg dst,
 611                                      struct brw_reg src);
 612    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 613    void generate_oword_dual_block_offsets(struct brw_reg m1,
 614                                           struct brw_reg index);
 615    void generate_scratch_write(vec4_instruction *inst,
 616                                struct brw_reg dst,
 617                                struct brw_reg src,
 618                                struct brw_reg index);
 619    void generate_scratch_read(vec4_instruction *inst,
 620                               struct brw_reg dst,
 621                               struct brw_reg index);
 622    void generate_pull_constant_load(vec4_instruction *inst,
 623                                     struct brw_reg dst,
 624                                     struct brw_reg index,
 625                                     struct brw_reg offset);
 626    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 627                                          struct brw_reg dst,
 628                                          struct brw_reg surf_index,
 629                                          struct brw_reg offset);
 630    void generate_unpack_flags(vec4_instruction *inst,
 631                               struct brw_reg dst);
 632
 633    void mark_surface_used(unsigned surf_index);
 634
 635    struct brw_context *brw;
 636
 637    struct brw_compile *p;
 638
 639    struct gl_shader_program *shader_prog;
 640    struct gl_shader *shader;
 641    const struct gl_program *prog;
 642
 643    struct brw_vec4_prog_data *prog_data;
 644
 645    void *mem_ctx;
 646    const bool debug_flag;
 647 };
 648
 649 } /* namespace brw */
 650 #endif /* __cplusplus */
 651
 652 #endif /* BRW_VEC4_H */