src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31
  32 extern "C" {
  33 #include "brw_vs.h"
  34 #include "brw_context.h"
  35 #include "brw_eu.h"
  36 };
  37
  38 #include "glsl/ir.h"
  39
  40 namespace brw {
  41
  42 class dst_reg;
  43
  44 unsigned
  45 swizzle_for_size(int size);
  46
  47 enum register_file {
  48    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
  49    GRF = BRW_GENERAL_REGISTER_FILE,
  50    MRF = BRW_MESSAGE_REGISTER_FILE,
  51    IMM = BRW_IMMEDIATE_VALUE,
  52    HW_REG, /* a struct brw_reg */
  53    ATTR,
  54    UNIFORM, /* prog_data->params[hw_reg] */
  55    BAD_FILE
  56 };
  57
  58 class reg
  59 {
  60 public:
  61    /** Register file: ARF, GRF, MRF, IMM. */
  62    enum register_file file;
  63    /** virtual register number.  0 = fixed hw reg */
  64    int reg;
  65    /** Offset within the virtual register. */
  66    int reg_offset;
  67    /** Register type.  BRW_REGISTER_TYPE_* */
  68    int type;
  69    struct brw_reg fixed_hw_reg;
  70
  71    /** Value for file == BRW_IMMMEDIATE_FILE */
  72    union {
  73       int32_t i;
  74       uint32_t u;
  75       float f;
  76    } imm;
  77 };
  78
  79 class src_reg : public reg
  80 {
  81 public:
  82    /* Callers of this ralloc-based new need not call delete. It's
  83     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
  84    static void* operator new(size_t size, void *ctx)
  85    {
  86       void *node;
  87
  88       node = ralloc_size(ctx, size);
  89       assert(node != NULL);
  90
  91       return node;
  92    }
  93
  94    void init();
  95
  96    src_reg(register_file file, int reg, const glsl_type *type);
  97    src_reg();
  98    src_reg(float f);
  99    src_reg(uint32_t u);
 100    src_reg(int32_t i);
 101
 102    bool equals(src_reg *r);
 103    bool is_zero() const;
 104    bool is_one() const;
 105
 106    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 107
 108    explicit src_reg(dst_reg reg);
 109
 110    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 111    bool negate;
 112    bool abs;
 113
 114    src_reg *reladdr;
 115 };
 116
 117 class dst_reg : public reg
 118 {
 119 public:
 120    /* Callers of this ralloc-based new need not call delete. It's
 121     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 122    static void* operator new(size_t size, void *ctx)
 123    {
 124       void *node;
 125
 126       node = ralloc_size(ctx, size);
 127       assert(node != NULL);
 128
 129       return node;
 130    }
 131
 132    void init();
 133
 134    dst_reg();
 135    dst_reg(register_file file, int reg);
 136    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 137    dst_reg(struct brw_reg reg);
 138    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 139
 140    explicit dst_reg(src_reg reg);
 141
 142    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 143
 144    src_reg *reladdr;
 145 };
 146
 147 class vec4_instruction : public backend_instruction {
 148 public:
 149    /* Callers of this ralloc-based new need not call delete. It's
 150     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 151    static void* operator new(size_t size, void *ctx)
 152    {
 153       void *node;
 154
 155       node = rzalloc_size(ctx, size);
 156       assert(node != NULL);
 157
 158       return node;
 159    }
 160
 161    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 162                     dst_reg dst = dst_reg(),
 163                     src_reg src0 = src_reg(),
 164                     src_reg src1 = src_reg(),
 165                     src_reg src2 = src_reg());
 166
 167    struct brw_reg get_dst(void);
 168    struct brw_reg get_src(int i);
 169
 170    dst_reg dst;
 171    src_reg src[3];
 172
 173    bool saturate;
 174    bool force_writemask_all;
 175    bool no_dd_clear, no_dd_check;
 176
 177    int conditional_mod; /**< BRW_CONDITIONAL_* */
 178
 179    int sampler;
 180    uint32_t texture_offset; /**< Texture Offset bitfield */
 181    int target; /**< MRT target. */
 182    bool shadow_compare;
 183
 184    bool eot;
 185    bool header_present;
 186    int mlen; /**< SEND message length */
 187    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 188
 189    uint32_t offset; /* spill/unspill offset */
 190    /** @{
 191     * Annotation for the generated IR.  One of the two can be set.
 192     */
 193    const void *ir;
 194    const char *annotation;
 195
 196    bool is_send_from_grf();
 197    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 198    void reswizzle_dst(int dst_writemask, int swizzle);
 199 };
 200
 201 /**
 202  * The vertex shader front-end.
 203  *
 204  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 205  * fixed-function) into VS IR.
 206  */
 207 class vec4_visitor : public backend_visitor
 208 {
 209 public:
 210    vec4_visitor(struct brw_context *brw,
 211                 struct brw_vec4_compile *c,
 212                 struct gl_program *prog,
 213                 const struct brw_vec4_prog_key *key,
 214                 struct brw_vec4_prog_data *prog_data,
 215                 struct gl_shader_program *shader_prog,
 216                 struct brw_shader *shader,
 217                 void *mem_ctx,
 218                 bool debug_flag);
 219    ~vec4_visitor();
 220
 221    dst_reg dst_null_f()
 222    {
 223       return dst_reg(brw_null_reg());
 224    }
 225
 226    dst_reg dst_null_d()
 227    {
 228       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 229    }
 230
 231    struct gl_program *prog;
 232    struct brw_vec4_compile *c;
 233    const struct brw_vec4_prog_key *key;
 234    struct brw_vec4_prog_data *prog_data;
 235    unsigned int sanity_param_count;
 236
 237    char *fail_msg;
 238    bool failed;
 239
 240    /**
 241     * GLSL IR currently being processed, which is associated with our
 242     * driver IR instructions for debugging purposes.
 243     */
 244    const void *base_ir;
 245    const char *current_annotation;
 246
 247    int *virtual_grf_sizes;
 248    int virtual_grf_count;
 249    int virtual_grf_array_size;
 250    int first_non_payload_grf;
 251    unsigned int max_grf;
 252    int *virtual_grf_def;
 253    int *virtual_grf_use;
 254    dst_reg userplane[MAX_CLIP_PLANES];
 255
 256    /**
 257     * This is the size to be used for an array with an element per
 258     * reg_offset
 259     */
 260    int virtual_grf_reg_count;
 261    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 262    int *virtual_grf_reg_map;
 263
 264    bool live_intervals_valid;
 265
 266    dst_reg *variable_storage(ir_variable *var);
 267
 268    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 269
 270    bool need_all_constants_in_pull_buffer;
 271
 272    /**
 273     * \name Visit methods
 274     *
 275     * As typical for the visitor pattern, there must be one \c visit method for
 276     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 277     * the hierarchy should not have \c visit methods.
 278     */
 279    /*@{*/
 280    virtual void visit(ir_variable *);
 281    virtual void visit(ir_loop *);
 282    virtual void visit(ir_loop_jump *);
 283    virtual void visit(ir_function_signature *);
 284    virtual void visit(ir_function *);
 285    virtual void visit(ir_expression *);
 286    virtual void visit(ir_swizzle *);
 287    virtual void visit(ir_dereference_variable  *);
 288    virtual void visit(ir_dereference_array *);
 289    virtual void visit(ir_dereference_record *);
 290    virtual void visit(ir_assignment *);
 291    virtual void visit(ir_constant *);
 292    virtual void visit(ir_call *);
 293    virtual void visit(ir_return *);
 294    virtual void visit(ir_discard *);
 295    virtual void visit(ir_texture *);
 296    virtual void visit(ir_if *);
 297    /*@}*/
 298
 299    src_reg result;
 300
 301    /* Regs for vertex results.  Generated at ir_variable visiting time
 302     * for the ir->location's used.
 303     */
 304    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 305    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 306    int uniform_size[MAX_UNIFORMS];
 307    int uniform_vector_size[MAX_UNIFORMS];
 308    int uniforms;
 309
 310    src_reg shader_start_time;
 311
 312    struct hash_table *variable_ht;
 313
 314    bool run(void);
 315    void fail(const char *msg, ...);
 316
 317    int virtual_grf_alloc(int size);
 318    void setup_uniform_clipplane_values();
 319    void setup_uniform_values(ir_variable *ir);
 320    void setup_builtin_uniform_values(ir_variable *ir);
 321    int setup_uniforms(int payload_reg);
 322    void setup_payload();
 323    bool reg_allocate_trivial();
 324    bool reg_allocate();
 325    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 326    int choose_spill_reg(struct ra_graph *g);
 327    void spill_reg(int spill_reg);
 328    void move_grf_array_access_to_scratch();
 329    void move_uniform_array_access_to_pull_constants();
 330    void move_push_constants_to_pull_constants();
 331    void split_uniform_registers();
 332    void pack_uniform_registers();
 333    void calculate_live_intervals();
 334    void split_virtual_grfs();
 335    bool dead_code_eliminate();
 336    bool virtual_grf_interferes(int a, int b);
 337    bool opt_copy_propagation();
 338    bool opt_algebraic();
 339    bool opt_register_coalesce();
 340    void opt_set_dependency_control();
 341
 342    bool can_do_source_mods(vec4_instruction *inst);
 343
 344    vec4_instruction *emit(vec4_instruction *inst);
 345
 346    vec4_instruction *emit(enum opcode opcode);
 347
 348    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 349
 350    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 351                           src_reg src0, src_reg src1);
 352
 353    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 354                           src_reg src0, src_reg src1, src_reg src2);
 355
 356    vec4_instruction *emit_before(vec4_instruction *inst,
 357                                  vec4_instruction *new_inst);
 358
 359    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 360    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 361    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 362    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 363    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 364    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 365    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 366    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 367    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 368    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 369    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 370    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 371    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 372    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 373    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 374    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 375    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 376    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 377    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 378    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 379    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 380    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 381                          uint32_t condition);
 382    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 383    vec4_instruction *IF(uint32_t predicate);
 384    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 385    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 386    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 387    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 388
 389    int implied_mrf_writes(vec4_instruction *inst);
 390
 391    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 392                                dst_reg dst,
 393                                src_reg src,
 394                                vec4_instruction *pre_rhs_inst,
 395                                vec4_instruction *last_rhs_inst);
 396
 397    bool try_copy_propagation(struct intel_context *intel,
 398                              vec4_instruction *inst, int arg,
 399                              src_reg *values[4]);
 400
 401    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 402    void visit_instructions(const exec_list *list);
 403
 404    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 405                     src_reg src0, src_reg src1, src_reg one);
 406
 407    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 408    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 409    void emit_if_gen6(ir_if *ir);
 410
 411    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 412
 413    void emit_block_move(dst_reg *dst, src_reg *src,
 414                         const struct glsl_type *type, uint32_t predicate);
 415
 416    void emit_constant_values(dst_reg *dst, ir_constant *value);
 417
 418    /**
 419     * Emit the correct dot-product instruction for the type of arguments
 420     */
 421    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 422
 423    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 424                     dst_reg dst, src_reg src0);
 425
 426    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 427                     dst_reg dst, src_reg src0, src_reg src1);
 428
 429    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 430                  dst_reg dst, const src_reg &src);
 431
 432    src_reg fix_3src_operand(src_reg src);
 433
 434    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 435    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 436    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 437    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 438    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 439    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 440    src_reg fix_math_operand(src_reg src);
 441
 442    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 443    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 444
 445    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 446
 447    void emit_ndc_computation();
 448    void emit_psiz_and_flags(struct brw_reg reg);
 449    void emit_clip_distances(struct brw_reg reg, int offset);
 450    void emit_generic_urb_slot(dst_reg reg, int varying);
 451    void emit_urb_slot(int mrf, int varying);
 452
 453    void emit_shader_time_begin();
 454    void emit_shader_time_end();
 455    void emit_shader_time_write(enum shader_time_shader_type type,
 456                                src_reg value);
 457
 458    src_reg get_scratch_offset(vec4_instruction *inst,
 459                               src_reg *reladdr, int reg_offset);
 460    src_reg get_pull_constant_offset(vec4_instruction *inst,
 461                                     src_reg *reladdr, int reg_offset);
 462    void emit_scratch_read(vec4_instruction *inst,
 463                           dst_reg dst,
 464                           src_reg orig_src,
 465                           int base_offset);
 466    void emit_scratch_write(vec4_instruction *inst,
 467                            int base_offset);
 468    void emit_pull_constant_load(vec4_instruction *inst,
 469                                 dst_reg dst,
 470                                 src_reg orig_src,
 471                                 int base_offset);
 472
 473    bool try_emit_sat(ir_expression *ir);
 474    void resolve_ud_negate(src_reg *reg);
 475
 476    src_reg get_timestamp();
 477
 478    bool process_move_condition(ir_rvalue *ir);
 479
 480    void dump_instruction(backend_instruction *inst);
 481
 482 protected:
 483    void emit_vertex();
 484    void lower_attributes_to_hw_regs(const int *attribute_map);
 485    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 486    virtual int setup_attributes(int payload_reg) = 0;
 487    virtual void emit_prolog() = 0;
 488    virtual void emit_program_code() = 0;
 489    virtual void emit_thread_end() = 0;
 490    virtual void emit_urb_write_header(int mrf) = 0;
 491    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 492    virtual int compute_array_stride(ir_dereference_array *ir);
 493
 494    const bool debug_flag;
 495 };
 496
 497 class vec4_vs_visitor : public vec4_visitor
 498 {
 499 public:
 500    vec4_vs_visitor(struct brw_context *brw,
 501                    struct brw_vs_compile *vs_compile,
 502                    struct brw_vs_prog_data *vs_prog_data,
 503                    struct gl_shader_program *prog,
 504                    struct brw_shader *shader,
 505                    void *mem_ctx);
 506
 507 protected:
 508    virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
 509    virtual int setup_attributes(int payload_reg);
 510    virtual void emit_prolog();
 511    virtual void emit_program_code();
 512    virtual void emit_thread_end();
 513    virtual void emit_urb_write_header(int mrf);
 514    virtual vec4_instruction *emit_urb_write_opcode(bool complete);
 515
 516 private:
 517    void setup_vp_regs();
 518    dst_reg get_vp_dst_reg(const prog_dst_register &dst);
 519    src_reg get_vp_src_reg(const prog_src_register &src);
 520
 521    struct brw_vs_compile * const vs_compile;
 522    struct brw_vs_prog_data * const vs_prog_data;
 523    src_reg *vp_temp_regs;
 524    src_reg vp_addr_reg;
 525 };
 526
 527 /**
 528  * The vertex shader code generator.
 529  *
 530  * Translates VS IR to actual i965 assembly code.
 531  */
 532 class vec4_generator
 533 {
 534 public:
 535    vec4_generator(struct brw_context *brw,
 536                   struct gl_shader_program *shader_prog,
 537                   struct gl_program *prog,
 538                   void *mem_ctx,
 539                   bool debug_flag);
 540    ~vec4_generator();
 541
 542    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 543
 544 private:
 545    void generate_code(exec_list *instructions);
 546    void generate_vec4_instruction(vec4_instruction *inst,
 547                                   struct brw_reg dst,
 548                                   struct brw_reg *src);
 549
 550    void generate_math1_gen4(vec4_instruction *inst,
 551                             struct brw_reg dst,
 552                             struct brw_reg src);
 553    void generate_math1_gen6(vec4_instruction *inst,
 554                             struct brw_reg dst,
 555                             struct brw_reg src);
 556    void generate_math2_gen4(vec4_instruction *inst,
 557                             struct brw_reg dst,
 558                             struct brw_reg src0,
 559                             struct brw_reg src1);
 560    void generate_math2_gen6(vec4_instruction *inst,
 561                             struct brw_reg dst,
 562                             struct brw_reg src0,
 563                             struct brw_reg src1);
 564    void generate_math2_gen7(vec4_instruction *inst,
 565                             struct brw_reg dst,
 566                             struct brw_reg src0,
 567                             struct brw_reg src1);
 568
 569    void generate_tex(vec4_instruction *inst,
 570                      struct brw_reg dst,
 571                      struct brw_reg src);
 572
 573    void generate_urb_write(vec4_instruction *inst);
 574    void generate_oword_dual_block_offsets(struct brw_reg m1,
 575                                           struct brw_reg index);
 576    void generate_scratch_write(vec4_instruction *inst,
 577                                struct brw_reg dst,
 578                                struct brw_reg src,
 579                                struct brw_reg index);
 580    void generate_scratch_read(vec4_instruction *inst,
 581                               struct brw_reg dst,
 582                               struct brw_reg index);
 583    void generate_pull_constant_load(vec4_instruction *inst,
 584                                     struct brw_reg dst,
 585                                     struct brw_reg index,
 586                                     struct brw_reg offset);
 587    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 588                                          struct brw_reg dst,
 589                                          struct brw_reg surf_index,
 590                                          struct brw_reg offset);
 591
 592    struct brw_context *brw;
 593    struct intel_context *intel;
 594    struct gl_context *ctx;
 595
 596    struct brw_compile *p;
 597
 598    struct gl_shader_program *shader_prog;
 599    struct gl_shader *shader;
 600    const struct gl_program *prog;
 601
 602    void *mem_ctx;
 603    const bool debug_flag;
 604 };
 605
 606 } /* namespace brw */
 607
 608 #endif /* BRW_VEC4_H */