src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include "brw_shader.h"
  28 #include "brw_program.h"
  29
  30 #ifdef __cplusplus
  31 #include "brw_ir_vec4.h"
  32 #endif
  33
  34 #include "compiler/glsl/ir.h"
  35 #include "compiler/nir/nir.h"
  36
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 const unsigned *
  43 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
  44                            void *log_data,
  45                            void *mem_ctx,
  46                            const nir_shader *nir,
  47                            struct brw_vue_prog_data *prog_data,
  48                            const struct cfg_t *cfg,
  49                            unsigned *out_assembly_size);
  50
  51 #ifdef __cplusplus
  52 } /* extern "C" */
  53
  54 namespace brw {
  55
  56 class vec4_live_variables;
  57
  58 /**
  59  * The vertex shader front-end.
  60  *
  61  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
  62  * fixed-function) into VS IR.
  63  */
  64 class vec4_visitor : public backend_shader
  65 {
  66 public:
  67    vec4_visitor(const struct brw_compiler *compiler,
  68                 void *log_data,
  69                 const struct brw_sampler_prog_key_data *key,
  70                 struct brw_vue_prog_data *prog_data,
  71                 const nir_shader *shader,
  72                 void *mem_ctx,
  73                 bool no_spills,
  74                 int shader_time_index);
  75    virtual ~vec4_visitor();
  76
  77    dst_reg dst_null_f()
  78    {
  79       return dst_reg(brw_null_reg());
  80    }
  81
  82    dst_reg dst_null_d()
  83    {
  84       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
  85    }
  86
  87    dst_reg dst_null_ud()
  88    {
  89       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
  90    }
  91
  92    const struct brw_sampler_prog_key_data * const key_tex;
  93    struct brw_vue_prog_data * const prog_data;
  94    char *fail_msg;
  95    bool failed;
  96
  97    /**
  98     * GLSL IR currently being processed, which is associated with our
  99     * driver IR instructions for debugging purposes.
 100     */
 101    const void *base_ir;
 102    const char *current_annotation;
 103
 104    int first_non_payload_grf;
 105    unsigned int max_grf;
 106    int *virtual_grf_start;
 107    int *virtual_grf_end;
 108    brw::vec4_live_variables *live_intervals;
 109    dst_reg userplane[MAX_CLIP_PLANES];
 110
 111    bool need_all_constants_in_pull_buffer;
 112
 113    /* Regs for vertex results.  Generated at ir_variable visiting time
 114     * for the ir->location's used.
 115     */
 116    dst_reg output_reg[VARYING_SLOT_TESS_MAX][4];
 117    unsigned output_num_components[VARYING_SLOT_TESS_MAX][4];
 118    const char *output_reg_annotation[VARYING_SLOT_TESS_MAX];
 119    int uniforms;
 120
 121    src_reg shader_start_time;
 122
 123    bool run();
 124    void fail(const char *msg, ...);
 125
 126    int setup_uniforms(int payload_reg);
 127
 128    bool reg_allocate_trivial();
 129    bool reg_allocate();
 130    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 131    int choose_spill_reg(struct ra_graph *g);
 132    void spill_reg(int spill_reg);
 133    void move_grf_array_access_to_scratch();
 134    void move_uniform_array_access_to_pull_constants();
 135    void move_push_constants_to_pull_constants();
 136    void split_uniform_registers();
 137    void pack_uniform_registers();
 138    void calculate_live_intervals();
 139    void invalidate_live_intervals();
 140    void split_virtual_grfs();
 141    bool opt_vector_float();
 142    bool opt_reduce_swizzle();
 143    bool dead_code_eliminate();
 144    int var_range_start(unsigned v, unsigned n) const;
 145    int var_range_end(unsigned v, unsigned n) const;
 146    bool virtual_grf_interferes(int a, int b);
 147    bool opt_cmod_propagation();
 148    bool opt_copy_propagation(bool do_constant_prop = true);
 149    bool opt_cse_local(bblock_t *block);
 150    bool opt_cse();
 151    bool opt_algebraic();
 152    bool opt_register_coalesce();
 153    bool eliminate_find_live_channel();
 154    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 155    void opt_set_dependency_control();
 156    void opt_schedule_instructions();
 157    void convert_to_hw_regs();
 158
 159    vec4_instruction *emit(vec4_instruction *inst);
 160
 161    vec4_instruction *emit(enum opcode opcode);
 162    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 163    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 164                           const src_reg &src0);
 165    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 166                           const src_reg &src0, const src_reg &src1);
 167    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 168                           const src_reg &src0, const src_reg &src1,
 169                           const src_reg &src2);
 170
 171    vec4_instruction *emit_before(bblock_t *block,
 172                                  vec4_instruction *inst,
 173                                  vec4_instruction *new_inst);
 174
 175 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 176 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 177 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 178    EMIT1(MOV)
 179    EMIT1(NOT)
 180    EMIT1(RNDD)
 181    EMIT1(RNDE)
 182    EMIT1(RNDZ)
 183    EMIT1(FRC)
 184    EMIT1(F32TO16)
 185    EMIT1(F16TO32)
 186    EMIT2(ADD)
 187    EMIT2(MUL)
 188    EMIT2(MACH)
 189    EMIT2(MAC)
 190    EMIT2(AND)
 191    EMIT2(OR)
 192    EMIT2(XOR)
 193    EMIT2(DP3)
 194    EMIT2(DP4)
 195    EMIT2(DPH)
 196    EMIT2(SHL)
 197    EMIT2(SHR)
 198    EMIT2(ASR)
 199    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 200                          enum brw_conditional_mod condition);
 201    vec4_instruction *IF(src_reg src0, src_reg src1,
 202                         enum brw_conditional_mod condition);
 203    vec4_instruction *IF(enum brw_predicate predicate);
 204    EMIT1(SCRATCH_READ)
 205    EMIT2(SCRATCH_WRITE)
 206    EMIT3(LRP)
 207    EMIT1(BFREV)
 208    EMIT3(BFE)
 209    EMIT2(BFI1)
 210    EMIT3(BFI2)
 211    EMIT1(FBH)
 212    EMIT1(FBL)
 213    EMIT1(CBIT)
 214    EMIT3(MAD)
 215    EMIT2(ADDC)
 216    EMIT2(SUBB)
 217    EMIT1(DIM)
 218
 219 #undef EMIT1
 220 #undef EMIT2
 221 #undef EMIT3
 222
 223    int implied_mrf_writes(vec4_instruction *inst);
 224
 225    vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 226                                  src_reg src0, src_reg src1);
 227
 228    vec4_instruction *emit_lrp(const dst_reg &dst, const src_reg &x,
 229                               const src_reg &y, const src_reg &a);
 230
 231    /**
 232     * Copy any live channel from \p src to the first channel of the
 233     * result.
 234     */
 235    src_reg emit_uniformize(const src_reg &src);
 236
 237    src_reg fix_3src_operand(const src_reg &src);
 238    src_reg resolve_source_modifiers(const src_reg &src);
 239
 240    vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 241                                const src_reg &src1 = src_reg());
 242
 243    src_reg fix_math_operand(const src_reg &src);
 244
 245    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 246    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 247    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 248    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 249    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 250    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 251
 252    void emit_texture(ir_texture_opcode op,
 253                      dst_reg dest,
 254                      const glsl_type *dest_type,
 255                      src_reg coordinate,
 256                      int coord_components,
 257                      src_reg shadow_comparitor,
 258                      src_reg lod, src_reg lod2,
 259                      src_reg sample_index,
 260                      uint32_t constant_offset,
 261                      src_reg offset_value,
 262                      src_reg mcs,
 263                      uint32_t surface, src_reg surface_reg,
 264                      src_reg sampler_reg);
 265
 266    src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
 267                           src_reg surface);
 268    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 269
 270    void emit_ndc_computation();
 271    void emit_psiz_and_flags(dst_reg reg);
 272    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp);
 273    virtual void emit_urb_slot(dst_reg reg, int varying);
 274
 275    void emit_shader_time_begin();
 276    void emit_shader_time_end();
 277    void emit_shader_time_write(int shader_time_subindex, src_reg value);
 278
 279    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 280                               src_reg *reladdr, int reg_offset);
 281    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 282                           dst_reg dst,
 283                           src_reg orig_src,
 284                           int base_offset);
 285    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 286                            int base_offset);
 287    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 288                                 dst_reg dst,
 289                                 src_reg orig_src,
 290                                 int base_offset,
 291                                 src_reg indirect);
 292    void emit_pull_constant_load_reg(dst_reg dst,
 293                                     src_reg surf_index,
 294                                     src_reg offset,
 295                                     bblock_t *before_block,
 296                                     vec4_instruction *before_inst);
 297    src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
 298                                 vec4_instruction *inst, src_reg src);
 299
 300    void resolve_ud_negate(src_reg *reg);
 301
 302    bool lower_minmax();
 303
 304    src_reg get_timestamp();
 305
 306    void dump_instruction(backend_instruction *inst);
 307    void dump_instruction(backend_instruction *inst, FILE *file);
 308
 309    bool is_high_sampler(src_reg sampler);
 310
 311    bool optimize_predicate(nir_alu_instr *instr, enum brw_predicate *predicate);
 312
 313    virtual void emit_nir_code();
 314    virtual void nir_setup_uniforms();
 315    virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr);
 316    virtual void nir_setup_system_values();
 317    virtual void nir_emit_impl(nir_function_impl *impl);
 318    virtual void nir_emit_cf_list(exec_list *list);
 319    virtual void nir_emit_if(nir_if *if_stmt);
 320    virtual void nir_emit_loop(nir_loop *loop);
 321    virtual void nir_emit_block(nir_block *block);
 322    virtual void nir_emit_instr(nir_instr *instr);
 323    virtual void nir_emit_load_const(nir_load_const_instr *instr);
 324    virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
 325    virtual void nir_emit_alu(nir_alu_instr *instr);
 326    virtual void nir_emit_jump(nir_jump_instr *instr);
 327    virtual void nir_emit_texture(nir_tex_instr *instr);
 328    virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
 329    virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr);
 330
 331    dst_reg get_nir_dest(const nir_dest &dest, enum brw_reg_type type);
 332    dst_reg get_nir_dest(const nir_dest &dest, nir_alu_type type);
 333    dst_reg get_nir_dest(const nir_dest &dest);
 334    src_reg get_nir_src(const nir_src &src, enum brw_reg_type type,
 335                        unsigned num_components = 4);
 336    src_reg get_nir_src(const nir_src &src, nir_alu_type type,
 337                        unsigned num_components = 4);
 338    src_reg get_nir_src(const nir_src &src,
 339                        unsigned num_components = 4);
 340    src_reg get_indirect_offset(nir_intrinsic_instr *instr);
 341
 342    virtual dst_reg *make_reg_for_system_value(int location) = 0;
 343
 344    dst_reg *nir_locals;
 345    dst_reg *nir_ssa_values;
 346    dst_reg *nir_system_values;
 347
 348 protected:
 349    void emit_vertex();
 350    void lower_attributes_to_hw_regs(const int *attribute_map,
 351                                     bool interleaved);
 352    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 353                                    int reg_node_count);
 354    virtual void setup_payload() = 0;
 355    virtual void emit_prolog() = 0;
 356    virtual void emit_thread_end() = 0;
 357    virtual void emit_urb_write_header(int mrf) = 0;
 358    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 359    virtual void gs_emit_vertex(int stream_id);
 360    virtual void gs_end_primitive();
 361
 362 private:
 363    /**
 364     * If true, then register allocation should fail instead of spilling.
 365     */
 366    const bool no_spills;
 367
 368    int shader_time_index;
 369
 370    unsigned last_scratch; /**< measured in 32-byte (register size) units */
 371 };
 372
 373 } /* namespace brw */
 374 #endif /* __cplusplus */
 375
 376 #endif /* BRW_VEC4_H */