src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 #include "brw_ir_vec4.h"
  35
  36 extern "C" {
  37 #endif
  38
  39 #include "brw_context.h"
  40 #include "brw_eu.h"
  41 #include "intel_asm_annotation.h"
  42
  43 #ifdef __cplusplus
  44 }; /* extern "C" */
  45 #endif
  46
  47 #include "glsl/ir.h"
  48
  49
  50 struct brw_vec4_compile {
  51    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  52 };
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 void
  59 brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx,
  60                                       struct brw_vue_prog_key *key,
  61                                       GLuint id, struct gl_program *prog);
  62
  63 #ifdef __cplusplus
  64 } /* extern "C" */
  65
  66 namespace brw {
  67
  68 class vec4_live_variables;
  69
  70 /**
  71  * The vertex shader front-end.
  72  *
  73  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
  74  * fixed-function) into VS IR.
  75  */
  76 class vec4_visitor : public backend_visitor
  77 {
  78 public:
  79    vec4_visitor(struct brw_context *brw,
  80                 struct brw_vec4_compile *c,
  81                 struct gl_program *prog,
  82                 const struct brw_vue_prog_key *key,
  83                 struct brw_vue_prog_data *prog_data,
  84                 struct gl_shader_program *shader_prog,
  85                 gl_shader_stage stage,
  86                 void *mem_ctx,
  87                 bool debug_flag,
  88                 bool no_spills,
  89                 shader_time_shader_type st_base,
  90                 shader_time_shader_type st_written,
  91                 shader_time_shader_type st_reset);
  92    ~vec4_visitor();
  93
  94    dst_reg dst_null_f()
  95    {
  96       return dst_reg(brw_null_reg());
  97    }
  98
  99    dst_reg dst_null_d()
 100    {
 101       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 102    }
 103
 104    dst_reg dst_null_ud()
 105    {
 106       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 107    }
 108
 109    struct brw_vec4_compile * const c;
 110    const struct brw_vue_prog_key * const key;
 111    struct brw_vue_prog_data * const prog_data;
 112    unsigned int sanity_param_count;
 113
 114    char *fail_msg;
 115    bool failed;
 116
 117    /**
 118     * GLSL IR currently being processed, which is associated with our
 119     * driver IR instructions for debugging purposes.
 120     */
 121    const void *base_ir;
 122    const char *current_annotation;
 123
 124    int first_non_payload_grf;
 125    unsigned int max_grf;
 126    int *virtual_grf_start;
 127    int *virtual_grf_end;
 128    brw::vec4_live_variables *live_intervals;
 129    dst_reg userplane[MAX_CLIP_PLANES];
 130
 131    dst_reg *variable_storage(ir_variable *var);
 132
 133    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 134
 135    bool need_all_constants_in_pull_buffer;
 136
 137    /**
 138     * \name Visit methods
 139     *
 140     * As typical for the visitor pattern, there must be one \c visit method for
 141     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 142     * the hierarchy should not have \c visit methods.
 143     */
 144    /*@{*/
 145    virtual void visit(ir_variable *);
 146    virtual void visit(ir_loop *);
 147    virtual void visit(ir_loop_jump *);
 148    virtual void visit(ir_function_signature *);
 149    virtual void visit(ir_function *);
 150    virtual void visit(ir_expression *);
 151    virtual void visit(ir_swizzle *);
 152    virtual void visit(ir_dereference_variable  *);
 153    virtual void visit(ir_dereference_array *);
 154    virtual void visit(ir_dereference_record *);
 155    virtual void visit(ir_assignment *);
 156    virtual void visit(ir_constant *);
 157    virtual void visit(ir_call *);
 158    virtual void visit(ir_return *);
 159    virtual void visit(ir_discard *);
 160    virtual void visit(ir_texture *);
 161    virtual void visit(ir_if *);
 162    virtual void visit(ir_emit_vertex *);
 163    virtual void visit(ir_end_primitive *);
 164    /*@}*/
 165
 166    src_reg result;
 167
 168    /* Regs for vertex results.  Generated at ir_variable visiting time
 169     * for the ir->location's used.
 170     */
 171    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 172    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 173    int *uniform_size;
 174    int *uniform_vector_size;
 175    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 176    int uniforms;
 177
 178    src_reg shader_start_time;
 179
 180    struct hash_table *variable_ht;
 181
 182    bool run(void);
 183    void fail(const char *msg, ...);
 184
 185    void setup_uniform_clipplane_values();
 186    void setup_uniform_values(ir_variable *ir);
 187    void setup_builtin_uniform_values(ir_variable *ir);
 188    int setup_uniforms(int payload_reg);
 189    bool reg_allocate_trivial();
 190    bool reg_allocate();
 191    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 192    int choose_spill_reg(struct ra_graph *g);
 193    void spill_reg(int spill_reg);
 194    void move_grf_array_access_to_scratch();
 195    void move_uniform_array_access_to_pull_constants();
 196    void move_push_constants_to_pull_constants();
 197    void split_uniform_registers();
 198    void pack_uniform_registers();
 199    void calculate_live_intervals();
 200    void invalidate_live_intervals();
 201    void split_virtual_grfs();
 202    bool opt_vector_float();
 203    bool opt_reduce_swizzle();
 204    bool dead_code_eliminate();
 205    bool virtual_grf_interferes(int a, int b);
 206    bool opt_copy_propagation(bool do_constant_prop = true);
 207    bool opt_cse_local(bblock_t *block);
 208    bool opt_cse();
 209    bool opt_algebraic();
 210    bool opt_register_coalesce();
 211    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 212    void opt_set_dependency_control();
 213    void opt_schedule_instructions();
 214
 215    vec4_instruction *emit(vec4_instruction *inst);
 216
 217    vec4_instruction *emit(enum opcode opcode);
 218    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 219    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 220                           const src_reg &src0);
 221    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 222                           const src_reg &src0, const src_reg &src1);
 223    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 224                           const src_reg &src0, const src_reg &src1,
 225                           const src_reg &src2);
 226
 227    vec4_instruction *emit_before(bblock_t *block,
 228                                  vec4_instruction *inst,
 229                                  vec4_instruction *new_inst);
 230
 231 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 232 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 233 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 234    EMIT1(MOV)
 235    EMIT1(NOT)
 236    EMIT1(RNDD)
 237    EMIT1(RNDE)
 238    EMIT1(RNDZ)
 239    EMIT1(FRC)
 240    EMIT1(F32TO16)
 241    EMIT1(F16TO32)
 242    EMIT2(ADD)
 243    EMIT2(MUL)
 244    EMIT2(MACH)
 245    EMIT2(MAC)
 246    EMIT2(AND)
 247    EMIT2(OR)
 248    EMIT2(XOR)
 249    EMIT2(DP3)
 250    EMIT2(DP4)
 251    EMIT2(DPH)
 252    EMIT2(SHL)
 253    EMIT2(SHR)
 254    EMIT2(ASR)
 255    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 256                          enum brw_conditional_mod condition);
 257    vec4_instruction *IF(src_reg src0, src_reg src1,
 258                         enum brw_conditional_mod condition);
 259    vec4_instruction *IF(enum brw_predicate predicate);
 260    EMIT1(PULL_CONSTANT_LOAD)
 261    EMIT1(SCRATCH_READ)
 262    EMIT2(SCRATCH_WRITE)
 263    EMIT3(LRP)
 264    EMIT1(BFREV)
 265    EMIT3(BFE)
 266    EMIT2(BFI1)
 267    EMIT3(BFI2)
 268    EMIT1(FBH)
 269    EMIT1(FBL)
 270    EMIT1(CBIT)
 271    EMIT3(MAD)
 272    EMIT2(ADDC)
 273    EMIT2(SUBB)
 274 #undef EMIT1
 275 #undef EMIT2
 276 #undef EMIT3
 277
 278    int implied_mrf_writes(vec4_instruction *inst);
 279
 280    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 281                                dst_reg dst,
 282                                src_reg src,
 283                                vec4_instruction *pre_rhs_inst,
 284                                vec4_instruction *last_rhs_inst);
 285
 286    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 287    void visit_instructions(const exec_list *list);
 288
 289    void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 290                     src_reg src0, src_reg src1, src_reg one);
 291
 292    void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
 293    void emit_if_gen6(ir_if *ir);
 294
 295    void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 296                     src_reg src0, src_reg src1);
 297
 298    void emit_lrp(const dst_reg &dst,
 299                  const src_reg &x, const src_reg &y, const src_reg &a);
 300
 301    void emit_block_move(dst_reg *dst, src_reg *src,
 302                         const struct glsl_type *type, brw_predicate predicate);
 303
 304    void emit_constant_values(dst_reg *dst, ir_constant *value);
 305
 306    /**
 307     * Emit the correct dot-product instruction for the type of arguments
 308     */
 309    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 310
 311    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 312                     dst_reg dst, src_reg src0);
 313
 314    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 315                     dst_reg dst, src_reg src0, src_reg src1);
 316
 317    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 318                  dst_reg dst, const src_reg &src);
 319
 320    src_reg fix_3src_operand(src_reg src);
 321
 322    void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 323                   const src_reg &src1 = src_reg());
 324    src_reg fix_math_operand(src_reg src);
 325
 326    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 327    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 328    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 329    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 330    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 331    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 332
 333    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 334    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
 335    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 336    void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 337
 338    void emit_ndc_computation();
 339    void emit_psiz_and_flags(dst_reg reg);
 340    void emit_clip_distances(dst_reg reg, int offset);
 341    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
 342    void emit_urb_slot(dst_reg reg, int varying);
 343
 344    void emit_shader_time_begin();
 345    void emit_shader_time_end();
 346    void emit_shader_time_write(enum shader_time_shader_type type,
 347                                src_reg value);
 348
 349    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 350                             dst_reg dst, src_reg offset, src_reg src0,
 351                             src_reg src1);
 352
 353    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 354                                   src_reg offset);
 355
 356    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 357                               src_reg *reladdr, int reg_offset);
 358    src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
 359                                     src_reg *reladdr, int reg_offset);
 360    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 361                           dst_reg dst,
 362                           src_reg orig_src,
 363                           int base_offset);
 364    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 365                            int base_offset);
 366    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 367                                 dst_reg dst,
 368                                 src_reg orig_src,
 369                                 int base_offset);
 370
 371    bool try_emit_mad(ir_expression *ir);
 372    bool try_emit_b2f_of_compare(ir_expression *ir);
 373    void resolve_ud_negate(src_reg *reg);
 374    void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
 375
 376    src_reg get_timestamp();
 377
 378    bool process_move_condition(ir_rvalue *ir);
 379
 380    void dump_instruction(backend_instruction *inst);
 381    void dump_instruction(backend_instruction *inst, FILE *file);
 382
 383    void visit_atomic_counter_intrinsic(ir_call *ir);
 384
 385 protected:
 386    void emit_vertex();
 387    void lower_attributes_to_hw_regs(const int *attribute_map,
 388                                     bool interleaved);
 389    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 390                                    int reg_node_count);
 391    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 392    virtual void assign_binding_table_offsets();
 393    virtual void setup_payload() = 0;
 394    virtual void emit_prolog() = 0;
 395    virtual void emit_program_code() = 0;
 396    virtual void emit_thread_end() = 0;
 397    virtual void emit_urb_write_header(int mrf) = 0;
 398    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 399    virtual int compute_array_stride(ir_dereference_array *ir);
 400
 401    const bool debug_flag;
 402
 403 private:
 404    /**
 405     * If true, then register allocation should fail instead of spilling.
 406     */
 407    const bool no_spills;
 408
 409    const shader_time_shader_type st_base;
 410    const shader_time_shader_type st_written;
 411    const shader_time_shader_type st_reset;
 412 };
 413
 414
 415 /**
 416  * The vertex shader code generator.
 417  *
 418  * Translates VS IR to actual i965 assembly code.
 419  */
 420 class vec4_generator
 421 {
 422 public:
 423    vec4_generator(struct brw_context *brw,
 424                   struct gl_shader_program *shader_prog,
 425                   struct gl_program *prog,
 426                   struct brw_vue_prog_data *prog_data,
 427                   void *mem_ctx,
 428                   bool debug_flag,
 429                   const char *stage_name,
 430                   const char *stage_abbrev);
 431    ~vec4_generator();
 432
 433    const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 434
 435 private:
 436    void generate_code(const cfg_t *cfg);
 437
 438    void generate_math1_gen4(vec4_instruction *inst,
 439                             struct brw_reg dst,
 440                             struct brw_reg src);
 441    void generate_math2_gen4(vec4_instruction *inst,
 442                             struct brw_reg dst,
 443                             struct brw_reg src0,
 444                             struct brw_reg src1);
 445    void generate_math_gen6(vec4_instruction *inst,
 446                            struct brw_reg dst,
 447                            struct brw_reg src0,
 448                            struct brw_reg src1);
 449
 450    void generate_tex(vec4_instruction *inst,
 451                      struct brw_reg dst,
 452                      struct brw_reg src,
 453                      struct brw_reg sampler_index);
 454
 455    void generate_vs_urb_write(vec4_instruction *inst);
 456    void generate_gs_urb_write(vec4_instruction *inst);
 457    void generate_gs_urb_write_allocate(vec4_instruction *inst);
 458    void generate_gs_thread_end(vec4_instruction *inst);
 459    void generate_gs_set_write_offset(struct brw_reg dst,
 460                                      struct brw_reg src0,
 461                                      struct brw_reg src1);
 462    void generate_gs_set_vertex_count(struct brw_reg dst,
 463                                      struct brw_reg src);
 464    void generate_gs_svb_write(vec4_instruction *inst,
 465                               struct brw_reg dst,
 466                               struct brw_reg src0,
 467                               struct brw_reg src1);
 468    void generate_gs_svb_set_destination_index(vec4_instruction *inst,
 469                                               struct brw_reg dst,
 470                                               struct brw_reg src);
 471    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
 472    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 473    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 474    void generate_gs_get_instance_id(struct brw_reg dst);
 475    void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
 476                                            struct brw_reg src0,
 477                                            struct brw_reg src1,
 478                                            struct brw_reg src2);
 479    void generate_gs_ff_sync(vec4_instruction *inst,
 480                             struct brw_reg dst,
 481                             struct brw_reg src0,
 482                             struct brw_reg src1);
 483    void generate_gs_set_primitive_id(struct brw_reg dst);
 484    void generate_oword_dual_block_offsets(struct brw_reg m1,
 485                                           struct brw_reg index);
 486    void generate_scratch_write(vec4_instruction *inst,
 487                                struct brw_reg dst,
 488                                struct brw_reg src,
 489                                struct brw_reg index);
 490    void generate_scratch_read(vec4_instruction *inst,
 491                               struct brw_reg dst,
 492                               struct brw_reg index);
 493    void generate_pull_constant_load(vec4_instruction *inst,
 494                                     struct brw_reg dst,
 495                                     struct brw_reg index,
 496                                     struct brw_reg offset);
 497    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 498                                          struct brw_reg dst,
 499                                          struct brw_reg surf_index,
 500                                          struct brw_reg offset);
 501    void generate_unpack_flags(struct brw_reg dst);
 502
 503    void generate_untyped_atomic(vec4_instruction *inst,
 504                                 struct brw_reg dst,
 505                                 struct brw_reg atomic_op,
 506                                 struct brw_reg surf_index);
 507
 508    void generate_untyped_surface_read(vec4_instruction *inst,
 509                                       struct brw_reg dst,
 510                                       struct brw_reg surf_index);
 511
 512    struct brw_context *brw;
 513
 514    struct brw_compile *p;
 515
 516    struct gl_shader_program *shader_prog;
 517    const struct gl_program *prog;
 518
 519    struct brw_vue_prog_data *prog_data;
 520
 521    void *mem_ctx;
 522    const char *stage_name;
 523    const char *stage_abbrev;
 524    const bool debug_flag;
 525 };
 526
 527 } /* namespace brw */
 528 #endif /* __cplusplus */
 529
 530 #endif /* BRW_VEC4_H */