2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
34 #include "brw_context.h"
45 * Common helper for constructing swizzles. When only a subset of
46 * channels of a vec4 are used, we don't want to reference the other
47 * channels, as that will tell optimization passes that those other
51 swizzle_for_size(int size
)
53 static const unsigned size_swizzles
[4] = {
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
56 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
57 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
60 assert((size
>= 1) && (size
<= 4));
61 return size_swizzles
[size
- 1];
65 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
66 GRF
= BRW_GENERAL_REGISTER_FILE
,
67 MRF
= BRW_MESSAGE_REGISTER_FILE
,
68 IMM
= BRW_IMMEDIATE_VALUE
,
69 HW_REG
, /* a struct brw_reg */
71 UNIFORM
, /* prog_data->params[hw_reg] */
78 /** Register file: ARF, GRF, MRF, IMM. */
79 enum register_file file
;
80 /** virtual register number. 0 = fixed hw reg */
82 /** Offset within the virtual register. */
84 /** Register type. BRW_REGISTER_TYPE_* */
86 struct brw_reg fixed_hw_reg
;
88 /** Value for file == BRW_IMMMEDIATE_FILE */
96 class src_reg
: public reg
99 /* Callers of this ralloc-based new need not call delete. It's
100 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
101 static void* operator new(size_t size
, void *ctx
)
105 node
= ralloc_size(ctx
, size
);
106 assert(node
!= NULL
);
113 memset(this, 0, sizeof(*this));
115 this->file
= BAD_FILE
;
118 src_reg(register_file file
, int reg
, const glsl_type
*type
)
124 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
125 this->swizzle
= swizzle_for_size(type
->vector_elements
);
127 this->swizzle
= SWIZZLE_XYZW
;
130 /** Generic unset register constructor. */
141 this->type
= BRW_REGISTER_TYPE_F
;
150 this->type
= BRW_REGISTER_TYPE_UD
;
159 this->type
= BRW_REGISTER_TYPE_D
;
163 bool equals(src_reg
*r
);
164 bool is_zero() const;
167 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
169 explicit src_reg(dst_reg reg
);
171 GLuint swizzle
; /**< SWIZZLE_XYZW swizzles from Mesa. */
178 class dst_reg
: public reg
181 /* Callers of this ralloc-based new need not call delete. It's
182 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
183 static void* operator new(size_t size
, void *ctx
)
187 node
= ralloc_size(ctx
, size
);
188 assert(node
!= NULL
);
195 memset(this, 0, sizeof(*this));
196 this->file
= BAD_FILE
;
197 this->writemask
= WRITEMASK_XYZW
;
205 dst_reg(register_file file
, int reg
)
213 dst_reg(struct brw_reg reg
)
218 this->fixed_hw_reg
= reg
;
221 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
223 explicit dst_reg(src_reg reg
);
225 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
230 class vec4_instruction
: public exec_node
{
232 /* Callers of this ralloc-based new need not call delete. It's
233 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
234 static void* operator new(size_t size
, void *ctx
)
238 node
= rzalloc_size(ctx
, size
);
239 assert(node
!= NULL
);
244 vec4_instruction(vec4_visitor
*v
, enum opcode opcode
,
245 dst_reg dst
= dst_reg(),
246 src_reg src0
= src_reg(),
247 src_reg src1
= src_reg(),
248 src_reg src2
= src_reg());
250 struct brw_reg
get_dst(void);
251 struct brw_reg
get_src(int i
);
253 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
258 bool predicate_inverse
;
261 int conditional_mod
; /**< BRW_CONDITIONAL_* */
264 int target
; /**< MRT target. */
269 int mlen
; /**< SEND message length */
270 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
272 uint32_t offset
; /* spill/unspill offset */
274 * Annotation for the generated IR. One of the two can be set.
277 const char *annotation
;
283 class vec4_visitor
: public ir_visitor
286 vec4_visitor(struct brw_vs_compile
*c
,
287 struct gl_shader_program
*prog
, struct brw_shader
*shader
);
292 return dst_reg(brw_null_reg());
297 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
300 struct brw_context
*brw
;
301 const struct gl_vertex_program
*vp
;
302 struct intel_context
*intel
;
303 struct gl_context
*ctx
;
304 struct brw_vs_compile
*c
;
305 struct brw_vs_prog_data
*prog_data
;
306 struct brw_compile
*p
;
307 struct brw_shader
*shader
;
308 struct gl_shader_program
*prog
;
310 exec_list instructions
;
316 * GLSL IR currently being processed, which is associated with our
317 * driver IR instructions for debugging purposes.
319 ir_instruction
*base_ir
;
320 const char *current_annotation
;
322 int *virtual_grf_sizes
;
323 int virtual_grf_count
;
324 int virtual_grf_array_size
;
325 int first_non_payload_grf
;
326 int *virtual_grf_def
;
327 int *virtual_grf_use
;
328 dst_reg userplane
[MAX_CLIP_PLANES
];
331 * This is the size to be used for an array with an element per
334 int virtual_grf_reg_count
;
335 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
336 int *virtual_grf_reg_map
;
338 bool live_intervals_valid
;
340 dst_reg
*variable_storage(ir_variable
*var
);
342 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
344 src_reg
src_reg_for_float(float val
);
347 * \name Visit methods
349 * As typical for the visitor pattern, there must be one \c visit method for
350 * each concrete subclass of \c ir_instruction. Virtual base classes within
351 * the hierarchy should not have \c visit methods.
354 virtual void visit(ir_variable
*);
355 virtual void visit(ir_loop
*);
356 virtual void visit(ir_loop_jump
*);
357 virtual void visit(ir_function_signature
*);
358 virtual void visit(ir_function
*);
359 virtual void visit(ir_expression
*);
360 virtual void visit(ir_swizzle
*);
361 virtual void visit(ir_dereference_variable
*);
362 virtual void visit(ir_dereference_array
*);
363 virtual void visit(ir_dereference_record
*);
364 virtual void visit(ir_assignment
*);
365 virtual void visit(ir_constant
*);
366 virtual void visit(ir_call
*);
367 virtual void visit(ir_return
*);
368 virtual void visit(ir_discard
*);
369 virtual void visit(ir_texture
*);
370 virtual void visit(ir_if
*);
375 /* Regs for vertex results. Generated at ir_variable visiting time
376 * for the ir->location's used.
378 dst_reg output_reg
[BRW_VERT_RESULT_MAX
];
379 const char *output_reg_annotation
[BRW_VERT_RESULT_MAX
];
380 int uniform_size
[MAX_UNIFORMS
];
381 int uniform_vector_size
[MAX_UNIFORMS
];
384 struct hash_table
*variable_ht
;
387 void fail(const char *msg
, ...);
389 int virtual_grf_alloc(int size
);
390 void setup_uniform_clipplane_values();
391 int setup_uniform_values(int loc
, const glsl_type
*type
);
392 void setup_builtin_uniform_values(ir_variable
*ir
);
393 int setup_attributes(int payload_reg
);
394 int setup_uniforms(int payload_reg
);
395 void setup_payload();
396 void reg_allocate_trivial();
398 void move_grf_array_access_to_scratch();
399 void move_uniform_array_access_to_pull_constants();
400 void move_push_constants_to_pull_constants();
401 void split_uniform_registers();
402 void pack_uniform_registers();
403 void calculate_live_intervals();
404 bool dead_code_eliminate();
405 bool virtual_grf_interferes(int a
, int b
);
406 bool opt_copy_propagation();
407 bool opt_algebraic();
408 bool opt_compute_to_mrf();
410 vec4_instruction
*emit(vec4_instruction
*inst
);
412 vec4_instruction
*emit(enum opcode opcode
);
414 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
, src_reg src0
);
416 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
417 src_reg src0
, src_reg src1
);
419 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
420 src_reg src0
, src_reg src1
, src_reg src2
);
422 vec4_instruction
*emit_before(vec4_instruction
*inst
,
423 vec4_instruction
*new_inst
);
425 vec4_instruction
*MOV(dst_reg dst
, src_reg src0
);
426 vec4_instruction
*NOT(dst_reg dst
, src_reg src0
);
427 vec4_instruction
*RNDD(dst_reg dst
, src_reg src0
);
428 vec4_instruction
*RNDE(dst_reg dst
, src_reg src0
);
429 vec4_instruction
*RNDZ(dst_reg dst
, src_reg src0
);
430 vec4_instruction
*FRC(dst_reg dst
, src_reg src0
);
431 vec4_instruction
*ADD(dst_reg dst
, src_reg src0
, src_reg src1
);
432 vec4_instruction
*MUL(dst_reg dst
, src_reg src0
, src_reg src1
);
433 vec4_instruction
*MACH(dst_reg dst
, src_reg src0
, src_reg src1
);
434 vec4_instruction
*MAC(dst_reg dst
, src_reg src0
, src_reg src1
);
435 vec4_instruction
*AND(dst_reg dst
, src_reg src0
, src_reg src1
);
436 vec4_instruction
*OR(dst_reg dst
, src_reg src0
, src_reg src1
);
437 vec4_instruction
*XOR(dst_reg dst
, src_reg src0
, src_reg src1
);
438 vec4_instruction
*DP3(dst_reg dst
, src_reg src0
, src_reg src1
);
439 vec4_instruction
*DP4(dst_reg dst
, src_reg src0
, src_reg src1
);
440 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
442 vec4_instruction
*IF(src_reg src0
, src_reg src1
, uint32_t condition
);
443 vec4_instruction
*IF(uint32_t predicate
);
444 vec4_instruction
*PULL_CONSTANT_LOAD(dst_reg dst
, src_reg index
);
445 vec4_instruction
*SCRATCH_READ(dst_reg dst
, src_reg index
);
446 vec4_instruction
*SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
);
448 int implied_mrf_writes(vec4_instruction
*inst
);
450 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
453 vec4_instruction
*pre_rhs_inst
,
454 vec4_instruction
*last_rhs_inst
);
456 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
457 void visit_instructions(const exec_list
*list
);
459 void emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
);
460 void emit_bool_comparison(unsigned int op
, dst_reg dst
, src_reg src0
, src_reg src1
);
461 void emit_if_gen6(ir_if
*ir
);
463 void emit_block_move(dst_reg
*dst
, src_reg
*src
,
464 const struct glsl_type
*type
, uint32_t predicate
);
466 void emit_constant_values(dst_reg
*dst
, ir_constant
*value
);
469 * Emit the correct dot-product instruction for the type of arguments
471 void emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
);
473 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
474 dst_reg dst
, src_reg src0
);
476 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
477 dst_reg dst
, src_reg src0
, src_reg src1
);
479 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
480 dst_reg dst
, const src_reg
&src
);
482 void emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
);
483 void emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
);
484 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src
);
485 void emit_math2_gen6(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
486 void emit_math2_gen4(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
487 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
489 void emit_ndc_computation();
490 void emit_psiz_and_flags(struct brw_reg reg
);
491 void emit_clip_distances(struct brw_reg reg
, int offset
);
492 void emit_generic_urb_slot(dst_reg reg
, int vert_result
);
493 void emit_urb_slot(int mrf
, int vert_result
);
494 void emit_urb_writes(void);
496 src_reg
get_scratch_offset(vec4_instruction
*inst
,
497 src_reg
*reladdr
, int reg_offset
);
498 src_reg
get_pull_constant_offset(vec4_instruction
*inst
,
499 src_reg
*reladdr
, int reg_offset
);
500 void emit_scratch_read(vec4_instruction
*inst
,
504 void emit_scratch_write(vec4_instruction
*inst
,
508 void emit_pull_constant_load(vec4_instruction
*inst
,
513 bool try_emit_sat(ir_expression
*ir
);
514 void resolve_ud_negate(src_reg
*reg
);
516 bool process_move_condition(ir_rvalue
*ir
);
518 void generate_code();
519 void generate_vs_instruction(vec4_instruction
*inst
,
521 struct brw_reg
*src
);
523 void generate_math1_gen4(vec4_instruction
*inst
,
526 void generate_math1_gen6(vec4_instruction
*inst
,
529 void generate_math2_gen4(vec4_instruction
*inst
,
532 struct brw_reg src1
);
533 void generate_math2_gen6(vec4_instruction
*inst
,
536 struct brw_reg src1
);
537 void generate_math2_gen7(vec4_instruction
*inst
,
540 struct brw_reg src1
);
542 void generate_urb_write(vec4_instruction
*inst
);
543 void generate_oword_dual_block_offsets(struct brw_reg m1
,
544 struct brw_reg index
);
545 void generate_scratch_write(vec4_instruction
*inst
,
548 struct brw_reg index
);
549 void generate_scratch_read(vec4_instruction
*inst
,
551 struct brw_reg index
);
552 void generate_pull_constant_load(vec4_instruction
*inst
,
554 struct brw_reg index
);
557 } /* namespace brw */
559 #endif /* BRW_VEC4_H */