src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39 #include "intel_asm_annotation.h"
  40
  41 #ifdef __cplusplus
  42 }; /* extern "C" */
  43 #endif
  44
  45 #include "glsl/ir.h"
  46
  47
  48 struct brw_vec4_compile {
  49    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  50 };
  51
  52
  53 struct brw_vec4_prog_key {
  54    GLuint program_string_id;
  55
  56    /**
  57     * True if at least one clip flag is enabled, regardless of whether the
  58     * shader uses clip planes or gl_ClipDistance.
  59     */
  60    GLuint userclip_active:1;
  61
  62    /**
  63     * How many user clipping planes are being uploaded to the vertex shader as
  64     * push constants.
  65     */
  66    GLuint nr_userclip_plane_consts:4;
  67
  68    GLuint clamp_vertex_color:1;
  69
  70    struct brw_sampler_prog_key_data tex;
  71 };
  72
  73
  74 #ifdef __cplusplus
  75 extern "C" {
  76 #endif
  77
  78 void
  79 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
  80                                        struct brw_vec4_prog_key *key,
  81                                        GLuint id, struct gl_program *prog);
  82
  83 #ifdef __cplusplus
  84 } /* extern "C" */
  85
  86 namespace brw {
  87
  88 class dst_reg;
  89
  90 unsigned
  91 swizzle_for_size(int size);
  92
  93 class src_reg : public backend_reg
  94 {
  95 public:
  96    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  97
  98    void init();
  99
 100    src_reg(register_file file, int reg, const glsl_type *type);
 101    src_reg();
 102    src_reg(float f);
 103    src_reg(uint32_t u);
 104    src_reg(int32_t i);
 105    src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
 106    src_reg(struct brw_reg reg);
 107
 108    bool equals(const src_reg &r) const;
 109
 110    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 111    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
 112
 113    explicit src_reg(dst_reg reg);
 114
 115    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 116
 117    src_reg *reladdr;
 118 };
 119
 120 static inline src_reg
 121 retype(src_reg reg, enum brw_reg_type type)
 122 {
 123    reg.fixed_hw_reg.type = reg.type = type;
 124    return reg;
 125 }
 126
 127 static inline src_reg
 128 offset(src_reg reg, unsigned delta)
 129 {
 130    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 131    reg.reg_offset += delta;
 132    return reg;
 133 }
 134
 135 /**
 136  * Reswizzle a given source register.
 137  * \sa brw_swizzle().
 138  */
 139 static inline src_reg
 140 swizzle(src_reg reg, unsigned swizzle)
 141 {
 142    assert(reg.file != HW_REG);
 143    reg.swizzle = BRW_SWIZZLE4(
 144       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
 145       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
 146       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
 147       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
 148    return reg;
 149 }
 150
 151 static inline src_reg
 152 negate(src_reg reg)
 153 {
 154    assert(reg.file != HW_REG && reg.file != IMM);
 155    reg.negate = !reg.negate;
 156    return reg;
 157 }
 158
 159 class dst_reg : public backend_reg
 160 {
 161 public:
 162    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 163
 164    void init();
 165
 166    dst_reg();
 167    dst_reg(register_file file, int reg);
 168    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 169    dst_reg(struct brw_reg reg);
 170    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 171
 172    explicit dst_reg(src_reg reg);
 173
 174    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 175
 176    src_reg *reladdr;
 177 };
 178
 179 static inline dst_reg
 180 retype(dst_reg reg, enum brw_reg_type type)
 181 {
 182    reg.fixed_hw_reg.type = reg.type = type;
 183    return reg;
 184 }
 185
 186 static inline dst_reg
 187 offset(dst_reg reg, unsigned delta)
 188 {
 189    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 190    reg.reg_offset += delta;
 191    return reg;
 192 }
 193
 194 static inline dst_reg
 195 writemask(dst_reg reg, unsigned mask)
 196 {
 197    assert(reg.file != HW_REG && reg.file != IMM);
 198    assert((reg.writemask & mask) != 0);
 199    reg.writemask &= mask;
 200    return reg;
 201 }
 202
 203 class vec4_instruction : public backend_instruction {
 204 public:
 205    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 206
 207    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 208                     const dst_reg &dst = dst_reg(),
 209                     const src_reg &src0 = src_reg(),
 210                     const src_reg &src1 = src_reg(),
 211                     const src_reg &src2 = src_reg());
 212
 213    struct brw_reg get_dst(void);
 214    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 215
 216    dst_reg dst;
 217    src_reg src[3];
 218
 219    enum brw_urb_write_flags urb_write_flags;
 220
 221    unsigned sol_binding; /**< gen6: SOL binding table index */
 222    bool sol_final_write; /**< gen6: send commit message */
 223    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 224
 225    bool is_send_from_grf();
 226    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
 227    void reswizzle(int dst_writemask, int swizzle);
 228    bool can_do_source_mods(struct brw_context *brw);
 229
 230    bool reads_flag()
 231    {
 232       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 233    }
 234
 235    bool writes_flag()
 236    {
 237       return conditional_mod && opcode != BRW_OPCODE_SEL;
 238    }
 239 };
 240
 241 /**
 242  * The vertex shader front-end.
 243  *
 244  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 245  * fixed-function) into VS IR.
 246  */
 247 class vec4_visitor : public backend_visitor
 248 {
 249 public:
 250    vec4_visitor(struct brw_context *brw,
 251                 struct brw_vec4_compile *c,
 252                 struct gl_program *prog,
 253                 const struct brw_vec4_prog_key *key,
 254                 struct brw_vec4_prog_data *prog_data,
 255                 struct gl_shader_program *shader_prog,
 256                 gl_shader_stage stage,
 257                 void *mem_ctx,
 258                 bool debug_flag,
 259                 bool no_spills,
 260                 shader_time_shader_type st_base,
 261                 shader_time_shader_type st_written,
 262                 shader_time_shader_type st_reset);
 263    ~vec4_visitor();
 264
 265    dst_reg dst_null_f()
 266    {
 267       return dst_reg(brw_null_reg());
 268    }
 269
 270    dst_reg dst_null_d()
 271    {
 272       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 273    }
 274
 275    dst_reg dst_null_ud()
 276    {
 277       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 278    }
 279
 280    struct brw_vec4_compile * const c;
 281    const struct brw_vec4_prog_key * const key;
 282    struct brw_vec4_prog_data * const prog_data;
 283    unsigned int sanity_param_count;
 284
 285    char *fail_msg;
 286    bool failed;
 287
 288    /**
 289     * GLSL IR currently being processed, which is associated with our
 290     * driver IR instructions for debugging purposes.
 291     */
 292    const void *base_ir;
 293    const char *current_annotation;
 294
 295    int *virtual_grf_sizes;
 296    int virtual_grf_count;
 297    int virtual_grf_array_size;
 298    int first_non_payload_grf;
 299    unsigned int max_grf;
 300    int *virtual_grf_start;
 301    int *virtual_grf_end;
 302    dst_reg userplane[MAX_CLIP_PLANES];
 303
 304    /**
 305     * This is the size to be used for an array with an element per
 306     * reg_offset
 307     */
 308    int virtual_grf_reg_count;
 309    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 310    int *virtual_grf_reg_map;
 311
 312    bool live_intervals_valid;
 313
 314    dst_reg *variable_storage(ir_variable *var);
 315
 316    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 317
 318    bool need_all_constants_in_pull_buffer;
 319
 320    /**
 321     * \name Visit methods
 322     *
 323     * As typical for the visitor pattern, there must be one \c visit method for
 324     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 325     * the hierarchy should not have \c visit methods.
 326     */
 327    /*@{*/
 328    virtual void visit(ir_variable *);
 329    virtual void visit(ir_loop *);
 330    virtual void visit(ir_loop_jump *);
 331    virtual void visit(ir_function_signature *);
 332    virtual void visit(ir_function *);
 333    virtual void visit(ir_expression *);
 334    virtual void visit(ir_swizzle *);
 335    virtual void visit(ir_dereference_variable  *);
 336    virtual void visit(ir_dereference_array *);
 337    virtual void visit(ir_dereference_record *);
 338    virtual void visit(ir_assignment *);
 339    virtual void visit(ir_constant *);
 340    virtual void visit(ir_call *);
 341    virtual void visit(ir_return *);
 342    virtual void visit(ir_discard *);
 343    virtual void visit(ir_texture *);
 344    virtual void visit(ir_if *);
 345    virtual void visit(ir_emit_vertex *);
 346    virtual void visit(ir_end_primitive *);
 347    /*@}*/
 348
 349    src_reg result;
 350
 351    /* Regs for vertex results.  Generated at ir_variable visiting time
 352     * for the ir->location's used.
 353     */
 354    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 355    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 356    int *uniform_size;
 357    int *uniform_vector_size;
 358    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 359    int uniforms;
 360
 361    src_reg shader_start_time;
 362
 363    struct hash_table *variable_ht;
 364
 365    bool run(void);
 366    void fail(const char *msg, ...);
 367
 368    int virtual_grf_alloc(int size);
 369    void setup_uniform_clipplane_values();
 370    void setup_uniform_values(ir_variable *ir);
 371    void setup_builtin_uniform_values(ir_variable *ir);
 372    int setup_uniforms(int payload_reg);
 373    bool reg_allocate_trivial();
 374    bool reg_allocate();
 375    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 376    int choose_spill_reg(struct ra_graph *g);
 377    void spill_reg(int spill_reg);
 378    void move_grf_array_access_to_scratch();
 379    void move_uniform_array_access_to_pull_constants();
 380    void move_push_constants_to_pull_constants();
 381    void split_uniform_registers();
 382    void pack_uniform_registers();
 383    void calculate_live_intervals();
 384    void invalidate_live_intervals();
 385    void split_virtual_grfs();
 386    bool opt_reduce_swizzle();
 387    bool dead_code_eliminate();
 388    bool virtual_grf_interferes(int a, int b);
 389    bool opt_copy_propagation();
 390    bool opt_cse_local(bblock_t *block);
 391    bool opt_cse();
 392    bool opt_algebraic();
 393    bool opt_register_coalesce();
 394    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 395    void opt_set_dependency_control();
 396    void opt_schedule_instructions();
 397
 398    vec4_instruction *emit(vec4_instruction *inst);
 399
 400    vec4_instruction *emit(enum opcode opcode);
 401    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 402    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 403                           const src_reg &src0);
 404    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 405                           const src_reg &src0, const src_reg &src1);
 406    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 407                           const src_reg &src0, const src_reg &src1,
 408                           const src_reg &src2);
 409
 410    vec4_instruction *emit_before(bblock_t *block,
 411                                  vec4_instruction *inst,
 412                                  vec4_instruction *new_inst);
 413
 414 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 415 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 416 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 417    EMIT1(MOV)
 418    EMIT1(NOT)
 419    EMIT1(RNDD)
 420    EMIT1(RNDE)
 421    EMIT1(RNDZ)
 422    EMIT1(FRC)
 423    EMIT1(F32TO16)
 424    EMIT1(F16TO32)
 425    EMIT2(ADD)
 426    EMIT2(MUL)
 427    EMIT2(MACH)
 428    EMIT2(MAC)
 429    EMIT2(AND)
 430    EMIT2(OR)
 431    EMIT2(XOR)
 432    EMIT2(DP3)
 433    EMIT2(DP4)
 434    EMIT2(DPH)
 435    EMIT2(SHL)
 436    EMIT2(SHR)
 437    EMIT2(ASR)
 438    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 439                          enum brw_conditional_mod condition);
 440    vec4_instruction *IF(src_reg src0, src_reg src1,
 441                         enum brw_conditional_mod condition);
 442    vec4_instruction *IF(enum brw_predicate predicate);
 443    EMIT1(PULL_CONSTANT_LOAD)
 444    EMIT1(SCRATCH_READ)
 445    EMIT2(SCRATCH_WRITE)
 446    EMIT3(LRP)
 447    EMIT1(BFREV)
 448    EMIT3(BFE)
 449    EMIT2(BFI1)
 450    EMIT3(BFI2)
 451    EMIT1(FBH)
 452    EMIT1(FBL)
 453    EMIT1(CBIT)
 454    EMIT3(MAD)
 455    EMIT2(ADDC)
 456    EMIT2(SUBB)
 457 #undef EMIT1
 458 #undef EMIT2
 459 #undef EMIT3
 460
 461    int implied_mrf_writes(vec4_instruction *inst);
 462
 463    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 464                                dst_reg dst,
 465                                src_reg src,
 466                                vec4_instruction *pre_rhs_inst,
 467                                vec4_instruction *last_rhs_inst);
 468
 469    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 470    void visit_instructions(const exec_list *list);
 471
 472    void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 473                     src_reg src0, src_reg src1, src_reg one);
 474
 475    void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
 476    void emit_if_gen6(ir_if *ir);
 477
 478    void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 479                     src_reg src0, src_reg src1);
 480
 481    void emit_lrp(const dst_reg &dst,
 482                  const src_reg &x, const src_reg &y, const src_reg &a);
 483
 484    void emit_block_move(dst_reg *dst, src_reg *src,
 485                         const struct glsl_type *type, brw_predicate predicate);
 486
 487    void emit_constant_values(dst_reg *dst, ir_constant *value);
 488
 489    /**
 490     * Emit the correct dot-product instruction for the type of arguments
 491     */
 492    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 493
 494    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 495                     dst_reg dst, src_reg src0);
 496
 497    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 498                     dst_reg dst, src_reg src0, src_reg src1);
 499
 500    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 501                  dst_reg dst, const src_reg &src);
 502
 503    src_reg fix_3src_operand(src_reg src);
 504
 505    void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 506                   const src_reg &src1 = src_reg());
 507    src_reg fix_math_operand(src_reg src);
 508
 509    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 510    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 511    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 512    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 513    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 514
 515    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 516    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
 517    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 518    void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 519
 520    void emit_ndc_computation();
 521    void emit_psiz_and_flags(dst_reg reg);
 522    void emit_clip_distances(dst_reg reg, int offset);
 523    void emit_generic_urb_slot(dst_reg reg, int varying);
 524    void emit_urb_slot(dst_reg reg, int varying);
 525
 526    void emit_shader_time_begin();
 527    void emit_shader_time_end();
 528    void emit_shader_time_write(enum shader_time_shader_type type,
 529                                src_reg value);
 530
 531    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 532                             dst_reg dst, src_reg offset, src_reg src0,
 533                             src_reg src1);
 534
 535    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 536                                   src_reg offset);
 537
 538    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 539                               src_reg *reladdr, int reg_offset);
 540    src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
 541                                     src_reg *reladdr, int reg_offset);
 542    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 543                           dst_reg dst,
 544                           src_reg orig_src,
 545                           int base_offset);
 546    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 547                            int base_offset);
 548    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 549                                 dst_reg dst,
 550                                 src_reg orig_src,
 551                                 int base_offset);
 552
 553    bool try_emit_mad(ir_expression *ir);
 554    bool try_emit_b2f_of_compare(ir_expression *ir);
 555    void resolve_ud_negate(src_reg *reg);
 556
 557    src_reg get_timestamp();
 558
 559    bool process_move_condition(ir_rvalue *ir);
 560
 561    void dump_instruction(backend_instruction *inst);
 562    void dump_instruction(backend_instruction *inst, FILE *file);
 563
 564    void visit_atomic_counter_intrinsic(ir_call *ir);
 565
 566 protected:
 567    void emit_vertex();
 568    void lower_attributes_to_hw_regs(const int *attribute_map,
 569                                     bool interleaved);
 570    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 571                                    int reg_node_count);
 572    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 573    virtual void assign_binding_table_offsets();
 574    virtual void setup_payload() = 0;
 575    virtual void emit_prolog() = 0;
 576    virtual void emit_program_code() = 0;
 577    virtual void emit_thread_end() = 0;
 578    virtual void emit_urb_write_header(int mrf) = 0;
 579    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 580    virtual int compute_array_stride(ir_dereference_array *ir);
 581
 582    const bool debug_flag;
 583
 584 private:
 585    /**
 586     * If true, then register allocation should fail instead of spilling.
 587     */
 588    const bool no_spills;
 589
 590    const shader_time_shader_type st_base;
 591    const shader_time_shader_type st_written;
 592    const shader_time_shader_type st_reset;
 593 };
 594
 595
 596 /**
 597  * The vertex shader code generator.
 598  *
 599  * Translates VS IR to actual i965 assembly code.
 600  */
 601 class vec4_generator
 602 {
 603 public:
 604    vec4_generator(struct brw_context *brw,
 605                   struct gl_shader_program *shader_prog,
 606                   struct gl_program *prog,
 607                   struct brw_vec4_prog_data *prog_data,
 608                   void *mem_ctx,
 609                   bool debug_flag);
 610    ~vec4_generator();
 611
 612    const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 613
 614 private:
 615    void generate_code(const cfg_t *cfg);
 616
 617    void generate_math1_gen4(vec4_instruction *inst,
 618                             struct brw_reg dst,
 619                             struct brw_reg src);
 620    void generate_math2_gen4(vec4_instruction *inst,
 621                             struct brw_reg dst,
 622                             struct brw_reg src0,
 623                             struct brw_reg src1);
 624    void generate_math_gen6(vec4_instruction *inst,
 625                            struct brw_reg dst,
 626                            struct brw_reg src0,
 627                            struct brw_reg src1);
 628
 629    void generate_tex(vec4_instruction *inst,
 630                      struct brw_reg dst,
 631                      struct brw_reg src,
 632                      struct brw_reg sampler_index);
 633
 634    void generate_vs_urb_write(vec4_instruction *inst);
 635    void generate_gs_urb_write(vec4_instruction *inst);
 636    void generate_gs_urb_write_allocate(vec4_instruction *inst);
 637    void generate_gs_thread_end(vec4_instruction *inst);
 638    void generate_gs_set_write_offset(struct brw_reg dst,
 639                                      struct brw_reg src0,
 640                                      struct brw_reg src1);
 641    void generate_gs_set_vertex_count(struct brw_reg dst,
 642                                      struct brw_reg src);
 643    void generate_gs_svb_write(vec4_instruction *inst,
 644                               struct brw_reg dst,
 645                               struct brw_reg src0,
 646                               struct brw_reg src1);
 647    void generate_gs_svb_set_destination_index(vec4_instruction *inst,
 648                                               struct brw_reg dst,
 649                                               struct brw_reg src);
 650    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
 651    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 652    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 653    void generate_gs_get_instance_id(struct brw_reg dst);
 654    void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
 655                                            struct brw_reg src0,
 656                                            struct brw_reg src1,
 657                                            struct brw_reg src2);
 658    void generate_gs_ff_sync(vec4_instruction *inst,
 659                             struct brw_reg dst,
 660                             struct brw_reg src0,
 661                             struct brw_reg src1);
 662    void generate_gs_set_primitive_id(struct brw_reg dst);
 663    void generate_oword_dual_block_offsets(struct brw_reg m1,
 664                                           struct brw_reg index);
 665    void generate_scratch_write(vec4_instruction *inst,
 666                                struct brw_reg dst,
 667                                struct brw_reg src,
 668                                struct brw_reg index);
 669    void generate_scratch_read(vec4_instruction *inst,
 670                               struct brw_reg dst,
 671                               struct brw_reg index);
 672    void generate_pull_constant_load(vec4_instruction *inst,
 673                                     struct brw_reg dst,
 674                                     struct brw_reg index,
 675                                     struct brw_reg offset);
 676    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 677                                          struct brw_reg dst,
 678                                          struct brw_reg surf_index,
 679                                          struct brw_reg offset);
 680    void generate_unpack_flags(vec4_instruction *inst,
 681                               struct brw_reg dst);
 682
 683    void generate_untyped_atomic(vec4_instruction *inst,
 684                                 struct brw_reg dst,
 685                                 struct brw_reg atomic_op,
 686                                 struct brw_reg surf_index);
 687
 688    void generate_untyped_surface_read(vec4_instruction *inst,
 689                                       struct brw_reg dst,
 690                                       struct brw_reg surf_index);
 691
 692    struct brw_context *brw;
 693
 694    struct brw_compile *p;
 695
 696    struct gl_shader_program *shader_prog;
 697    const struct gl_program *prog;
 698
 699    struct brw_vec4_prog_data *prog_data;
 700
 701    void *mem_ctx;
 702    const bool debug_flag;
 703 };
 704
 705 } /* namespace brw */
 706 #endif /* __cplusplus */
 707
 708 #endif /* BRW_VEC4_H */