src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39 #include "intel_asm_annotation.h"
  40
  41 #ifdef __cplusplus
  42 }; /* extern "C" */
  43 #endif
  44
  45 #include "glsl/ir.h"
  46
  47
  48 struct brw_vec4_compile {
  49    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  50 };
  51
  52 #ifdef __cplusplus
  53 extern "C" {
  54 #endif
  55
  56 void
  57 brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx,
  58                                       struct brw_vue_prog_key *key,
  59                                       GLuint id, struct gl_program *prog);
  60
  61 #ifdef __cplusplus
  62 } /* extern "C" */
  63
  64 namespace brw {
  65
  66 class dst_reg;
  67
  68 class vec4_live_variables;
  69
  70 unsigned
  71 swizzle_for_size(int size);
  72
  73 class src_reg : public backend_reg
  74 {
  75 public:
  76    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  77
  78    void init();
  79
  80    src_reg(register_file file, int reg, const glsl_type *type);
  81    src_reg();
  82    src_reg(float f);
  83    src_reg(uint32_t u);
  84    src_reg(int32_t i);
  85    src_reg(uint8_t vf[4]);
  86    src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  87    src_reg(struct brw_reg reg);
  88
  89    bool equals(const src_reg &r) const;
  90
  91    src_reg(class vec4_visitor *v, const struct glsl_type *type);
  92    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
  93
  94    explicit src_reg(dst_reg reg);
  95
  96    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
  97
  98    src_reg *reladdr;
  99 };
 100
 101 static inline src_reg
 102 retype(src_reg reg, enum brw_reg_type type)
 103 {
 104    reg.fixed_hw_reg.type = reg.type = type;
 105    return reg;
 106 }
 107
 108 static inline src_reg
 109 offset(src_reg reg, unsigned delta)
 110 {
 111    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 112    reg.reg_offset += delta;
 113    return reg;
 114 }
 115
 116 /**
 117  * Reswizzle a given source register.
 118  * \sa brw_swizzle().
 119  */
 120 static inline src_reg
 121 swizzle(src_reg reg, unsigned swizzle)
 122 {
 123    assert(reg.file != HW_REG);
 124    reg.swizzle = BRW_SWIZZLE4(
 125       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
 126       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
 127       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
 128       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
 129    return reg;
 130 }
 131
 132 static inline src_reg
 133 negate(src_reg reg)
 134 {
 135    assert(reg.file != HW_REG && reg.file != IMM);
 136    reg.negate = !reg.negate;
 137    return reg;
 138 }
 139
 140 class dst_reg : public backend_reg
 141 {
 142 public:
 143    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 144
 145    void init();
 146
 147    dst_reg();
 148    dst_reg(register_file file, int reg);
 149    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 150    dst_reg(struct brw_reg reg);
 151    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 152
 153    explicit dst_reg(src_reg reg);
 154
 155    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 156
 157    src_reg *reladdr;
 158 };
 159
 160 static inline dst_reg
 161 retype(dst_reg reg, enum brw_reg_type type)
 162 {
 163    reg.fixed_hw_reg.type = reg.type = type;
 164    return reg;
 165 }
 166
 167 static inline dst_reg
 168 offset(dst_reg reg, unsigned delta)
 169 {
 170    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 171    reg.reg_offset += delta;
 172    return reg;
 173 }
 174
 175 static inline dst_reg
 176 writemask(dst_reg reg, unsigned mask)
 177 {
 178    assert(reg.file != HW_REG && reg.file != IMM);
 179    assert((reg.writemask & mask) != 0);
 180    reg.writemask &= mask;
 181    return reg;
 182 }
 183
 184 class vec4_instruction : public backend_instruction {
 185 public:
 186    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 187
 188    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 189                     const dst_reg &dst = dst_reg(),
 190                     const src_reg &src0 = src_reg(),
 191                     const src_reg &src1 = src_reg(),
 192                     const src_reg &src2 = src_reg());
 193
 194    struct brw_reg get_dst(void);
 195    struct brw_reg get_src(const struct brw_vue_prog_data *prog_data, int i);
 196
 197    dst_reg dst;
 198    src_reg src[3];
 199
 200    enum brw_urb_write_flags urb_write_flags;
 201
 202    unsigned sol_binding; /**< gen6: SOL binding table index */
 203    bool sol_final_write; /**< gen6: send commit message */
 204    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 205
 206    bool is_send_from_grf();
 207    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
 208    void reswizzle(int dst_writemask, int swizzle);
 209    bool can_do_source_mods(struct brw_context *brw);
 210
 211    bool reads_flag()
 212    {
 213       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 214    }
 215
 216    bool writes_flag()
 217    {
 218       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
 219                                   opcode != BRW_OPCODE_IF &&
 220                                   opcode != BRW_OPCODE_WHILE));
 221    }
 222 };
 223
 224 /**
 225  * The vertex shader front-end.
 226  *
 227  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 228  * fixed-function) into VS IR.
 229  */
 230 class vec4_visitor : public backend_visitor
 231 {
 232 public:
 233    vec4_visitor(struct brw_context *brw,
 234                 struct brw_vec4_compile *c,
 235                 struct gl_program *prog,
 236                 const struct brw_vue_prog_key *key,
 237                 struct brw_vue_prog_data *prog_data,
 238                 struct gl_shader_program *shader_prog,
 239                 gl_shader_stage stage,
 240                 void *mem_ctx,
 241                 bool debug_flag,
 242                 bool no_spills,
 243                 shader_time_shader_type st_base,
 244                 shader_time_shader_type st_written,
 245                 shader_time_shader_type st_reset);
 246    ~vec4_visitor();
 247
 248    dst_reg dst_null_f()
 249    {
 250       return dst_reg(brw_null_reg());
 251    }
 252
 253    dst_reg dst_null_d()
 254    {
 255       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 256    }
 257
 258    dst_reg dst_null_ud()
 259    {
 260       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 261    }
 262
 263    struct brw_vec4_compile * const c;
 264    const struct brw_vue_prog_key * const key;
 265    struct brw_vue_prog_data * const prog_data;
 266    unsigned int sanity_param_count;
 267
 268    char *fail_msg;
 269    bool failed;
 270
 271    /**
 272     * GLSL IR currently being processed, which is associated with our
 273     * driver IR instructions for debugging purposes.
 274     */
 275    const void *base_ir;
 276    const char *current_annotation;
 277
 278    int first_non_payload_grf;
 279    unsigned int max_grf;
 280    int *virtual_grf_start;
 281    int *virtual_grf_end;
 282    brw::vec4_live_variables *live_intervals;
 283    dst_reg userplane[MAX_CLIP_PLANES];
 284
 285    dst_reg *variable_storage(ir_variable *var);
 286
 287    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 288
 289    bool need_all_constants_in_pull_buffer;
 290
 291    /**
 292     * \name Visit methods
 293     *
 294     * As typical for the visitor pattern, there must be one \c visit method for
 295     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 296     * the hierarchy should not have \c visit methods.
 297     */
 298    /*@{*/
 299    virtual void visit(ir_variable *);
 300    virtual void visit(ir_loop *);
 301    virtual void visit(ir_loop_jump *);
 302    virtual void visit(ir_function_signature *);
 303    virtual void visit(ir_function *);
 304    virtual void visit(ir_expression *);
 305    virtual void visit(ir_swizzle *);
 306    virtual void visit(ir_dereference_variable  *);
 307    virtual void visit(ir_dereference_array *);
 308    virtual void visit(ir_dereference_record *);
 309    virtual void visit(ir_assignment *);
 310    virtual void visit(ir_constant *);
 311    virtual void visit(ir_call *);
 312    virtual void visit(ir_return *);
 313    virtual void visit(ir_discard *);
 314    virtual void visit(ir_texture *);
 315    virtual void visit(ir_if *);
 316    virtual void visit(ir_emit_vertex *);
 317    virtual void visit(ir_end_primitive *);
 318    /*@}*/
 319
 320    src_reg result;
 321
 322    /* Regs for vertex results.  Generated at ir_variable visiting time
 323     * for the ir->location's used.
 324     */
 325    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 326    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 327    int *uniform_size;
 328    int *uniform_vector_size;
 329    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 330    int uniforms;
 331
 332    src_reg shader_start_time;
 333
 334    struct hash_table *variable_ht;
 335
 336    bool run(void);
 337    void fail(const char *msg, ...);
 338
 339    void setup_uniform_clipplane_values();
 340    void setup_uniform_values(ir_variable *ir);
 341    void setup_builtin_uniform_values(ir_variable *ir);
 342    int setup_uniforms(int payload_reg);
 343    bool reg_allocate_trivial();
 344    bool reg_allocate();
 345    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 346    int choose_spill_reg(struct ra_graph *g);
 347    void spill_reg(int spill_reg);
 348    void move_grf_array_access_to_scratch();
 349    void move_uniform_array_access_to_pull_constants();
 350    void move_push_constants_to_pull_constants();
 351    void split_uniform_registers();
 352    void pack_uniform_registers();
 353    void calculate_live_intervals();
 354    void invalidate_live_intervals();
 355    void split_virtual_grfs();
 356    bool opt_vector_float();
 357    bool opt_reduce_swizzle();
 358    bool dead_code_eliminate();
 359    bool virtual_grf_interferes(int a, int b);
 360    bool opt_copy_propagation(bool do_constant_prop = true);
 361    bool opt_cse_local(bblock_t *block);
 362    bool opt_cse();
 363    bool opt_algebraic();
 364    bool opt_register_coalesce();
 365    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 366    void opt_set_dependency_control();
 367    void opt_schedule_instructions();
 368
 369    vec4_instruction *emit(vec4_instruction *inst);
 370
 371    vec4_instruction *emit(enum opcode opcode);
 372    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 373    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 374                           const src_reg &src0);
 375    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 376                           const src_reg &src0, const src_reg &src1);
 377    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 378                           const src_reg &src0, const src_reg &src1,
 379                           const src_reg &src2);
 380
 381    vec4_instruction *emit_before(bblock_t *block,
 382                                  vec4_instruction *inst,
 383                                  vec4_instruction *new_inst);
 384
 385 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 386 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 387 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 388    EMIT1(MOV)
 389    EMIT1(NOT)
 390    EMIT1(RNDD)
 391    EMIT1(RNDE)
 392    EMIT1(RNDZ)
 393    EMIT1(FRC)
 394    EMIT1(F32TO16)
 395    EMIT1(F16TO32)
 396    EMIT2(ADD)
 397    EMIT2(MUL)
 398    EMIT2(MACH)
 399    EMIT2(MAC)
 400    EMIT2(AND)
 401    EMIT2(OR)
 402    EMIT2(XOR)
 403    EMIT2(DP3)
 404    EMIT2(DP4)
 405    EMIT2(DPH)
 406    EMIT2(SHL)
 407    EMIT2(SHR)
 408    EMIT2(ASR)
 409    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 410                          enum brw_conditional_mod condition);
 411    vec4_instruction *IF(src_reg src0, src_reg src1,
 412                         enum brw_conditional_mod condition);
 413    vec4_instruction *IF(enum brw_predicate predicate);
 414    EMIT1(PULL_CONSTANT_LOAD)
 415    EMIT1(SCRATCH_READ)
 416    EMIT2(SCRATCH_WRITE)
 417    EMIT3(LRP)
 418    EMIT1(BFREV)
 419    EMIT3(BFE)
 420    EMIT2(BFI1)
 421    EMIT3(BFI2)
 422    EMIT1(FBH)
 423    EMIT1(FBL)
 424    EMIT1(CBIT)
 425    EMIT3(MAD)
 426    EMIT2(ADDC)
 427    EMIT2(SUBB)
 428 #undef EMIT1
 429 #undef EMIT2
 430 #undef EMIT3
 431
 432    int implied_mrf_writes(vec4_instruction *inst);
 433
 434    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 435                                dst_reg dst,
 436                                src_reg src,
 437                                vec4_instruction *pre_rhs_inst,
 438                                vec4_instruction *last_rhs_inst);
 439
 440    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 441    void visit_instructions(const exec_list *list);
 442
 443    void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 444                     src_reg src0, src_reg src1, src_reg one);
 445
 446    void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
 447    void emit_if_gen6(ir_if *ir);
 448
 449    void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 450                     src_reg src0, src_reg src1);
 451
 452    void emit_lrp(const dst_reg &dst,
 453                  const src_reg &x, const src_reg &y, const src_reg &a);
 454
 455    void emit_block_move(dst_reg *dst, src_reg *src,
 456                         const struct glsl_type *type, brw_predicate predicate);
 457
 458    void emit_constant_values(dst_reg *dst, ir_constant *value);
 459
 460    /**
 461     * Emit the correct dot-product instruction for the type of arguments
 462     */
 463    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 464
 465    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 466                     dst_reg dst, src_reg src0);
 467
 468    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 469                     dst_reg dst, src_reg src0, src_reg src1);
 470
 471    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 472                  dst_reg dst, const src_reg &src);
 473
 474    src_reg fix_3src_operand(src_reg src);
 475
 476    void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 477                   const src_reg &src1 = src_reg());
 478    src_reg fix_math_operand(src_reg src);
 479
 480    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 481    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 482    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 483    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 484    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 485    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 486
 487    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 488    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
 489    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 490    void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 491
 492    void emit_ndc_computation();
 493    void emit_psiz_and_flags(dst_reg reg);
 494    void emit_clip_distances(dst_reg reg, int offset);
 495    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
 496    void emit_urb_slot(dst_reg reg, int varying);
 497
 498    void emit_shader_time_begin();
 499    void emit_shader_time_end();
 500    void emit_shader_time_write(enum shader_time_shader_type type,
 501                                src_reg value);
 502
 503    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 504                             dst_reg dst, src_reg offset, src_reg src0,
 505                             src_reg src1);
 506
 507    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 508                                   src_reg offset);
 509
 510    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 511                               src_reg *reladdr, int reg_offset);
 512    src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
 513                                     src_reg *reladdr, int reg_offset);
 514    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 515                           dst_reg dst,
 516                           src_reg orig_src,
 517                           int base_offset);
 518    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 519                            int base_offset);
 520    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 521                                 dst_reg dst,
 522                                 src_reg orig_src,
 523                                 int base_offset);
 524
 525    bool try_emit_mad(ir_expression *ir);
 526    bool try_emit_b2f_of_compare(ir_expression *ir);
 527    void resolve_ud_negate(src_reg *reg);
 528    void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
 529
 530    src_reg get_timestamp();
 531
 532    bool process_move_condition(ir_rvalue *ir);
 533
 534    void dump_instruction(backend_instruction *inst);
 535    void dump_instruction(backend_instruction *inst, FILE *file);
 536
 537    void visit_atomic_counter_intrinsic(ir_call *ir);
 538
 539 protected:
 540    void emit_vertex();
 541    void lower_attributes_to_hw_regs(const int *attribute_map,
 542                                     bool interleaved);
 543    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 544                                    int reg_node_count);
 545    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 546    virtual void assign_binding_table_offsets();
 547    virtual void setup_payload() = 0;
 548    virtual void emit_prolog() = 0;
 549    virtual void emit_program_code() = 0;
 550    virtual void emit_thread_end() = 0;
 551    virtual void emit_urb_write_header(int mrf) = 0;
 552    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 553    virtual int compute_array_stride(ir_dereference_array *ir);
 554
 555    const bool debug_flag;
 556
 557 private:
 558    /**
 559     * If true, then register allocation should fail instead of spilling.
 560     */
 561    const bool no_spills;
 562
 563    const shader_time_shader_type st_base;
 564    const shader_time_shader_type st_written;
 565    const shader_time_shader_type st_reset;
 566 };
 567
 568
 569 /**
 570  * The vertex shader code generator.
 571  *
 572  * Translates VS IR to actual i965 assembly code.
 573  */
 574 class vec4_generator
 575 {
 576 public:
 577    vec4_generator(struct brw_context *brw,
 578                   struct gl_shader_program *shader_prog,
 579                   struct gl_program *prog,
 580                   struct brw_vue_prog_data *prog_data,
 581                   void *mem_ctx,
 582                   bool debug_flag,
 583                   const char *stage_name,
 584                   const char *stage_abbrev);
 585    ~vec4_generator();
 586
 587    const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 588
 589 private:
 590    void generate_code(const cfg_t *cfg);
 591
 592    void generate_math1_gen4(vec4_instruction *inst,
 593                             struct brw_reg dst,
 594                             struct brw_reg src);
 595    void generate_math2_gen4(vec4_instruction *inst,
 596                             struct brw_reg dst,
 597                             struct brw_reg src0,
 598                             struct brw_reg src1);
 599    void generate_math_gen6(vec4_instruction *inst,
 600                            struct brw_reg dst,
 601                            struct brw_reg src0,
 602                            struct brw_reg src1);
 603
 604    void generate_tex(vec4_instruction *inst,
 605                      struct brw_reg dst,
 606                      struct brw_reg src,
 607                      struct brw_reg sampler_index);
 608
 609    void generate_vs_urb_write(vec4_instruction *inst);
 610    void generate_gs_urb_write(vec4_instruction *inst);
 611    void generate_gs_urb_write_allocate(vec4_instruction *inst);
 612    void generate_gs_thread_end(vec4_instruction *inst);
 613    void generate_gs_set_write_offset(struct brw_reg dst,
 614                                      struct brw_reg src0,
 615                                      struct brw_reg src1);
 616    void generate_gs_set_vertex_count(struct brw_reg dst,
 617                                      struct brw_reg src);
 618    void generate_gs_svb_write(vec4_instruction *inst,
 619                               struct brw_reg dst,
 620                               struct brw_reg src0,
 621                               struct brw_reg src1);
 622    void generate_gs_svb_set_destination_index(vec4_instruction *inst,
 623                                               struct brw_reg dst,
 624                                               struct brw_reg src);
 625    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
 626    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 627    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 628    void generate_gs_get_instance_id(struct brw_reg dst);
 629    void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
 630                                            struct brw_reg src0,
 631                                            struct brw_reg src1,
 632                                            struct brw_reg src2);
 633    void generate_gs_ff_sync(vec4_instruction *inst,
 634                             struct brw_reg dst,
 635                             struct brw_reg src0,
 636                             struct brw_reg src1);
 637    void generate_gs_set_primitive_id(struct brw_reg dst);
 638    void generate_oword_dual_block_offsets(struct brw_reg m1,
 639                                           struct brw_reg index);
 640    void generate_scratch_write(vec4_instruction *inst,
 641                                struct brw_reg dst,
 642                                struct brw_reg src,
 643                                struct brw_reg index);
 644    void generate_scratch_read(vec4_instruction *inst,
 645                               struct brw_reg dst,
 646                               struct brw_reg index);
 647    void generate_pull_constant_load(vec4_instruction *inst,
 648                                     struct brw_reg dst,
 649                                     struct brw_reg index,
 650                                     struct brw_reg offset);
 651    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 652                                          struct brw_reg dst,
 653                                          struct brw_reg surf_index,
 654                                          struct brw_reg offset);
 655    void generate_unpack_flags(vec4_instruction *inst,
 656                               struct brw_reg dst);
 657
 658    void generate_untyped_atomic(vec4_instruction *inst,
 659                                 struct brw_reg dst,
 660                                 struct brw_reg atomic_op,
 661                                 struct brw_reg surf_index);
 662
 663    void generate_untyped_surface_read(vec4_instruction *inst,
 664                                       struct brw_reg dst,
 665                                       struct brw_reg surf_index);
 666
 667    struct brw_context *brw;
 668
 669    struct brw_compile *p;
 670
 671    struct gl_shader_program *shader_prog;
 672    const struct gl_program *prog;
 673
 674    struct brw_vue_prog_data *prog_data;
 675
 676    void *mem_ctx;
 677    const char *stage_name;
 678    const char *stage_abbrev;
 679    const bool debug_flag;
 680 };
 681
 682 } /* namespace brw */
 683 #endif /* __cplusplus */
 684
 685 #endif /* BRW_VEC4_H */