src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31
  32 extern "C" {
  33 #include "brw_vs.h"
  34 #include "brw_context.h"
  35 #include "brw_eu.h"
  36 };
  37
  38 #include "glsl/ir.h"
  39
  40 namespace brw {
  41
  42 class dst_reg;
  43
  44 /**
  45  * Common helper for constructing swizzles.  When only a subset of
  46  * channels of a vec4 are used, we don't want to reference the other
  47  * channels, as that will tell optimization passes that those other
  48  * channels are used.
  49  */
  50 static int
  51 swizzle_for_size(int size)
  52 {
  53    int size_swizzles[4] = {
  54       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
  55       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
  56       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
  57       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
  58    };
  59
  60    assert((size >= 1) && (size <= 4));
  61    return size_swizzles[size - 1];
  62 }
  63
  64 enum register_file {
  65    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
  66    GRF = BRW_GENERAL_REGISTER_FILE,
  67    MRF = BRW_MESSAGE_REGISTER_FILE,
  68    IMM = BRW_IMMEDIATE_VALUE,
  69    HW_REG, /* a struct brw_reg */
  70    ATTR,
  71    UNIFORM, /* prog_data->params[hw_reg] */
  72    BAD_FILE
  73 };
  74
  75 class reg
  76 {
  77 public:
  78    /** Register file: ARF, GRF, MRF, IMM. */
  79    enum register_file file;
  80    /** virtual register number.  0 = fixed hw reg */
  81    int reg;
  82    /** Offset within the virtual register. */
  83    int reg_offset;
  84    /** Register type.  BRW_REGISTER_TYPE_* */
  85    int type;
  86    bool sechalf;
  87    struct brw_reg fixed_hw_reg;
  88    int smear; /* -1, or a channel of the reg to smear to all channels. */
  89
  90    /** Value for file == BRW_IMMMEDIATE_FILE */
  91    union {
  92       int32_t i;
  93       uint32_t u;
  94       float f;
  95    } imm;
  96 };
  97
  98 class src_reg : public reg
  99 {
 100 public:
 101    /* Callers of this ralloc-based new need not call delete. It's
 102     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 103    static void* operator new(size_t size, void *ctx)
 104    {
 105       void *node;
 106
 107       node = ralloc_size(ctx, size);
 108       assert(node != NULL);
 109
 110       return node;
 111    }
 112
 113    void init()
 114    {
 115       memset(this, 0, sizeof(*this));
 116
 117       this->file = BAD_FILE;
 118    }
 119
 120    src_reg(register_file file, int reg, const glsl_type *type)
 121    {
 122       init();
 123
 124       this->file = file;
 125       this->reg = reg;
 126       if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
 127          this->swizzle = swizzle_for_size(type->vector_elements);
 128       else
 129          this->swizzle = SWIZZLE_XYZW;
 130    }
 131
 132    /** Generic unset register constructor. */
 133    src_reg()
 134    {
 135       init();
 136    }
 137
 138    src_reg(float f)
 139    {
 140       init();
 141
 142       this->file = IMM;
 143       this->type = BRW_REGISTER_TYPE_F;
 144       this->imm.f = f;
 145    }
 146
 147    src_reg(uint32_t u)
 148    {
 149       init();
 150
 151       this->file = IMM;
 152       this->type = BRW_REGISTER_TYPE_UD;
 153       this->imm.f = u;
 154    }
 155
 156    src_reg(int32_t i)
 157    {
 158       init();
 159
 160       this->file = IMM;
 161       this->type = BRW_REGISTER_TYPE_D;
 162       this->imm.i = i;
 163    }
 164
 165    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 166
 167    explicit src_reg(dst_reg reg);
 168
 169    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 170    bool negate;
 171    bool abs;
 172
 173    src_reg *reladdr;
 174 };
 175
 176 class dst_reg : public reg
 177 {
 178 public:
 179    /* Callers of this ralloc-based new need not call delete. It's
 180     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 181    static void* operator new(size_t size, void *ctx)
 182    {
 183       void *node;
 184
 185       node = ralloc_size(ctx, size);
 186       assert(node != NULL);
 187
 188       return node;
 189    }
 190
 191    void init()
 192    {
 193       memset(this, 0, sizeof(*this));
 194       this->file = BAD_FILE;
 195       this->writemask = WRITEMASK_XYZW;
 196    }
 197
 198    dst_reg()
 199    {
 200       init();
 201    }
 202
 203    dst_reg(register_file file, int reg)
 204    {
 205       init();
 206
 207       this->file = file;
 208       this->reg = reg;
 209    }
 210
 211    dst_reg(struct brw_reg reg)
 212    {
 213       init();
 214
 215       this->file = HW_REG;
 216       this->fixed_hw_reg = reg;
 217    }
 218
 219    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 220
 221    explicit dst_reg(src_reg reg);
 222
 223    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 224
 225    src_reg *reladdr;
 226 };
 227
 228 class vec4_instruction : public exec_node {
 229 public:
 230    /* Callers of this ralloc-based new need not call delete. It's
 231     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 232    static void* operator new(size_t size, void *ctx)
 233    {
 234       void *node;
 235
 236       node = rzalloc_size(ctx, size);
 237       assert(node != NULL);
 238
 239       return node;
 240    }
 241
 242    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 243                     dst_reg dst = dst_reg(),
 244                     src_reg src0 = src_reg(),
 245                     src_reg src1 = src_reg(),
 246                     src_reg src2 = src_reg());
 247
 248    struct brw_reg get_dst(void);
 249    struct brw_reg get_src(int i);
 250
 251    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 252    dst_reg dst;
 253    src_reg src[3];
 254
 255    bool saturate;
 256    bool predicate_inverse;
 257    uint32_t predicate;
 258
 259    int conditional_mod; /**< BRW_CONDITIONAL_* */
 260
 261    int sampler;
 262    int target; /**< MRT target. */
 263    bool shadow_compare;
 264
 265    bool eot;
 266    bool header_present;
 267    int mlen; /**< SEND message length */
 268    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 269
 270    uint32_t offset; /* spill/unspill offset */
 271    /** @{
 272     * Annotation for the generated IR.  One of the two can be set.
 273     */
 274    ir_instruction *ir;
 275    const char *annotation;
 276 };
 277
 278 class vec4_visitor : public ir_visitor
 279 {
 280 public:
 281    vec4_visitor(struct brw_vs_compile *c,
 282                 struct gl_shader_program *prog, struct brw_shader *shader);
 283    ~vec4_visitor();
 284
 285    dst_reg dst_null_f()
 286    {
 287       return dst_reg(brw_null_reg());
 288    }
 289
 290    dst_reg dst_null_d()
 291    {
 292       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 293    }
 294
 295    struct brw_context *brw;
 296    const struct gl_vertex_program *vp;
 297    struct intel_context *intel;
 298    struct gl_context *ctx;
 299    struct brw_vs_compile *c;
 300    struct brw_vs_prog_data *prog_data;
 301    struct brw_compile *p;
 302    struct brw_shader *shader;
 303    struct gl_shader_program *prog;
 304    void *mem_ctx;
 305    exec_list instructions;
 306
 307    char *fail_msg;
 308    bool failed;
 309
 310    /**
 311     * GLSL IR currently being processed, which is associated with our
 312     * driver IR instructions for debugging purposes.
 313     */
 314    ir_instruction *base_ir;
 315    const char *current_annotation;
 316
 317    int *virtual_grf_sizes;
 318    int virtual_grf_count;
 319    int virtual_grf_array_size;
 320    int first_non_payload_grf;
 321    int *virtual_grf_def;
 322    int *virtual_grf_use;
 323    bool live_intervals_valid;
 324
 325    dst_reg *variable_storage(ir_variable *var);
 326
 327    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 328
 329    src_reg src_reg_for_float(float val);
 330
 331    /**
 332     * \name Visit methods
 333     *
 334     * As typical for the visitor pattern, there must be one \c visit method for
 335     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 336     * the hierarchy should not have \c visit methods.
 337     */
 338    /*@{*/
 339    virtual void visit(ir_variable *);
 340    virtual void visit(ir_loop *);
 341    virtual void visit(ir_loop_jump *);
 342    virtual void visit(ir_function_signature *);
 343    virtual void visit(ir_function *);
 344    virtual void visit(ir_expression *);
 345    virtual void visit(ir_swizzle *);
 346    virtual void visit(ir_dereference_variable  *);
 347    virtual void visit(ir_dereference_array *);
 348    virtual void visit(ir_dereference_record *);
 349    virtual void visit(ir_assignment *);
 350    virtual void visit(ir_constant *);
 351    virtual void visit(ir_call *);
 352    virtual void visit(ir_return *);
 353    virtual void visit(ir_discard *);
 354    virtual void visit(ir_texture *);
 355    virtual void visit(ir_if *);
 356    /*@}*/
 357
 358    src_reg result;
 359
 360    /* Regs for vertex results.  Generated at ir_variable visiting time
 361     * for the ir->location's used.
 362     */
 363    dst_reg output_reg[BRW_VERT_RESULT_MAX];
 364    const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
 365    int uniform_size[MAX_UNIFORMS];
 366    int uniform_vector_size[MAX_UNIFORMS];
 367    int uniforms;
 368
 369    struct hash_table *variable_ht;
 370
 371    bool run(void);
 372    void fail(const char *msg, ...);
 373
 374    int virtual_grf_alloc(int size);
 375    int setup_uniform_values(int loc, const glsl_type *type);
 376    void setup_builtin_uniform_values(ir_variable *ir);
 377    int setup_attributes(int payload_reg);
 378    int setup_uniforms(int payload_reg);
 379    void setup_payload();
 380    void reg_allocate_trivial();
 381    void reg_allocate();
 382    void move_grf_array_access_to_scratch();
 383    void move_uniform_array_access_to_pull_constants();
 384    void split_uniform_registers();
 385    void pack_uniform_registers();
 386    void calculate_live_intervals();
 387    bool dead_code_eliminate();
 388    bool virtual_grf_interferes(int a, int b);
 389
 390    vec4_instruction *emit(vec4_instruction *inst);
 391
 392    vec4_instruction *emit(enum opcode opcode);
 393
 394    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 395
 396    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 397                           src_reg src0, src_reg src1);
 398
 399    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 400                           src_reg src0, src_reg src1, src_reg src2);
 401
 402    vec4_instruction *emit_before(vec4_instruction *inst,
 403                                  vec4_instruction *new_inst);
 404
 405    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 406    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 407    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 408    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 409    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 410    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 411    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 412    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 413    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 414    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 415    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 416    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 417    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 418    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 419    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 420    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 421                          uint32_t condition);
 422    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 423    vec4_instruction *IF(uint32_t predicate);
 424    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 425    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 426    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 427
 428    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 429                                dst_reg dst,
 430                                src_reg src,
 431                                vec4_instruction *pre_rhs_inst,
 432                                vec4_instruction *last_rhs_inst);
 433
 434    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 435    void visit_instructions(const exec_list *list);
 436
 437    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 438    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 439    void emit_if_gen6(ir_if *ir);
 440
 441    void emit_block_move(dst_reg *dst, src_reg *src,
 442                         const struct glsl_type *type, uint32_t predicate);
 443
 444    void emit_constant_values(dst_reg *dst, ir_constant *value);
 445
 446    /**
 447     * Emit the correct dot-product instruction for the type of arguments
 448     */
 449    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 450
 451    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 452                     dst_reg dst, src_reg src0);
 453
 454    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 455                     dst_reg dst, src_reg src0, src_reg src1);
 456
 457    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 458                  dst_reg dst, const src_reg &src);
 459
 460    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 461    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 462    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 463    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 464    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 465    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 466
 467    void emit_ndc_computation();
 468    void emit_psiz_and_flags(struct brw_reg reg);
 469    void emit_clip_distances(struct brw_reg reg, int offset);
 470    void emit_urb_slot(int mrf, int vert_result);
 471    void emit_urb_writes(void);
 472
 473    src_reg get_scratch_offset(vec4_instruction *inst,
 474                               src_reg *reladdr, int reg_offset);
 475    src_reg get_pull_constant_offset(vec4_instruction *inst,
 476                                     src_reg *reladdr, int reg_offset);
 477    void emit_scratch_read(vec4_instruction *inst,
 478                           dst_reg dst,
 479                           src_reg orig_src,
 480                           int base_offset);
 481    void emit_scratch_write(vec4_instruction *inst,
 482                            src_reg temp,
 483                            dst_reg orig_dst,
 484                            int base_offset);
 485    void emit_pull_constant_load(vec4_instruction *inst,
 486                                 dst_reg dst,
 487                                 src_reg orig_src,
 488                                 int base_offset);
 489
 490    GLboolean try_emit_sat(ir_expression *ir);
 491
 492    bool process_move_condition(ir_rvalue *ir);
 493
 494    void generate_code();
 495    void generate_vs_instruction(vec4_instruction *inst,
 496                                 struct brw_reg dst,
 497                                 struct brw_reg *src);
 498
 499    void generate_math1_gen4(vec4_instruction *inst,
 500                             struct brw_reg dst,
 501                             struct brw_reg src);
 502    void generate_math1_gen6(vec4_instruction *inst,
 503                             struct brw_reg dst,
 504                             struct brw_reg src);
 505    void generate_math2_gen4(vec4_instruction *inst,
 506                             struct brw_reg dst,
 507                             struct brw_reg src0,
 508                             struct brw_reg src1);
 509    void generate_math2_gen6(vec4_instruction *inst,
 510                             struct brw_reg dst,
 511                             struct brw_reg src0,
 512                             struct brw_reg src1);
 513
 514    void generate_urb_write(vec4_instruction *inst);
 515    void generate_oword_dual_block_offsets(struct brw_reg m1,
 516                                           struct brw_reg index);
 517    void generate_scratch_write(vec4_instruction *inst,
 518                                struct brw_reg dst,
 519                                struct brw_reg src,
 520                                struct brw_reg index);
 521    void generate_scratch_read(vec4_instruction *inst,
 522                               struct brw_reg dst,
 523                               struct brw_reg index);
 524    void generate_pull_constant_load(vec4_instruction *inst,
 525                                     struct brw_reg dst,
 526                                     struct brw_reg index);
 527 };
 528
 529 } /* namespace brw */
 530
 531 #endif /* BRW_VEC4_H */