src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31
  32 extern "C" {
  33 #include "brw_vs.h"
  34 #include "brw_context.h"
  35 #include "brw_eu.h"
  36 };
  37
  38 #include "../glsl/ir.h"
  39
  40 namespace brw {
  41
  42 class dst_reg;
  43
  44 /**
  45  * Common helper for constructing swizzles.  When only a subset of
  46  * channels of a vec4 are used, we don't want to reference the other
  47  * channels, as that will tell optimization passes that those other
  48  * channels are used.
  49  */
  50 static int
  51 swizzle_for_size(int size)
  52 {
  53    int size_swizzles[4] = {
  54       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
  55       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
  56       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
  57       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
  58    };
  59
  60    assert((size >= 1) && (size <= 4));
  61    return size_swizzles[size - 1];
  62 }
  63
  64 enum register_file {
  65    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
  66    GRF = BRW_GENERAL_REGISTER_FILE,
  67    MRF = BRW_MESSAGE_REGISTER_FILE,
  68    IMM = BRW_IMMEDIATE_VALUE,
  69    HW_REG, /* a struct brw_reg */
  70    ATTR,
  71    UNIFORM, /* prog_data->params[hw_reg] */
  72    BAD_FILE
  73 };
  74
  75 class reg
  76 {
  77 public:
  78    /** Register file: ARF, GRF, MRF, IMM. */
  79    enum register_file file;
  80    /** virtual register number.  0 = fixed hw reg */
  81    int reg;
  82    /** Offset within the virtual register. */
  83    int reg_offset;
  84    /** Register type.  BRW_REGISTER_TYPE_* */
  85    int type;
  86    bool sechalf;
  87    struct brw_reg fixed_hw_reg;
  88    int smear; /* -1, or a channel of the reg to smear to all channels. */
  89
  90    /** Value for file == BRW_IMMMEDIATE_FILE */
  91    union {
  92       int32_t i;
  93       uint32_t u;
  94       float f;
  95    } imm;
  96 };
  97
  98 class src_reg : public reg
  99 {
 100 public:
 101    /* Callers of this ralloc-based new need not call delete. It's
 102     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 103    static void* operator new(size_t size, void *ctx)
 104    {
 105       void *node;
 106
 107       node = ralloc_size(ctx, size);
 108       assert(node != NULL);
 109
 110       return node;
 111    }
 112
 113    void init()
 114    {
 115       memset(this, 0, sizeof(*this));
 116
 117       this->file = BAD_FILE;
 118    }
 119
 120    src_reg(register_file file, int reg, const glsl_type *type)
 121    {
 122       init();
 123
 124       this->file = file;
 125       this->reg = reg;
 126       if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
 127          this->swizzle = swizzle_for_size(type->vector_elements);
 128       else
 129          this->swizzle = SWIZZLE_XYZW;
 130    }
 131
 132    /** Generic unset register constructor. */
 133    src_reg()
 134    {
 135       init();
 136    }
 137
 138    src_reg(float f)
 139    {
 140       init();
 141
 142       this->file = IMM;
 143       this->type = BRW_REGISTER_TYPE_F;
 144       this->imm.f = f;
 145    }
 146
 147    src_reg(uint32_t u)
 148    {
 149       init();
 150
 151       this->file = IMM;
 152       this->type = BRW_REGISTER_TYPE_UD;
 153       this->imm.f = u;
 154    }
 155
 156    src_reg(int32_t i)
 157    {
 158       init();
 159
 160       this->file = IMM;
 161       this->type = BRW_REGISTER_TYPE_D;
 162       this->imm.i = i;
 163    }
 164
 165    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 166
 167    explicit src_reg(dst_reg reg);
 168
 169    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 170    bool negate;
 171    bool abs;
 172 };
 173
 174 class dst_reg : public reg
 175 {
 176 public:
 177    /* Callers of this ralloc-based new need not call delete. It's
 178     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 179    static void* operator new(size_t size, void *ctx)
 180    {
 181       void *node;
 182
 183       node = ralloc_size(ctx, size);
 184       assert(node != NULL);
 185
 186       return node;
 187    }
 188
 189    void init()
 190    {
 191       memset(this, 0, sizeof(*this));
 192       this->file = BAD_FILE;
 193       this->writemask = WRITEMASK_XYZW;
 194    }
 195
 196    dst_reg()
 197    {
 198       init();
 199    }
 200
 201    dst_reg(register_file file, int reg)
 202    {
 203       init();
 204
 205       this->file = file;
 206       this->reg = reg;
 207    }
 208
 209    dst_reg(struct brw_reg reg)
 210    {
 211       init();
 212
 213       this->file = HW_REG;
 214       this->fixed_hw_reg = reg;
 215    }
 216
 217    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 218
 219    explicit dst_reg(src_reg reg);
 220
 221    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 222 };
 223
 224 class vec4_instruction : public exec_node {
 225 public:
 226    /* Callers of this ralloc-based new need not call delete. It's
 227     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 228    static void* operator new(size_t size, void *ctx)
 229    {
 230       void *node;
 231
 232       node = rzalloc_size(ctx, size);
 233       assert(node != NULL);
 234
 235       return node;
 236    }
 237
 238    struct brw_reg get_dst(void);
 239    struct brw_reg get_src(int i);
 240
 241    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 242    dst_reg dst;
 243    src_reg src[3];
 244
 245    bool saturate;
 246    bool predicate_inverse;
 247    uint32_t predicate;
 248
 249    int conditional_mod; /**< BRW_CONDITIONAL_* */
 250
 251    int sampler;
 252    int target; /**< MRT target. */
 253    bool shadow_compare;
 254
 255    bool eot;
 256    bool header_present;
 257    int mlen; /**< SEND message length */
 258    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 259
 260    uint32_t offset; /* spill/unspill offset */
 261    /** @{
 262     * Annotation for the generated IR.  One of the two can be set.
 263     */
 264    ir_instruction *ir;
 265    const char *annotation;
 266 };
 267
 268 class vec4_visitor : public ir_visitor
 269 {
 270 public:
 271    vec4_visitor(struct brw_vs_compile *c,
 272                 struct gl_shader_program *prog, struct brw_shader *shader);
 273    ~vec4_visitor();
 274
 275    dst_reg dst_null_f()
 276    {
 277       return dst_reg(brw_null_reg());
 278    }
 279
 280    dst_reg dst_null_d()
 281    {
 282       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 283    }
 284
 285    dst_reg dst_null_cmp()
 286    {
 287       if (intel->gen > 4)
 288          return dst_null_d();
 289       else
 290          return dst_null_f();
 291    }
 292
 293    struct brw_context *brw;
 294    const struct gl_vertex_program *vp;
 295    struct intel_context *intel;
 296    struct gl_context *ctx;
 297    struct brw_vs_compile *c;
 298    struct brw_vs_prog_data *prog_data;
 299    struct brw_compile *p;
 300    struct brw_shader *shader;
 301    struct gl_shader_program *prog;
 302    void *mem_ctx;
 303    exec_list instructions;
 304
 305    char *fail_msg;
 306    bool failed;
 307
 308    /**
 309     * GLSL IR currently being processed, which is associated with our
 310     * driver IR instructions for debugging purposes.
 311     */
 312    ir_instruction *base_ir;
 313    const char *current_annotation;
 314
 315    int *virtual_grf_sizes;
 316    int virtual_grf_count;
 317    int virtual_grf_array_size;
 318    int first_non_payload_grf;
 319
 320    dst_reg *variable_storage(ir_variable *var);
 321
 322    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 323
 324    src_reg src_reg_for_float(float val);
 325
 326    /**
 327     * \name Visit methods
 328     *
 329     * As typical for the visitor pattern, there must be one \c visit method for
 330     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 331     * the hierarchy should not have \c visit methods.
 332     */
 333    /*@{*/
 334    virtual void visit(ir_variable *);
 335    virtual void visit(ir_loop *);
 336    virtual void visit(ir_loop_jump *);
 337    virtual void visit(ir_function_signature *);
 338    virtual void visit(ir_function *);
 339    virtual void visit(ir_expression *);
 340    virtual void visit(ir_swizzle *);
 341    virtual void visit(ir_dereference_variable  *);
 342    virtual void visit(ir_dereference_array *);
 343    virtual void visit(ir_dereference_record *);
 344    virtual void visit(ir_assignment *);
 345    virtual void visit(ir_constant *);
 346    virtual void visit(ir_call *);
 347    virtual void visit(ir_return *);
 348    virtual void visit(ir_discard *);
 349    virtual void visit(ir_texture *);
 350    virtual void visit(ir_if *);
 351    /*@}*/
 352
 353    src_reg result;
 354
 355    /* Regs for vertex results.  Generated at ir_variable visiting time
 356     * for the ir->location's used.
 357     */
 358    dst_reg output_reg[VERT_RESULT_MAX];
 359    int uniform_size[MAX_UNIFORMS];
 360    int uniforms;
 361
 362    struct hash_table *variable_ht;
 363
 364    bool run(void);
 365    void fail(const char *msg, ...);
 366
 367    int virtual_grf_alloc(int size);
 368    int setup_uniform_values(int loc, const glsl_type *type);
 369    void setup_builtin_uniform_values(ir_variable *ir);
 370    int setup_attributes(int payload_reg);
 371    int setup_uniforms(int payload_reg);
 372    void setup_payload();
 373    void reg_allocate_trivial();
 374    void reg_allocate();
 375
 376    vec4_instruction *emit(enum opcode opcode);
 377
 378    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 379
 380    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 381                           src_reg src0, src_reg src1);
 382
 383    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 384                           src_reg src0, src_reg src1, src_reg src2);
 385
 386    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 387    void visit_instructions(const exec_list *list);
 388
 389    void emit_bool_to_cond_code(ir_rvalue *ir);
 390    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 391    void emit_if_gen6(ir_if *ir);
 392
 393    void emit_block_move(ir_assignment *ir);
 394
 395    /**
 396     * Emit the correct dot-product instruction for the type of arguments
 397     */
 398    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 399
 400    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 401                     dst_reg dst, src_reg src0);
 402
 403    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 404                     dst_reg dst, src_reg src0, src_reg src1);
 405
 406    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 407                  dst_reg dst, const src_reg &src);
 408
 409    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 410    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 411    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 412    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 413    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 414    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 415
 416    int emit_vue_header_gen6(int header_mrf);
 417    int emit_vue_header_gen4(int header_mrf);
 418    void emit_urb_writes(void);
 419
 420    GLboolean try_emit_sat(ir_expression *ir);
 421
 422    bool process_move_condition(ir_rvalue *ir);
 423
 424    void generate_code();
 425    void generate_vs_instruction(vec4_instruction *inst,
 426                                 struct brw_reg dst,
 427                                 struct brw_reg *src);
 428    void generate_math1_gen4(vec4_instruction *inst,
 429                             struct brw_reg dst,
 430                             struct brw_reg src);
 431    void generate_math1_gen6(vec4_instruction *inst,
 432                             struct brw_reg dst,
 433                             struct brw_reg src);
 434    void generate_urb_write(vec4_instruction *inst);
 435 };
 436
 437 } /* namespace brw */
 438
 439 #endif /* BRW_VEC4_H */